Semiconductor integrated circuit with encryption/decryption function

i

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having an encryption / decryptor function for protecting input / output data transmitted on an internal bus.

The use of plastic cards such as credit cards or bank cards for carrying out, for example, financial transactions, is becoming more and more widespread. As is well known, a plastic card including a magnetic card cannot store a large amount of data, and has a security problem. As semiconductor technology has been remarkably developed, the size of integrated circuits has been greatly reduced. Consequently, plastic cards comprising a chip of integrated circuits (called chip cards) have been developed to replace the conventional magnetic card. The smart card can store a very large amount of data, and has advantages such as improved security and durability. Therefore, the smart card has been used for various purposes, for example as an identification card, as a health insurance card, and as a bank card.

Since important data, such as a credit card number, resident registration number, bank account number, and code word, are stored in the integrated circuit of a smart card, security concerning the data stored in the integrated circuit is very important.

FIG. 1 is a diagram of an example of an integrated circuit for a smart card. An integrated circuit 10 in the smart card comprises a central processing unit (CPU) or a processor 11 such as a microprocessor, a random access memory (RAM) 13, a read only memory (ROM) 14, a programmable and erasable read only memory electrically (EEPROM) 15, and an input / output control device 12. The circuit blocks in integrated circuit 10 are connected to each other through a system bus 16, thereby transmitting and receiving data, programs, and control codes.

Those familiar with the art of integrated circuits can easily distinguish blocks of circuits from a system bus and control data loaded into the system bus using predetermined means. If the data transmitted and received among the circuit blocks is exposed to a hacker and violated, a serious social problem is encountered.

Therefore, it is highly desirable that a smart card which is used as a credit card, as a health insurance card, and as an identification card, has functions which can maintain the security of data transmitted and received between. internal circuit blocks.

A semiconductor integrated circuit is provided, which comprises: a first circuit; a second circuit; a data bus; and first and second encryption / decryption circuits for encrypting / decrypting data transmitted between the first and second circuits on the data bus, wherein the first encryption / decryption circuit serves to encrypt data output from the first circuit, outputting the encrypted data to the data bus, decrypting and encrypting the data received from the second encryption / decryption circuit, and outputting the decrypted data to the first circuit; and the second encryption / decryption circuit serves to decrypt encrypted data received from the first encryption / decryption circuit, to output the decrypted data to the second circuit, to encrypt the data output from the second circuit, and to output the data. encrypted data to the data bus.

According to an embodiment of the present invention, the semiconductor integrated circuit further comprises a random number generator for generating a random number in response to a clock signal, and outputting the random number to the first encryption / decryption circuit and to the second encryption / decryption circuit for controlling the execution of the encryption and decryption operations. The random number generator is included in a circuit block associated with one of the first encryption / decryption circuit and the second encryption / decryption circuit.

Also provided is a semiconductor integrated circuit, which comprises: a first circuit block including a processor circuit; a second circuit block comprising a storage circuit; and a data bus for transmitting data between the first and second circuit blocks, wherein the first circuit block further comprises a random number generator for generating a random number in response to a clock signal, and a first encryption / decryption circuit for encrypting data output from the processor circuit according to a random number generated by the random number generator, outputting the encrypted data to the data bus, decrypting the encrypted data received from the storage circuit on the data bus, and outputting the decrypted data to the processor circuit; and wherein the second circuit block further comprises a second encryption / decryption circuit for decrypting the encrypted data received from the processor circuit on the data bus based on a random number generated from the random number generator, deliver the decrypted data to the storage circuit, encrypt the data delivered at the output of the storage circuit according to the random number, and outputting the encrypted data to the data bus.

A semiconductor integrated circuit is also provided, which comprises: a first circuit; a second circuit; a data bus for transmitting a plurality of data bits between the first and second circuits; a random number generator for generating a random number in response to a clock signal; a first scrambler for changing an array of the plurality of data bits output from the first circuit as a function of the random number, outputting the changed array to the data bus, re-establishing an array of the plurality of data bits received from the second circuit on the data bus into an original grouping according to the random number, and delivering the restored grouping to the first circuit, and a second scrambler for restoring the grouping of the plurality of data bits received from the first circuit on the data bus to an original grouping according to the random number, outputting the restored grouping to the second circuit, changing the grouping of the plurality of data bits outputted from the second circuit as a function of the random number, and outputting the changed grouping to the data bus.

According to one embodiment of the present invention, the plurality of data bits are N bits, N being an integer. The first scrambler comprises: a first generator for generating first selection signals corresponding to the random number; and a first bit grouping changer for changing the grouping of the plurality of data bits outputted from the first circuit according to the first selection signals, outputting the changed grouping to the data bus, restoring the grouping of the plurality bits of data received from the second circuit on the data bus into the original array according to the first select signals, and output the restored array to the first circuit. The first bit grouping changer includes a plurality of first switching circuits corresponding to transmitting and receiving the plurality of data bits, respectively, each of the plurality of first switching circuits for connecting a corresponding bit of the plurality of data bits input / output to / from the first one-bit circuit corresponding to the first selection signals among the bits of the data bus. Each of the plurality of first switching circuits: outputs a corresponding bit of the plurality of data bits output from the first circuit when data is output from the first circuit, in the form of a bit corresponding to the first selection signals from among the bits of the data bus , and outputs a bit corresponding to the first selection signals among the data bits loaded into the data bus when data is input from the data bus, in the form of a corresponding bit of the plurality of data bits inputted to the first circuit. Each of the plurality of first switching circuits includes a plurality of switches which are connected between a plurality of data bus bits and a corresponding one of the plurality of data bits input / output to / from the first circuit, respectively , for operation in response to the first selection signals. The second scrambler comprises: a second generator for generating second selection signals corresponding to the random number; and a second bit grouping changer for restoring the grouping of the plurality of data bits received from the first circuit on the data bus to the original grouping according to the second selection signals, outputting the reestablished grouping to the second circuit, changing grouping data bits outputted from the second circuit according to the second selection signals, and outputting the changed grouping to the data bus. The first selection signals and the second selection signals are identical to each other. The second bit grouping changer includes a plurality of second switching circuits corresponding to the transmitted and received data bits, each of the second switching circuits serving to connect a corresponding bit among the data bits input / output to / from the second circuit with bits corresponding to the second selection signals among the bits of the data bus.

According to one embodiment of the present invention, each of the second switching circuits: outputs a corresponding bit among the data bits output from the second circuit when data is output from the second circuit, in the form of a bit corresponding to the second selection signals among the bits of the data bus, and outputs a bit corresponding to the second selection signals among the data bits loaded on the data bus when data is input from the data bus, as a corresponding bit among the data bits input to the second circuit. Each of the second switching circuits includes a plurality of switches which are connected between a plurality of bits of the data bus and a corresponding bit of the data bits input / output to / from the second circuit, respectively, for responsive operation. to the second selection signals.

A smart card is also provided which comprises: a first circuit; a second circuit; a data bus for transmitting a plurality of data bits between the first and second circuits; a random number generator for generating a random number in response to a clock signal; a first scrambler for changing an array of the plurality of data bits outputted from the first circuit according to the random number, outputting the changed array to the data bus, re-establishing an array of the plurality of data bits received from the second circuit on the data bus into an original array according to the random number, and output the restored array to the first circuit; and a second scrambler for restoring an array of the plurality of data bits received from the first circuit on the data bus to an original array according to the random number, outputting the restored data to the second circuit, changing an array of the plurality of data bits output from the second circuit as a function of the random number, and output the changed grouping to the data bus.

A semiconductor integrated circuit is also provided, which comprises: a first circuit; a second circuit; a data bus for transmitting a plurality of data bits between the first and second circuits; a random number generator for generating a random number in response to a clock signal; a first scrambler for partially changing an array of the plurality of data bits output from the first circuit according to the random number and outputting the changed array to the data bus; and a second scrambler for restoring the data bits of the array whose array has been changed by the first scrambler, among the data bits input from the first circuit through the data bus according to the random number, into a cluster original, deliver the re-established grouping to the second circuit, partially change a grouping among the data bits delivered at the output of the second circuit as a function of the random number, and outputting the changed grouping to the data bus, in which the first scrambler resets certain bits whose grouping was changed by the second scrambler, among the data bits input from the second circuit on the data bus according to the number random, in an original bundle, and delivers the restored bundle to the first circuit.

According to one embodiment of the present invention, the first scrambler comprises: a first generator for generating first selection signals corresponding to the random number; and a first bit grouping changer for partially changing the grouping of data bits output from the first circuit as a function of the first selection signals, outputting the changed grouping to the data bus, restoring the grouping of certain bits of which the grouping has been changed by the second scrambler, among data bits entered from the second circuit block by 1¹ intermediary of the data bus according to the first selection signals, in an original grouping, and delivering the restored grouping to the first circuit. The second scrambler comprises: a second generator for generating second selection signals corresponding to the random number; and a second bit grouping changer for restoring the grouping of certain bits whose grouping was changed by the first scrambler, among the data bits input from the first circuit on the data bus to the original grouping according to the second signals selection, delivering the restored grouping to the second circuit, partially changing the grouping of data bits delivered at the output of the second circuit as a function of the second selection signals, and outputting the changed grouping to the data bus. The data transmitted and received between the first and second circuits via the data bus comprises N bits, and the bits whose bit array has been changed / restored by the first and second bit pool changers, among the data. with N bits, are K lower order bits (K <N), K and N being integers. The first bit grouping changer includes a plurality of first switching circuits corresponding to bits of the K-bit data, each of the first switching circuits for connecting bits corresponding to lower order K bits of the input data. / output to / from the first circuit, to a bit corresponding to the first selection signals among K lower order bits of the data bus. Each of the first switching circuits: outputs a corresponding bit among K lower order bits of data output from the first circuit when data is output from the first circuit, in the form of a bit corresponding to the first selection signals among K bits lower order of the data bus, and outputs a bit corresponding to the first selection signals from among data bits loaded onto the data bus when data is input from the data bus, as a corresponding bit among data bits inputted to the data bus. first circuit. Each of the first switching circuits comprises a plurality of switches which are connected between K lower order bits of the data bus and a corresponding bit of K lower order bits of the data input / output to / from the first circuit, respectively, for operation in response to the first selection signals. The second bit array changer includes a plurality of second switching circuits corresponding to K-bit data, respectively, each of the second switching circuits for connecting a corresponding one of K lower order bits of input data / output to / from the second circuit, to one bit corresponding to the second selection signals among K lower order bits of the data bus. Each of the second switching circuits: outputs a corresponding bit among K lower order bits of data ίο outputted from the second circuit when data is output from the second circuit, in the form of a bit corresponding to the second selection signals among K bits lower order of the data bus, and outputs a bit corresponding to the second selection signals from among K lower order bits of data loaded onto the data bus when data is input from the data bus, in the form of a corresponding bit from among K order bits lower data input in the second circuit. Each of the second switching circuits comprises a plurality of switches which are connected between K lower order bits of the data bus and a corresponding one among K lower order bits of data input / output to / from the second circuit, respectively, for operation in response to the second selection signals.

A method is provided for transmitting internal data of a semiconductor memory device comprising a chip consisting of a first circuit block, a second circuit block, and a data bus for transmitting data between the first and second memory blocks. circuits, the method comprising the steps of: outputting data using the first circuit block; changing a bit array of the data output from the first circuit block; transmitting the data whose bit grouping is changed to the data bus; restoring an array of data bits loaded on the data bus to an original array; and outputting the data whose bit array is restored to the second circuit block.

According to an embodiment of the present invention, the bit grouping changing step changes some bits of the data outputted from the second circuit block, and the bit grouping restoring step resets the bits of which the bit grouping was changed during the step of changing the bit grouping, among the data loaded in the data bus, to the original grouping. The method further comprises the following steps: outputting data using the second circuit block; changing a bit array of the data output from the second circuit; transmitting the data whose bit grouping is changed on the data bus; restoring an array of data bits loaded on the data bus to an original array; and inputting the data whose bit array is restored to the first circuit block. The step of changing the data bit grouping changes some of the data outputted from the second circuit block, and the bit setting step resets the bits whose bit grouping was changed during the process. step of changing the bit grouping to the original one.

The above objects and advantages of the present invention will become more evident from a detailed description of preferred embodiments thereof, with reference to the accompanying drawings, in which:

FIG. 1 is a diagram for an example of an integrated circuit which can be used in a smart card;

FIG. 2 is a diagram illustrating a structure of an integrated circuit for a smart card according to a preferred embodiment of the present invention;

Figure 3 is a block diagram illustrating architectures of the first and second scramblers of Figure 2 according to embodiments of the present invention;

FIG. 4 is a general diagram illustrating. an architecture of the first and second bit array changers of Figure 3 according to embodiments of the present invention;

Fig. 5 is a diagram illustrating a circuit architecture of the switching parts of Fig. 4 according to an embodiment of the present invention;

Fig. 6A is an exemplary graph showing changes in the position of data bits as a function of random numbers generated from a random number generator when data output from a CPU is transmitted to RAM; and Fig. 6B is an exemplary graph showing changes in the position of data bits as a function of a random number generated from a random number generator when data output from a RAM is transmitted to a random number generator. central unit.

The present invention will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, this invention can be practiced in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are given so that this description is thorough and complete, and will fully convey the extent of the applicability of the invention to those of ordinary skill in the art.

Fig. 2 is a diagram illustrating a structure of an integrated circuit for a smart card according to a preferred embodiment of the present invention. An integrated circuit 100 includes a CPU circuit block 110 including a CPU 111, a RAM circuit block 120 including RAM, and a data bus 130 for transmitting and receiving data between the blocks. CPU and RAM circuits 110 and 120. According to one embodiment of the present invention, the data transmitted and received between the CPU circuit block 110 and the RAM circuit block 120 comprises 8-bit blocks. However, it should be understood that the bit width of the data transmitted and received between circuit blocks 110 and 120 can vary variably. Also, although the present embodiment illustrates and explains circuitry for protecting data transmitted and received between CPU 111 and RAM 121, it should be appreciated that the present invention can be applied to protect all data. transmitted and received between circuit blocks of an integrated circuit, as well as the data transmitted and received between the central processing unit and the random access memory.

The CPU circuit block 110 further includes a first scrambler 112, and a random number generator 113. The random number generator 113 generates a 4-bit random number in response to a clock signal CLK. The first scrambler 112 changes a group of 4 bits of lower order DATA_A [3: 0] among the 8-bit data output from the central unit 111 as a function of the random number, outputs the group changed to the data bus. data 130, resets an array of data bits, inputted from RAM circuit block 120 through data bus 130, to an original array, and outputs the re-established array to CPU 111.

RAM circuit block 120 further includes a second scrambler 122. Second scrambler 122 restores a 4-bit data bundle, inputted from CPU circuit block 110 through the data bus. 13 0 based on a random number generated from the random number generator 113, into an original grouping. The second scrambler 122 further delivers the reestablished array to the RAM 121, changes a lower order 4-bit array DATA_C [3: 0] among 8-bit data output from the RAM 121 as a function of the number random, and outputs the changed array to the data bus 130. In another embodiment, the random number generator 113 may be included in a RAM circuit block 120.

Figure 3 is a block diagram illustrating a circuit structure of the first and second jammers of Figure 2 according to embodiments of the invention. The first scrambler 112 includes a first bit array changer 200 and a first selection signal generator 220. The first select signal generator 220 generates a 16-bit select signal SEL1 [15: O] in response to a 4-bit random number input from the random number generator 113. When the data DATA_A [3: 0] are output from the central unit 111, the first bit grouping changer 200 changes a bit grouping of the data DATA_A [3: 0] in response to the selection signal SEL1 [15: O], and outputs DATA_B [3: 0] to data bus 130. When DATA_B [3: 0] data is inputted through the data bus 130, the first bit grouping changer 200 reverts the bit grouping of the DATA_B [3: 0] data to an original bit grouping in response. to the selection signal SEL1 [15: 0], and delivers the re-established group to the central unit 111.

The second scrambler 122 includes a second bit array changer 300 and a second select signal generator 320 similarly to the first scrambler 112. The second select signal generator 320 generates a 16 bit select signal SEL2 [15 : 0] in response to a 4-bit random number entered from the random number generator 113. The selection signal SEL1 [15: O] supplied at the output of the first selection signal generator 220 and the selection signal SEL2 [15: 0] supplied at the output of the second selection signal generator 320 are substantially identical to each other. When the data DATA_C [3: 0] is output from the RAM 121, the second bit grouping changer 300 changes a bit grouping of the DATA_C [3: 0] data in response to the selection signal SEL1 [15: O], and outputs DATA_B [3: 0] to the data bus 130. When DATA_B [3: 0] data is input via data bus 130, the second bit grouping changer 300 reverts a bit grouping of the DATA_B [3: 0] data to an original bit grouping in response. at the selection signal

<td>SEL2 [15: 0], and delivers RAM 121.</td><td>the group</td><td>of</td><td>bits</td><td>restored</td><td>to the</td>

<td>According to this</td><td colspan="2">invention, when</td><td>of</td><td>data</td><td>are</td>

<td>transmitted from the unit</td><td>central 111 to</td><td>the</td><td colspan="2">RAM</td><td> 121,</td>

the low-order 4-bit data DATA_A [3: 0] output from the CPU 111 is encrypted by the first bit grouping changer 200 (that is, the bit grouping is changed). The encrypted data DATA_B [3: 0] is transmitted over the data bus 130 to the second bit array changer 300, where the data is decrypted before being stored in the RAM 212. Therefore, the DATA_A [3: 0] data output from the CPU 111 to the first bit grouping changer 200 and the DATA_C [3: 0] data output from the second bit grouping changer 300 to the random access memory 121 are identical to each other, so as not to influence the data transmission. Since the DATA_B [3: 0] data transmitted on the data bus 130 is encrypted, even if the data bus 130 is controlled by a hacker from outside, the exposed data is different from the data substantially transmitted from the. central unit 111 to memory 121, so as to secure the real data.

Likewise, low-order 4-bit data DATA_C [3: 0], which is output from RAM 121 when data is transmitted from RAM 121 to CPU 111, is encrypted by the. second bit grouping changer 300 (that is, the bit grouping is changed) to become DATA_B [3: 0], which are transmitted over data bus 130. The encrypted DATA_B [3: 0] data on the data bus is decrypted by the first bit grouping changer

200 so as to become DATA_A [3: 0], which are output to the CPU 111. Therefore, the data DATA_C [3: 0] output from the RAM 121 to the second bit cluster changer 300, and the data DATA_A [3: 0] supplied from the first bit grouping changer 200 to the central unit 111, are identical to each other, so as not to influence the data transmission. Since the DATA_B [3: 0] data loaded on the data bus 130 is encrypted, even if the data bus 130 is controlled by a hacker from outside, the exposed data is different from the data substantially transmitted from the data source. RAM 121 to central unit 111, and therefore the data transmitted from memory 121 to central unit 111 is secured.

Figures 4 and 5 are diagrams illustrating preferred structures and operations of the first and second bit grouping changers 200 and 300 for changing and re-establishing bit groupings.

Referring to Figure 4, the first bit grouping changer has four switching parts

201 to 204, and the second bit grouping changer 300 includes four switching parts 301 to 304, which correspond to the switching parts 201 to 204 in the first bit grouping changer 200, respectively.

The switching parts 201 to 204 in the first bit grouping changer 200 are controlled by the to 204 in the first

200, and parts from to 304 in the corresponding second 4-bit signals among the selection signals SEL1 [15: O] generated from the first selection signal generator 220, respectively. In other words, the switching part 201 is controlled by a selection signal SEL1 [15:12], the switching part 202 is controlled by a selection signal SEL1 [11: 8], the switching part 203 is controlled by a selection signal SEL1 [7: 4], and the switching part 204 is controlled by a selection signal SEL1 [3: O].

As explained above, the selection signals SEL1 [15: O] and SEL2 [15: 0], output from the first and second selection signal generators 220 and 320, respectively, are identical to each other. Therefore, the corresponding switching bit grouping changer switching parts 201 301 bit grouping changer 300, are controlled by the same signals, respectively.

Referring to Fig. 5, the switching part 201 includes four switches SWA0 to SWA3, and the switching part 301 includes four switches SWB0 to SWB3, corresponding to the switches SWA0 to SWA3, respectively. The switches SWA0 to SWA3 in the switching part 201 are controlled by corresponding signals among the selection signals SEL1 [15:12] generated from the first selection signal generator 220, respectively. The switches SWB0 to SWB3 in the switching part 301 are controlled by signals corresponding among the selection signals SEL2 [15:12] generated from the second selection signal generator 320, respectively. If the selection signals SEL1 [15:12] and SEL2 [15:12] are logic 1s, the corresponding switches SWA0 to SWA3 and SWB0 to SWB3 turn on, respectively. But if they are logical 0s, the corresponding switches become out of service, respectively.

Similarly, the switching parts 202 to 204 and 302 to 304 comprise four switches, respectively, identical to the switching parts 201 and 301 shown in Fig. 5, and controlled by corresponding selection signals. Therefore, a detailed description of the structure and operation of the switching parts 202 to 204 and 302 to 304 is not necessary for a person of ordinary skill in the art to be able to understand their operation.

Table 1 shows examples of selection signals SEL1 [15: O] and SEL2 [15: 0] output from the first and second selection signal generators 220 and 320 as a function of a 4-bit random number generated at from a random number generator 113, and groups of data bits DATA_B [3: 0] output on the data bus 130 therefrom.

[Table 1]

<td>Random number to 4 bits</td><td>Selection signals (SELl [15: 0] and SEL2 [15: 0])</td><td>DATA_B bit group [3: 0]</td>

<td> 0000</td><td> 1000 0010 0100 0001</td><td>B0 B2B1 B3</td>

<td> 0001</td><td> 1000 0010 0001 0100</td><td>B0 B2B3B1</td>

<td> 0010</td><td> 1000 0001 0100 0010</td><td>B0B3 B1 B2</td>

<td> 0011</td><td> 1000 0001 0010 0100</td><td>B0B3 B2B1</td>

<td> 0100</td><td> 0100 1000 0010 0001</td><td>B1 B0 B2 B3</td>

<td> 0101</td><td> 0100 1000 0001 0010</td><td>B1 B0 B3 B2</td>

<td> 0110</td><td> 0100 0001 1000 0010</td><td>B1 B3 B0 B2</td>

<td> 0111</td><td> 0100 0001 0010 1000</td><td>B1 B3 B2 B0</td>

<td> 1000</td><td> 0010 1000 0100 0001</td><td>B2 B0 B1 B3</td>

<td> 1001</td><td> 0010 1000 0001 0100</td><td>B2 B0 B3B1</td>

<td> 1010</td><td> 0010 0100 1000 0001</td><td>B2B1 B0B3</td>

<td> 1011</td><td> 0010 0001 0100 1000</td><td>B2 B3B1 B0</td>

<td> 1100</td><td> 0001 1000 0100 0010</td><td>B3 B0B1 B2</td>

<td> 1101</td><td> 00011000 0010 0100</td><td>B3 B0 B2B1</td>

<td> 1110</td><td> 0001 0100 1000 0010</td><td>B3 B1 B0 B2</td>

<td> 1111</td><td> 0001 0100 0010 1000</td><td>B3 B1 B2 B0</td>

For example, when the data DATA_A [3: 0] delivered at the output of the central unit 111 is transmitted to the random access memory 121 via the bus 13 0, if the 4-bit random number generated from the generator of random numbers 113 is 0000, the first and second selection signals SEL1 [15: O] and SEL2 [15: 0] become 1000 0010 0100 0001. As explained above, the first and second selection signals SEL1 [15: O ] and SEL2 [15: 0] become identical to each other. As the first selection signal SEL1 [15:12] becomes 1000, the switch SWA3 of the switching part 201 turns on, and the data DATA_A [0] output from the CPU 111 is output on a third bit. of the data bus, namely on DATA_B [3]. With this method, the data DATA_A [1], the data DATA_A [2] and the data DATA_A [3], which are output from the central unit 111, are output on the data bus DATA_B [1] , on the DATA_B data bus [2] and on the DATA_B data bus [0], respectively.

Therefore, when one group of bits of DATA_A [3: 0] data outputted from CPU 111 is B3 B2 B1 B0, another group of bits of DATA_B [3: 0] data outputted on the data bus data 130 becomes B0 B2 B1 B3.

For example, if the data DATA_A [3: 0] output from the CPU 111 is 1100, the DATA_B [3: 0] data output on the data bus 130 becomes 0101. Therefore, even if the data on the DATA_B [3: 0] data bus delivered on the data bus 130 are exposed to a hacker, as the exposed data is different from the output data on the DATA_A [3: 0] data bus, the exposure of actual data can be prevented.

The data DATA_B [3: 0] loaded on the data bus 130 is transmitted to the RAM 121 using the following method. As in the example above, when a 4-bit random number generated from the random number generator 113 is 0000, the second selection signal SEL2 [15: 0] is 1000 0010 0100 0001. Since the second selection signal SEL2 [15:12] is 1000, the switch SWB3 of the switching part 301 turns on, and a third bit of the data bus, namely data loaded on DATA_B [3], is output. as bit data DATA_C [0] via switch SWB3. With this method, the data DATA_B [1] loaded on the data bus 130 is supplied to the first bit data DATA__C [1] of the RAM 121, the data DATA_B [2] is supplied to the second bit data DATA_C [2] of random access memory 121, and data DATA_B [0] is supplied to third bit data DATA_C [3] of random access memory 121.

Therefore, when the DATA_B [3: 0] data loaded on the data bus 130 is B0 B2 Bl B3, the DATA_C [3: 0] data output to the RAM 121 becomes B3 B2 Bl B0. This is the same as a grouping of bits of DATA_A [3: 0] data output from CPU 111. Therefore, the data which is transmitted from the CPU 111 to the RAM 121 through the data bus 130 cannot be exposed to a hacker, and is not influenced.

Fig. 6A is a graph showing changes in the position of data bits in the case where a random number generated from the random number generator 113 is 0000 when the data DATA_A [3: 0] output from the CPU. 111 are transmitted to the RAM 121. As shown in Fig. 6A, each bit position of the data DATA_A [3: 0] output from the CPU 111 is changed according to the selection signals SEL1 [15: O] and output to the data bus 130. In other words, the data DATA_A [0], DATA_A [1], DATA_A [2], and DATA_A [3], which are output from the central unit 111, are changed to DATA_B [3], DATA_B [1] , DATA_B [2] and DATA_B [0] of the data bus 130, respectively. Depending on the selection signal SEL [15: 0], DATA_B [0], DATA_B [1], DATA_B [2] and DATA_B [3], which are loaded on the data bus 130, are changed to DATA_C [3] , DATA_C [1], DATA_C [2] and DATA_C [0], respectively, and the changed data is output to RAM 121.

The method of transmitting data from the random access memory 121 to the central unit 111 via the data bus 130 is executed in a reverse order from that of the method explained above for transmitting the data from the central unit 111. to RAM 121.

For example, if the 4-bit random number generated from the random number generator 113 is 0100, the first and second selection signals SEL1 [15: O] and SEL2 [15: 0] become 0100 1000 0010 0001. As explained above, the first and second selection signals SEL1 [15: 0] and SEL2 [15: 0] are identical to each other. Since the second selection signal SEL2 [15:12] is 0100, the switch SWB2 of the switching part 301 turns on, and, therefore, the data DATA_C [0] output from the RAM 121 is output to a second bit of the data bus, namely on DATA_B [2]. With the same method, the data DATA_C [1], DATA_C [2], and DATA_C [3], which are output from the random access memory 121, are output on the data buses DATA_B [3], DATA_B [1] and DATA_B [0], respectively. Therefore, when the data bit group DATA_C [3: 0] output from the RAM 121 is B3 B2 Bl B0, another data bit group DATA_B [3: 0] loaded on the data bus 130 becomes Bl B0 B2 B3.

For example, if the DATA_C [3: 0] data output from RAM 121 is 1100, the DATA_B [3: 0] data loaded on data bus 130 becomes

0011. Therefore, although the data DATA_B [3: 0] loaded on the data bus 130 can be exposed to an unauthorized person, the data exposure can be prevented, because the exposed data is different from the actual data DATA_C [3 : 0] delivered at the output of the random access memory 121.

However, the data DATA_B [3: 0] loaded on the data bus 130 is transmitted to the CPU 111 using the following method. As in the example above, when a 4-bit random number generated from the random number generator 113 is 0100, the first selection signal SEL1 [15: O] is 0100 1000 0010 0001. Since the first selection signal SEL1 [15:12] is 0100, the switch SWB2 of the switching part 201 turns on, and a second bit of the data bus, namely the data loaded on DATA_B [2], is output. in the form of the bit data DATA_A [0] of the CPU 111 through the switch SWB2. With this method, the data DATA_B [0], DATA_B [1], and DATA_B [3] loaded on the data bus 130 are delivered to DATA_A [3], DATA_A [2], and DATA_A [1] of the unit. central 111, respectively.

Therefore, when the DATA_B [3: 0] data loaded on the data bus 130 is B1 B0 B2 B3, the DATA_A [3: 0] data output to the CPU 111 becomes B3 B2 B1 B0. This is originally identical to a grouping of bits of DATA_C [3: 0] data output from RAM 121. Therefore, the data transmitted from the RAM 121 to the CPU 111 through the data bus 130 cannot be exposed to a hacker, and is not influenced.

Fig. 6B is a graph showing changes in the position of data bits in the case where the random number generated from the random number generator 113 is 0100 when the data DATA_C [3: 0] output from the RAM 121. are transmitted to the central unit 111. As shown in Fig. 6B, each bit position of DATA_C [3: 0] data output from RAM 121 is changed according to selection signal SEL2 [15: 0] and output to data bus 130. Otherwise dit, DATA_C [0], DATA_C [1], DATA_C [2], and DATA_C [3], output from RAM 121, are changed to DATA_B [2], DATA_B [3], DATA_B [1], and DATA_B [0] of the data bus 130, respectively. Depending on the selection signal SEL1 [15: O], DATA_B [0], DATA_B [1], DATA_B [2] and DATA_B [3] loaded on the data bus 130 are changed to DATA_A [3], DATA_A [2 ] DATA_A [0], and DATA_A [1], and the changed data is output to the CPU 111, respectively.

However, since the random number generator 113 according to the present invention operates by synchronization with the clock signal CLK (FIG. 2), the first and second scramblers 112 and 122 perform bit grouping change operations at each clock. Therefore, even if the data loaded on the data bus 130 is exposed to a hacker, it is very difficult to decrypt the data, because for each clock a bit grouping is changed by a different method.

Although this invention has been particularly shown and described with reference to preferred embodiments thereof, those of ordinary skill in the art will understand that various changes in shape and detail can be made without departing from it. of the spirit and extent of the applicability of the invention as defined by the appended claims. For example, in the present embodiment, an array of lower order 4-bit data bits among 8-bit data output from the CPU 111 is changed. However, even if all of the 3-bit data or some bits of the 8-bit data are changed, the object of the present invention can be practiced by those skilled in the art.

According to the present invention, even if input / output data among internal circuit blocks is exposed to an unauthorized person, since the exposed data is different from the original data, the input / output data among the circuit blocks internal can be protected.