Reading device and method for integrated circuit memory

PROCEDURE AND READING DEVICE FOR MEMORY IN

INTEGRATED CIRCUIT

The present invention relates to a method and a reading device for an integrated circuit memory.

It applies in particular,. but not exclusively, to electrically programmable non-volatile memories of the EPROM or OTP type.

An object of the invention is to improve the memory read access time, ie the time at the end of which the data item reflecting the state stored in one or more memory cells is available at the output.

It will be recalled that the cells of a memory are usually organized in a matrix in bit lines and word lines. Bit lines are the conductors through which the state stored in a cell is read. Thus, when a memory cell is addressed for reading, the corresponding word line is selected and the corresponding bit line is connected to a reading device.

In general, one does not read a single memory cell, but several, allowing the reading of a memory word. In general, all of these cells forming a memory word are attached to the same word line, and to each one corresponds a respective bit line.

In reading, each of these bit lines is connected to a corresponding reading device.

All these reading devices are identical.

As the bit lines contain a large number of cells, they are capacitive (due to the sum of the individual capacities due to the components themselves: cells, selection transistors, and due to the topology of the bit lines) and resistive ( because of all the materials used, contact resistances, metallization and internal resistances of the transistors of the cells). For these reasons, the reading device usually comprises precharging means for charging the equivalent capacitance of a bit line selected for reading to a determined read precharging voltage. Then, current generating means establishes a current in the bit line. If the selected cell absorbs current, a voltage variation will be detected on the line. In the case of EPROM type memory cells, the reading device further comprises a bit line voltage limiter at a level close to 1 volt, in order to eliminate the risk of memory cell programming during read access.

Furthermore, the reading is often based on the comparison between the current flowing in the cell selected for reading and that flowing in a reference cell.

For example, in the case of an EPROM or OTP memory, the two possible states of a memory cell are the virgin state (which is also the erased state, by UV rays), and the programmed state. The reference cells are all in the same known state, generally the pristine state. In this state, the floating gate transistor of the memory cell has a low threshold voltage, of the order of 1.4 volts for example. In the programmed state, this threshold voltage becomes higher, for example equal to 5.5 volts.

The principle of reading by comparison is based on the fact that if the cell selected for reading is in the erased state, it is capable of absorbing as much current as the reference cell placed under the same polarization conditions. If only a fraction of this current is supplied to it, it will cause the bit line voltage to collapse, which will be detected.

Thus, in practice, a read current generator injects a determined read current Iref into the reference bit line associated with the reference cell, and injects a fraction of this reference current, for example half or a third, in the data bit line associated with the cell to be read. A differential sense amplifier receives on the first differential input a signal from the data bit line and on the second differential input a signal from the reference bit line.

If the read cell is erased, it draws more current than the fraction of the reference current that the current generator supplies it. The first differential input is then drawn at a voltage U lower than the voltage Uref on the second input of the differential amplifier and the output of the amplifier switches in one direction. If, on the contrary, the read cell is programmed, it absorbs a very low current or no current. The first differential input is then drawn to a voltage U greater than the voltage Uref on the second input of the differential amplifier, and the output of the amplifier switches in the other direction.

Thus, a usual reading device comprises, a precharge circuit for each of the bit lines with limitation of the bit line voltage, a generator of reading current in the bit lines and a sense amplifier which supplies the information. output.

The precharge circuit is in practice a current-voltage converter, which performs three different functions:

a first current supply function for precharging the bit lines, a second function for limiting the bit line potential to a determined read precharge voltage, eliminating the risks of programming, and a third function for supplying a signal to the amplifier, with a voltage varying strongly with the current on the associated bit line, in the evaluation phase.

The read device therefore goes through different operating phases: starting up of the precharge circuits, activation of the read current generators, selection and precharging of the bit lines, selection of the word line (row decoding). The voltage levels seen by the sense amplifier are then often close to Vdd and are not linked to the state of the selected cell, but to the precharge circuit.

At this moment the cell selected for reading absorbs or does not absorb current. If there is current absorption (blank or erased cell), this current is first supplied by the bit line capacitor, then by the associated read current generator. This current absorption produces a large voltage variation on the signal applied to the input of the differential amplifier, which causes it to switch.

However, the output of the amplifier oscillates throughout the duration of the variations on the bit lines, slowing down the establishment of the real data at the output.

In practice, the sequencing necessary to start up the various circuits of the read device and the parasitic oscillations of the amplifier slow down the read access time. It takes one and a half clock cycles to obtain the output data. In one example, there is thus a read access time of 80 nanoseconds typical, 130 nanoseconds maximum.

To avoid the problem of oscillations at the output of the amplifier, there are read devices using a latch instead of the differential read amplifier. However, additional external sequencing must then be provided to provide the activation signal for this latch as a function of all the time constraints and as a function of the sensitivity of the latch. This activation signal often comes from a control block using so-called dummy control circuits in the English literature, sized to obtain a sufficient margin, taking into account the worst cases of propagation.

In the invention, an attempt is made to improve the read access time of a memory. In a practical example, it is sought to ensure a maximum read access time of 25 nanoseconds instead of the 80 nanoseconds typical of the state of the art.

The subject of the invention is thus a memory reading device, using a differential amplifier, with very fast access time.

In the state of the art, reading is slowed down due to the successive sequencing required and to the oscillation of the amplifier.

An object of the invention is a reading device which does not have these drawbacks.

A reading device according to the invention thus comprises asymmetric precharging means for bringing the input of the amplifier associated with the selected data bit line to a voltage level higher than that of the input associated with the line. reference bit, during the precharge phase. In this way, the output of the amplifier is brought into a determined state. In the following evaluation phase, the output of the amplifier is confirmed in this state, or else switches to the complementary state, depending on the state stored in the cell on the selected bit line.

Thus, according to the invention, there is a precharge of the data and reference bit lines at a read precharge voltage, close to 1 volt, in combination with an asymmetrical precharge of the inputs of the amplifier.

As characterized, the invention therefore relates to a method for reading in an integrated circuit memory comprising a precharging phase for bringing to a precharging voltage a data bit line comprising a memory cell to be read and a reference bit line. comprising a reference cell and an evaluation phase by establishing a reference current in the reference bit line and a fraction of this current in the data bit line, a voltage signal supplied by a current / voltage converter connected to the data bit line and a voltage signal supplied by a current / voltage converter connected to the reference bit line being applied respectively at the data input and at the input of reference of a differential amplifier, characterized in that in the precharging phase, asymmetric precharging means are activated making it possible to bring one of the inputs of the differential amplifier to a voltage level higher than that of the other. The invention also relates to a corresponding reading device.

Other characteristics and advantages of the invention are detailed in the following description, given by way of indication and without limitation of the invention and with reference to the appended drawings in which:

FIG. 1 represents a block diagram of a memory architecture corresponding to a reading device according to the invention;

- Figure 2 is a detailed diagram of the architecture shown in Figure 1;

- Figure 3 shows a timing diagram of the signals corresponding to the reading of an erased cell (blank) with a device. reading according to the invention; and

FIG. 4 represents a timing diagram of the signals corresponding to the reading of a cell programmed with a reading device according to the invention.

It will be noted that, in the description, a signal and its voltage are sometimes designated under the same reference.

FIG. 1 represents the architecture of a memory using a reading device according to the invention.

In the example, the memory is of the Eprom type. A cell of this memory comprises a floating gate transistor, the drain of which is connected to a bit line of the memory plane and the gate of which is connected to a word line. The reference cell (s) are generally located on one or more reference bit lines, generally included in the memory plane.

In certain architectures, the reference cells are outside the memory plane because we want their word lines to be at a different potential than those of the cells to be read.

The architecture of the memory can be more or less complex, with or without access transistors, with grouping of bit lines or the like, and the memory can be of another type (non-volatile or other). The invention thus applies to all the different types and architectures of memory.

When a memory cell Cm is addressed for reading, the data bit line Bl associated with the cell to be read and a reference bit line Bl_refare selected to be connected to a reading device 1. This selection is made in the example by a decoding transistor. For the cell to be read, there is thus a decoding transistor T1 connected between the data bit line B1 and a data input Ed of the reading device 1. For the reference cell C_ref, a decoding transistor T1_Ris connected between a reference input Er and the reference bit line Bl_ref.

In the case of an EPROM or OTP memory cell, the memory cells are selected for reading by applying a read voltage to their gate, via the corresponding word line. In the example, the cell to be read and the reference cell have their gates connected to the same word line W1.

The reading device 1 comprises a current / voltage converter CIVd on the data side and a current / voltage converter CIVr on the reference side.

The converter CIVd is connected between the input node Ed and an output node Sd. This output node Sd of the converter CIVd is connected to the data input MTX of a differential read amplifier 2.

The converter CIVr is connected between the input node Er and an output node Sr. This output node Sr of the converter CIVr is connected to the reference input REF of the differential read amplifier 2.

Each of these converters comprises, in a known manner, in their simplest embodiment, a feedback loop formed of a transistor Tp and of an inverter II. Drain d of transistor Tp is connected to the output node and supplies the voltage signal to be compared to the differential amplifier. The source s of the transistor Tp, connected to the input node of the converter, is looped back to the gate g of the transistor Tp through the inverter II to establish a slaving imposing a precharge voltage VI on the input node Ed. The bit line connected to it is precharged to this voltage. The level of this precharge voltage is established so that the cell cannot be programmed in the read phases.

The characteristics (dimensions W / L and threshold voltage) of the transistor Tp and those of the transistors constituting the inverter define the value of the

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This generator has a current mirror structure to establish a reference current Ir on the reference bit line and a current Id equal to a fraction of this reference current on the data bit line. We thus have lR = k.lD, where k can for example take values ​​between 1.5 and 4, depending on the characteristics of the transistors used in the current mirror structure. In the example, this current generator comprises a first branch connected to the output node Sr of the converter associated with the reference bit line and a second branch connected to the output node Sd of the converter associated with the data bit line.

The first branch comprises a switching transistor T2, connected between the supply voltage Vdd of the integrated circuit and a node NI and two transistors T3 and T4 in parallel between this node NI and the output node Sr. They are mounted as a mirror. current with their grids and their sources connected in common. When the switching transistor T2 is activated, transmitting the supply voltage Vdd to the node NI, the reference reading current Ir is obtained. This current is mainly a function of the characteristics of the reference cell and of the reference bit line. The voltage on the gates and sources connected in common is established at a level Vref, which is the voltage level of the reference input REF of the differential amplifier.

In the example, the second branch comprises a switching transistor T5, connected between the supply voltage Vdd of the integrated circuit and a node N2, and a transistor T6 connected between this node N2 and the output node Sd. This transistor T6 has its gate controlled by the gate-source connection of transistors T3 and T4 of the first branch. If the transistors T3, T4 and T6 are identical, in this way a data reading current Id equal to iR / k is obtained when the switching transistor T5 is on and brings the voltage Vdd to the node N2. In the example, k is equal to 2, as a first approximation. For circuits supplied with low voltage (Vdd), k is preferably taken less than 2.

The reading device according to the invention further comprises a circuit 4 for asymmetric precharging of the data and reference inputs of the amplifier.

This asymmetric precharge circuit 4 is connected in parallel on the second branch of the current generator 3. It comprises a switching transistor T7 and a precharge transistor T8 connected in series between the supply voltage Vdd and the output node Sd. When the switching transistor T7 is activated, the precharge transistor T8 supplies a high precharge current Ipch, at low output impedance.

The reading device thus ensures an asymmetrical precharge of the inputs of the amplifier, by bringing one of the inputs of the amplifier to a voltage level higher than that of the other input. The voltage difference between the two inputs of the amplifier switches its output to a determined state.

In the exemplary embodiment of the invention described and shown in the figures, it is the MTX data input which is brought by the asymmetric precharge circuit to a voltage level higher than that of the other input, the 'reference entry REF.

This asymmetric preload must be stopped before the start of the evaluation phase proper in the amplifier. Advantageously, in order not to be dependent on the various variations of the load parameters due to the operating conditions and to the characteristics of the manufacturing process, provision is made to detect conditions for stopping the asymmetrical preload, in order to switch the device to phase. devaluation.

Thus, a circuit 5 is provided for detecting stopping conditions on a signal affected by the precharging.

The stop conditions correspond to a sufficient voltage difference between the two inputs MTX and REF. This difference is sufficient if it makes it possible to switch the output of the amplifier to the desired state, 0 in the case where it is the data input MTX which is brought to a higher voltage level. These stopping conditions can be detected in different ways, with more or less facilities depending on the signal chosen. An example of a detection circuit will be detailed later.

The detection circuit supplies a stop control signal VBMTXDT which is applied to the input of a logic circuit 6, which also receives the activation control signal SON. This logic circuit 6 provides at output the gate control signal PCHN of the precharge transistor T8 of the asymmetric precharge circuit 4 according to the invention, so that the activation of the control signal SON of the reading device activates the precharging circuit. asymmetric while the activation of the stop command signal stops it.

The reading device activation control signal SON is in practice generated by a control circuit provided in the memory circuit. This signal is activated for each read access to the memory, when the addressed bit line is actually connected to the read circuit (bit line selected). In the example, the signal SON is applied as gate control to all the switching transistors of the supply voltage

Vdd: T2, T5 and T7, to enable the different circuits of the reading device to be switched on. In general, a control of the same type is provided in the differential amplifier.

According to the invention, this signal SON also allows the activation of the asymmetrical precharge circuit according to the invention.

Thus, when the row address decoding is completed (by the column decoder of the memory circuit), the bit line B1 is selected and actively connected to the input node Ed of the reading device 1 and the reference bit line Bl_ref is actively connected to the input node Er of the reading device. The SON signal is then activated, energizing the reading device and validating the reading current generator and the asymmetric precharge circuit 4. The following self-sequenced operation is obtained:

On the data bit line side, we have a current equal to Ipch + lD, with Id supplied by the read current generator and Ipch &gt;&gt; lD supplied by the unbalanced precharge circuit under very low output impedance (characteristics of T8) . On the reference bit line side, there is a current Ir = 2.Id supplied by the read current generator at a higher output impedance (characteristics of T2, T3, T4).

The capacity of these data and reference bit lines is charged. The preload phase begins. This precharge is asymmetrical, the low output impedance on the data bit line side making it possible to raise this line to a higher level than the reference bit line. In addition, the precharging current Ipch makes it possible to accelerate the precharging on the data bit line side, accentuating this asymmetry, and making it possible to offer a high-performance read access time.

Thus, on the data bit line side, the source of transistor Tp of converter CIVd rises to read precharge voltage VI, while at the same time the drain of this transistor rises to a level close to Vdd. It is the converter servo loop that prevents the source of the transistor from rising above VI. As shown in Figure 3 or 4, the voltage VbI of the data bit line rapidly rises to its read precharge voltage level VI (close to 1 volt) while the data input MTX of the differential amplifier rises to a voltage Vmtx close to the supply voltage Vdd.

On the reference bit line side, the source of the transistor Tp of the converter CIVr rises to a read precharge voltage V2 close to 1 volt, while at the same time the drain of this transistor rises to a level defined by the chain of transistors MOS T2, T3, T4 and the reference cell. It is the servo loop which prevents the source of the transistor Tp from rising above V2. Thus, as shown in Figure 3 or 4, the voltage Vbl of the data bit line rises more slowly to its precharge voltage level V2 (close to 1 volt) while the reference input of the differential amplifier rises to a voltage level Vref lower than the voltage level Vmtx. There is then a sufficient voltage difference between the two inputs MTX and REF of the differential amplifier, to switch its output to the desired state, while the two bit lines, data and reference, are substantially preloaded to the same level. close to 1 volt. This voltage difference between the two inputs of the amplifier is obtained rapidly, owing to the acceleration of the precharging on the data bit line side by the use of a precharging current Ipch which is much greater than the read current. At the end of the precharge, the output Out of the amplifier switches to a known state, 0 in the example (Vout in FIGS. 3 and 4).

When the voltage Vmtx of the data input MTX reaches a sufficient level higher than the voltage Vref, it is necessary to cut the asymmetric precharging circuit 4, in order to go to the evaluation phase. This is achieved by the stop condition detection circuit 5. This detection circuit 5 must allow the voltage on the MTX input to rise significantly higher than the voltage on the REF input. Several detection possibilities can be envisaged, which will be detailed below. This detection circuit supplies at output a stop control signal Vbmtx. The logic circuit 6 applies a stop control voltage to the PCHN control signal of the asymmetric precharge circuit 4. In the example, the transistor T8 goes into the off state.

When the asymmetric precharge circuit 4 is cut, only the read generator current is found, ie Id = Ir / 2 on the data bit line side and Ir on the reference bit line side. The reading device goes into the evaluation phase. The evaluation begins as soon as the data and reference cells are selected by the row decoder of the memory circuit (with application of a gate control voltage of the appropriate level to these cells).

The data cell is polarized under the same conditions as the reference cell. If it is blank, it therefore has the capacity to absorb as much current as the reference cell.

If the data cell is blank (or erased), a case corresponding to figure 3, as the reading current generator can only supply it with a fraction Id of this reference current, this cell begins by discharging the line capacitor of bit, then it causes the voltage to collapse at the output node Sd of the converter CIVd: the amplifier switches. The voltage Vout of its output Out goes from 0 to Vdd.

If the data cell is programmed, a case corresponding to FIG. 4, the data cell does not absorb any current. The voltage Vmtx remains unchanged and the output of the amplifier too. In the example, the output voltage Vout remains at zero.

Thus, without sequencing signals other than the bit line and row selection signals supplied by the decoders of the memory and the read control signal SON, the output data is obtained very quickly.

It will be noted that in practice, it is necessary to activate the read device with asymmetric precharge after the bit lines are selected (data, reference), and therefore effectively connected by a converter to a corresponding input of the amplifier. Indeed, if this were not the case, the asymmetric preload would very quickly raise the input of the desired amplifier to the higher voltage level, since there would be no load on this input, causing the device in the evaluation phase too quickly, before the bit lines selected after activation of the reading device have the hardware time to rise to their precharge voltage level, causing the assembly to malfunction.

Usually, the sense amplifier comprises an amplifier stage, comprising two branches, and an output stage of the inverter type, connected to a connection node of one of the branches of the amplifier stage. The output of the inverter stage provides the Out output of the amplifier. The amplifier, of which numerous variant embodiments exist, moreover well known to those skilled in the art will not be detailed further.

In an improvement of the invention shown in FIG. 2, provision is made to dimension the output stage of the amplifier to promote its tilting in the opposite direction to that of the precharge. Thus, in the example, the output Out of the amplifier is brought to 0 in the precharging phase. The output stage is then dimensioned to favor the switching of this output from 0 to 1. Thus, the response time of the entire read chain is improved.

In FIG. 2, there is thus represented an output stage Esl with a CMOS inverter, of which the MOS transistor P has been oversized (W / L = 5μ /0.35μ) with respect to the MOS transistor N (W / L = 0.8μ / 0.35μ), in order to favor the switching of the output of the amplifier in the desired direction, 0 to 1 in this case.

To balance the loads on the amplifier stage, it is usual to provide a control output stage, dummy, connected to a connection point of the other branch, and having the same load characteristics as the output stage actually used. . This is the output stage Es2 shown in Figure 2. As this inverter stage is not used in operation, provision is made for each of the transistors of this inverter stage to have its source and its drain short-circuited and connected to the power supplies, so that this inverter does not consume current at any time.

It has been seen that a detection circuit 5 is required to stop the asymmetric precharge circuit.

In the example shown in FIG. 2, it is chosen to detect the level of the gate control signal Vbiasmtx of the precharge transistor of the current / voltage converter CIVd.

This detection can be obtained by a simple inverter 12 calibrated to switch after that of the converter.

When we are at the start of the precharging phase, this signal Vbiasmtx is at the level Vdd, to hang the highly conductive transistor Tp, allowing the voltage rise of its source. This level gradually decreases, as the source voltage increases, by the effect of the feedback loop (II).

The inverter 12 is calibrated to switch to a level Vdet, after the inverter II. As soon as the signal Vbiasmtx passes the level Vdet, the asymmetric precharge circuit 4 is cut off. This marks the end of the preload phase and the start of the evaluation phase.

During this evaluation phase, if the memory cell selected for reading is blank (FIG. 3), it will draw more current than the current generator can provide. By the effect of the feedback loop, the transistor Tp becomes very conductive again: the level of the gate signal Vbiasmtx becomes high again. The inverter 12 of the detection circuit 5 switches in the other direction and tends to restart the asymmetric precharge circuit 4. For this reason, provision must be made for the logic circuit 6 to include a memory element, so as not to allow the re-activation of the asymmetric precharge circuit 4 during the evaluation phase. This can be simply obtained by an RS flip-flop, as will be seen later.

In the case where the memory cell selected for reading is programmed (FIG. 4), the transistor Tp of the feedback loop becomes less and less conductive: the gate control signal Vbiasmtx is drawn towards the precharge level of the bit lines (about 1 volt).

Other possibilities of detection can be envisaged. In particular, the detection can be carried out on the voltage level of the output signal Out of the amplifier, or on the signal Sd.

FIG. 2 shows a detailed example of a read circuit according to the invention. In particular, the inverter II, the detection circuit 5 and the logic circuit 6 are detailed.

The inverter II is a Cmos type transistor with N and P transistors.

The detection circuit 5 comprises an inverter 12 of the Cmos type with N and P transistors, an additional transistor mounted as a diode being provided in the N branch so that the switching at the output 0 to 1, corresponding to the detection of the shutdown conditions of the asymmetric precharge circuit, occurs at a level greater than the 0 to 1 switchover of inverter Il: in other words, it is necessary that the signal Vbiasmtx at the output of the inverter II can go down to the detection level Vdet of the inverter 12.

We have seen that in this context, the logic circuit 6 should include a memory element to take into account only the first tilting of the inverter 12.

This memory element is in the example an RS flip-flop, whose reset input (Set) receives the command signal SON from the reading device, active on level 1, and whose reset input ( Reset) receives the stop detection signal Vbmtx supplied by the detection circuit 5. The data output Q of the flip-flop provides a stop signal which, once positioned, does not change until the next reading. It is combined with the activation control signal SON, in a logic gate 7, in the example, a door of the Non-OR type, which provides the PCH activation command of the asymmetric precharge circuit according to the invention.

In FIG. 2, there is detailed a differential amplifier which can be used in the invention, comprising a switching transistor T9 controlled by the control signal SON to switch the amplifier on.

Finally, discharge transistors T10 and Tll are usually provided for the bit lines (FIGS. 1 and 2), allowing initialization of the bit lines, data and reference, on the one hand, and a reduction in the consumption of the read module. out of use.

A reading device according to the invention with detection of the conditions for stopping the asymmetric preloading allows very rapid self-sequenced operation. In practice, the data can be obtained at the output in about 20 to 30 nanoseconds.

In the description of an embodiment of a reading device according to the invention which has just been given, the asymmetric precharge circuit according to the invention brings the data input of the amplifier to a voltage level greater than the reference data entry. We have seen that it can be provided that it is the reference input which is brought to a voltage level higher than the data input. Those skilled in the art will know how to adapt the device described so that the additional precharge current is injected into the reference bit line, and to make some adaptations to ensure the correct copying of the read currents in the evaluation phase to arrive at a corresponding reading device. In the example, for the stop condition detection circuit more particularly described, it could place the inverter 12 on the side of the converter associated with the reference bit line.