Charge pump circuit

Charge pumping circuit for a substrate voltage generator in a semiconductor memory device ”

The present invention relates to a substrate voltage generator in a semiconductor memory device, and more particularly to a charge pumping circuit for a substrate voltage generator.

Typically, Dynamic Random Access Memory (DRAM) uses a substrate voltage generator to generate a negative voltage in the memory chip. There are advantages to applying a negative voltage to the substrate of a memory chip as compared to applying a ground voltage to the substrate. Indeed, the variation of the threshold voltage caused by the hand effect of a transistor is minimized, and the penetration voltage is increased. In addition, the operating speed of the transistor is improved by reducing the junction capacitance. In addition the sub-threshold current can be reduced and the transistor is removed to be then biased by the drop in the input voltage of a TTL (Transistor-Logic Transistor) input terminal, this protects the memory chip. . Accordingly, if a constant negative voltage is applied to the substrate using a substrate voltage generator, the performance of the memory chip is improved.

In Figure 1, a general substrate voltage generator is shown. The substrate voltage generator of FIG. 1 comprises an oscillator 1, an amplifier 2, a control circuit.

Due to the fact that an applied to return, when the a voltage provides a charge pumping capacitance 3 and a detector 4.Output signal ηβη from detector 4 is oscillator 1 through the oscillator 1 is not through the operational loop that V_BB does not keep the rectangular wave amplifier 2 9 at a constant negative substrate voltage. charge pumping signal 5 of a charge pumping circuit 3 by amplifying an alternating current (AC) signal 8 generated by oscillator 1. The charge pumping circuit 3 connected to the substrate voltage V_BBcomprises a charge pumping capacitor 5 and two diodes 6, 7. The voltage level charged in the charge pumping capacitor 5 is determined by the level of the square wave signal 9 applied to it. If the rectangular wave signal 9 has a high logic level, the diode D ^, is conductive and the charges are discharged through the earth voltage terminal. On the other hand, if the rectangular wave signal 9 is at a low logic level, because the diode^dsub is conductive, charges are transferred from the substrate voltage terminal and the substrate voltage V_BB is lowered to a negative voltage.

Figure 2 shows a conventional charge pumping circuit, this circuit comprises P-channel MOS (Metal Oxide Silicon) transistors. Figure 3 shows a timing diagram of the operation of the conventional charge circuit of Figure 2. The operation of the The charge pumping circuit will now be described with reference to Figures 2 and 3. For ease of description, it will be assumed that the MOS transistors of Figure 2 are ideal transistors, and therefore, the threshold voltages of the MOS transistors will be ignored. The charge pumping circuit is activated by the clock signals CLK1 to CLK4. CLK1 and CLK2 signals have the same phase and different pulse widths from each other, and similarly, CLK3 and CLK4 signals have the same phase and different pulse widths from each other. . In addition, the phase of the signals CLK1 and CLK2 is in opposition to the phase of the signals CLK3 and CLK4, it follows that the charge pumping circuit performs two pumping operations during a period. If the signals CLK1 and CLK2 go to the high logic level of a supply voltage Vcc, then the signals CLK3 and CLK4 go to the low level of an earth voltage Vss after the elapse of a determined time. At this time, because the voltages of nodes c and d are set to a negative supply voltage -Vcc by the third and fourth pump capacitors 13 and 14, the third and fifth transistors 23 and 25 are conductive. As a result, the charges which have flowed from node b to substrate voltage ^ BB for half of the previous period are transferred to the earth voltage terminal through third transistor 23. At the same time, at node c, due to the fact that the charges flow from the substrate voltage V_BB through the fifth transistor 25 which is conductive, the substrate voltage V_BB is lowered to a negative voltage. In this case, because the voltage of node b exceeds the earth voltage Vss, a sixth transistor 26 is turned off and the earth voltage terminal is isolated from the substrate voltage V_BB.

If the signals CLK3 and CLK4 have a logic high level of a supply voltage Vcc, and the signals CLK1 and CLK2 go to a logic low level of the earth voltage Vss, because the nodes a and b are lowered to a negative supply voltage -Vcc by the first and second pumping capacitors 11 and 12, the second and sixth transistors 22 and 26 are conductive. As a result the charges which have flowed to node c from the substrate voltage Vbb during half of the previous period are transferred to the earth voltage terminal through the sixth transistor 26. At the same time, since charges flow to node b through second transistor 22 which is conductive, substrate voltage V_BB is lowered to a negative voltage. At this time, because the voltage of node c exceeds the earth voltage Vss, the third transistor 23 is turned off, which isolates the earth voltage terminal from the substrate voltage V_BB.

However, in this example, the second and third transistors 22 and 23 or the fifth and sixth transistors 25 and 26 should not be simultaneously conductive. If the second and third transistors 22 and 23 or the fifth and sixth transistors 25 and 26 were simultaneously conductive, since the ground voltage terminal and the substrate voltage Vbb are connected with each other, the voltage of substrate V_BB might not be lowered to negative voltage. However, in the circuit of Fig. 2, the second and third transistors 22 and 23 or the fifth and sixth transistors 25 and 26 can be simultaneously conductive. Indeed, when the supply voltage

Vcc lowers power chip after memory power is turned on to bring voltage Vcc, nodes a through d are pulled down to a negative power supply voltage -Vcc by the first four pump capacitors 11 to 14. In this case, because the substrate voltage V_BB has not been set to a negative voltage, the first and fourth transistors 21 and 24 having their gate connected to the substrate voltage V_BB are cut.

Further, the second and sixth transistors 22 and 26 are conductive through nodes a and b, and the third and fifth transistors 23 and 25 are conductive through nodes c and d. Indeed, because the second and third transistors 22 and 23, and the fifth and sixth transistors 25 and 26 are simultaneously conductive, the substrate voltage Vbb is connected to the earth voltage terminal and the substrate voltage V_BB cannot be lowered to negative voltage. Consequently the supply voltage Vcc of a considerably high level must be applied. However if the substrate voltage V_BB is positioned at the negative voltage of a high-level supply voltage Vcc, because the oscillator operates with the high-level supply voltage Vcc, the current is suddenly increased.

FIG. 6 shows the evolution characteristic of the substrate voltage V_BB of the charge pumping circuit of FIG. 2 when the supply voltage Vcc is successively raised and lowered. In a first cycle, when the voltage Vcc rises, the substrate voltage^VBB is positioned at a negative voltage of the supply voltage Vcc of substantially 2 volts. However, in a second cycle, when the supply voltage Vcc is raised again after the voltage Vcc has dropped to 0 volts, the substrate voltage V_BB is set to a negative voltage of the supply voltage Vcc of 4 volts or more. As a result, since the substrate voltage V_BB is positioned at a negative voltage of the high level supply voltage Vcc, the standby current is increased.

Further, in the charge pumping circuit of Fig. 2, because the potential of nodes b and c connected to the third and sixth transistors 23 and 26 is not constant, the efficiency of charge pumping is lowered. In other words, when discharging the charges transferred from the substrate voltage V_BB to the earth voltage terminal, because the potential of nodes b and c does not keep the negative supply voltage -Vcc and exceeds the negative supply voltage -Vcc or more, a rapid and sufficient discharge is not not achieved and the efficiency of charge pumping is reduced.

An object of the present invention is to provide a charge pumping circuit for minimizing the current in the substrate voltage generator.

Another object of the present invention is to provide a charge pumping circuit having a fast rate of positioning the substrate voltage when the supply voltage applied to the charge pumping circuit is successively raised and lowered.

Another object of the present invention is to provide a charge pumping circuit for improving the recurrence and reliability of very regularly repeated operations of the substrate voltage cycle.

It is yet another object of the present invention to provide a charge pumping circuit for increasing the efficiency of charge pumping.

According to the present invention, a charge pumping circuit having an output terminal connected to a substrate voltage, first and second pumping capacitors for respectively receiving first and second rectangular wave signals having the same phase and a width d. 'impulse different from each other, third and fourth pumping capacitors for respectively receiving third and fourth square wave signals having a phase different from that of the first and second square wave signals and different pulses from each other, a first pumping node connected to the second pumping capacity, first interrupting means, the two terminals of which are connected between the first pumping node and the output terminal and of which the control terminal is connected to the first pumping capacitor, second means of¹ interrupt connected between the first pumping node and an earth voltage terminal, a second pumping node connected to the third pumping capacitor, third interrupting means, the two terminals of which are connected between the second pumping node and the terminal output and whose control terminal is connected to the fourth pumping capacitor, and fourth interrupting means connected between the second pumping node and the earth voltage terminal, the charge pumping circuit being arranged to pump the charge from the output terminal twice during a period of the first and second square wave signals, is characterized in that it further comprises:

- first means connected to the first pumping capacitor and to the fourth pumping capacitor to disconnect the first pumping node from the second pumping node,

- second means connected to the control terminals of the second and fourth interrupting means for controlling the operation of the second and fourth interrupting means, and

- third means connected to the first and second pumping nodes and to the control terminals of the second and fourth interrupting means, for a complementary operation of the second and fourth interrupting means when receiving a signal from the second means.

Thus, according to one aspect of the present invention, a substrate voltage terminal of a charge pumping circuit is not connected to the gate of a MOS transistor, and the charge pumping circuit has pumping capacitors. additional.

The objects, advantages and devices of the present invention, as mentioned above as well as others, will be more apparent in view of the following detailed description illustrated by the accompanying drawings in which:

- Figure 1 is a block diagram of a general substrate voltage generator,

- Figure 2 is a circuit diagram showing a conventional charge pumping circuit,

- Figure 3 is a timing diagram illustrating the operation of Figure 2,

- Figure 4 is a circuit diagram of a charge pumping circuit according to the present invention,

- Figure 5 is a timing diagram illustrating the operation of Figure 4,

FIG. 6 is a graph illustrating the positioning characteristic of the substrate tension of FIG. 2, and

FIG. 7 is a graph illustrating the positioning characteristics of the substrate tension of FIG. 4.

In the preferred embodiment, the threshold voltages of the transistors of Figure 4 are ignored for convenience of description. A first pumping capacitor 31 has a terminal connected to the signal CLK1. A second pumping capacitor 32 has a terminal connected to signal CLK2 which has a pulse width smaller than that of signal CLK1 and the same phase as signal CLK1. A third pumping capacitor 33 is connected in parallel with the second pumping capacitor 32, one of its terminals being connected to the signal CLK2. A fourth pumping capacitor 34 has a terminal connected to signal CLK3 which has a pulse width smaller than that of signal CLK1 and a phase different from signal CLK1. A fifth pumping capacitor 35 is connected in parallel to the signal CLK3, and one of its terminals is connected to the third pumping capacitor 33. A sixth pump capacitor 36 has a terminal connected to signal CLK4 which has a larger pulse width than signal CLK3 and the same phase as CLK3. The first six pumping capacitors 31 to 36 consist of transistors whose other terminals are respectively connected to nodes A to F. A first transistor 41 is also provided with its channel connected between nodes A and B and its gate connected to the node. F. A second transistor 42 has its channel connected between node B and the substrate voltage V_BB, and its gate connected to node A. A third transistor 43 has its channel connected between node B and a ground voltage terminal and its gate connected to node E. A fourth transistor 44 has its channel connected between nodes C and B and its gate connected to node E. A fifth transistor 45 has its channel connected between nodes F and D and its gate connected to node A. A sixth transistor 46 has its channel connected between node D and the substrate voltage V_BBand its gate connected to node F. A seventh transistor 47 has its channel connected between node D and a ground voltage terminal and its gate connected to node C. An eighth transistor 48 has its channel connected between nodes E and D and its gate connected to node C. The second and sixth transistors 42 and 46 serve as charge transfer from the substrate voltage ^VBBr and the third and seventh transistors 43 and 47 transfer the charges from the substrate voltage V_BB up to the earth voltage terminal.

In addition, the first and fifth transistors 41 and 45 cause the second and sixth transistors 42 and 46 to cut off by transferring the charges from nodes B and D respectively to nodes A and F. As a result, nodes B and D are cut off opposite each other. of the substrate voltage V_BB.

Similarly, the fourth and eighth transistors 44 and 48 cause the cut-off of the third and seventh transistors 43 and 47 by transferring the charges from nodes B and D to nodes C and E, thus disconnecting nodes B and D with respect to the earth voltage terminal.

In Figure 5 is shown the timing of the operation of Figure 4. The operation of the charge pumping circuit according to the present invention will now be described with reference to Figures 4 and 5.

The charge pumping circuit is actuated by signals CLK1 to CLK4. CLK1 and CLK2 signals have the same phase and each other and different pulse width, similarly, CLK3 and CLK4 signals have the same phase and each other and different pulse width l 'one in relation to the other. The phase of signals CLK1 and CLK2 is in opposition to the phase of signals CLK3 and CLK4. As a result, the charge pumping circuit performs the pumping operations twice during a period. If the signals CLK1 and CLK2 have a logic high level of the supply voltage Vcc, the signals CLK3 and CLK4 go to the logic low level of the earth voltage level Vss after the elapse of a determined period. At this time, the voltages of the nodes D, E and F go to a negative voltage level -Vcc because of the fourth, fifth and sixth pumping capacities 34, 35 and 36, so that the first, third, fourth and sixth transistors 41, 43, 44 and 46 are conductors. As a result, the charges which have flowed to node B from the substrate voltage V_BB during half of the previous period are discharged to the earth voltage terminal through the third transistor 43. Because these charges from the substrate voltage V_BB are also transferred to node A through transistor 41, the voltage of node A is kept higher than the earth voltage Vss. As a result, the second transistor 42 is turned off and the node B is disconnected from the substrate voltage V_BB.

Further, since the charges from the substrate voltage V_BB are also transferred to node C through transistor 44, the voltage of node C is maintained above ground voltage Vss. As a result, the seventh transistor 47 is turned off and the node D is disconnected from the substrate voltage V_{BB /} so that the eighth transistor 48 is turned off and the voltage of node E is held above the negative supply voltage -Vcc. At this time, the charges from the substrate voltage V_BB are transferred to node D through the sixth transistor 46 which is conductive, and the result is that the substrate voltage V_BB is lowered to a negative voltage.

If the signals CLK3 and CLK4 go to the high level ”of the supply voltage Vcc and the signals CLK1 and CLK2 go to the low level of the earth voltage Vss, the nodes A, B and C go to the negative voltage level -Vcc because of the first, second and third pumping capacitors 31, 32 and 33 so that the second, fifth, seventh and eighth transistors 42, 45, 47 and 48 are conductive. As a result, the charges that flowed to node D from the substrate voltage V_BB during the preceding half-period are transferred to the earth voltage terminal through the seventh transistor 47. Because these charges from the substrate voltage V_BB are transferred to node F through transistor 45, the voltage of node F is held above ground voltage Vss or more through fifth transistor 45. As a result, sixth transistor 46 is turned off and node D is disconnected from the substrate voltage ^vbb

Further, since the charge from the substrate voltage V_BB is also transferred to node E through eighth transistor 48, the voltage of node E is maintained above ground voltage Vss. As a result, the fourth transistor 44 is turned off so that the voltage of node C is held above the negative voltage -Vcc. At this time, the charges from the substrate voltage V_BB are transferred to node B through the second transistor 42 which is conductive, it follows that the substrate voltage V_BB is lowered to a negative voltage.

In Fig. 4, since there is no place where the substrate voltage V_BB either connected to the gate of a transistor, the earth voltage terminal is disconnected from the substrate voltage V_BB. In practice, if the voltage Vcc is successively raised and lowered and consequently the nodes A to F are lowered to a negative voltage by the pumping capacitors 31 to 36, because the nodes A and F are charged to the voltage level of ground by receiving charges from the ground voltage terminal through the fifth and first transistors 45 and 41, the second and sixth transistors 42 and 46 are turned off. Then the nodes B and D are instantly disconnected from the substrate voltage V_BB. As a result, since the earth voltage terminal is disconnected from the substrate voltage V_BB, the substrate voltage V_BB is quickly positioned at a negative voltage even when the supply voltage Vcc has a low level.

In addition, because nodes B and D are in a locked state through the fourth and eighth transistors 44 and 48, the charges in nodes B and D are transferred to nodes C and E respectively and the seventh and third transistors 47 and 43 are complementarily cut. So nodes B and D are disconnected from the earth voltage terminal.

Further, because of the third and fifth pumping capacitors 33 and 35, the gate voltages .5 of the third and seventh transistors 43 and 47 are held at the negative voltage -Vcc so that the charges of nodes B and D can be quickly and sufficiently transferred to the earth voltage terminal through third and seventh transistors 43 and 47. Thus, the efficiency of the charge pumping is increased and due to the fact that the number of operations of the charge pumping circuit necessary for the positioning of the substrate voltage V_BB is reduced, the standby current is reduced.

In Fig. 7, when the voltage Vcc is successively raised and lowered, in a first cycle, the substrate voltage Vbb is set to a negative voltage at the supply voltage Vcc of the same level with a second cycle.

In the preferred embodiment described above, in order to prevent the gate oxide layers from being damaged when the strong electric field is applied to the gate oxide layers of the transistors of Fig. 4, at least one 25 diode can be connected in series with the gates of the transistors.

Although the invention has been more particularly shown and described with reference to a preferred embodiment, it will be apparent to those skilled in the art that changes in form and detail can be made without going beyond the scope of the mind and. within the scope of the present invention.