Multi-protocol isdn communication controller

(54) MULTIPROTOCOL ISDN COMMUNICATIONS CONTROLLER (||) Filing date: 27.12.88.

(30) Priority:

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References to other related national documents:

(7l) Applicant (s): BULL SA -FR.

(43) Date of making the request available to the public: 07/20.90 Bulletin 90/29.

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Inventor (s): NAJIB ABDELMOUTTALIB - DIDIER DU FLOT

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Date of making the patent for the invention available to the public: 06.17.94 Bulletin 94/24.

FR 2 641 925 - B1

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List of documents cited in the research report:

See the end of this booklet (73) Holder (s):

(74) Representative (s): DANIEL GOUESMEL lllllllllllllllllllllllllllllllllllllllllllllll

-d MULTIPROTOCOL ISDN COMMUNICATIONS CONTROLLER.

The present invention relates to a multiprotocol ISDN communications controller. It is used in particular in terminal equipment of a data transmission network where the data are routed via a type S communication link.₂ defined by European standard ECMA 104, each terminal equipment being connected by way of this link to a digital type telephone exchange.

It is known that a data transmission network is constituted by a plurality of units, generally called Terminal Equipment of

Data Processing, abbreviated, DTE, (Data Terminal Equipment, in English, abbreviated, DTE), or even terminals or stations for convenience of language. These terminals can be made up of computers, or even of any type of telephone device. These DTEs 15 communicate with each other via a transmission system or line, consisting for example of two pairs of telephone wires (one for transmission, the other for reception) or even a coaxial cable. The transmission line physically connects the geographic locations • where the terminals are located.

Local networks are transmission networks limited to a limited area (building, industrial establishment, campus, hospital) where the distances between the various terminals are of the order of a few meters or tens of meters, to a few kilometers.

The various stations or terminals of a network send information messages and receive those sent by the other stations. The individual message is called an information frame. This is structured, includes a start and end message, the address of the terminal for which the message is intended, the address of the sending terminal, the length of the data, the payload data, etc .... In other words, the information frame is the elementary block of information sent by any terminal which passes over the transmission line.

The rules for accessing the various terminals which govern the dialogue between them define what is commonly called a protocol. This last

- 2 - 'constitutes a system which orders the conversation between the terminals without prioritizing it.

Different types of protocol are known (to designate a protocol, the word procedure is also used). One of the most widely used protocols is the HDLC (Hign Level Data Link Control) protocol, standardized according to the X25 opinion of the CCITT (International Telegraph Telephone Advisory Committee), yellow book, fascicle XIII.2, November 1980 , and according to the international standards defined by the International Organization for Standardization, known as ISO, under the following designations IS3309-2, IS4335, IS6159 and 6256.

There is also a protocol defined by the European standard ECMA 102 (or even by the CCITT, under the designation V110), which tends to be used more and more commonly.

A terminal comprises two essential functional parts, namely the data source or collector, on the one hand, and the communication controller grouping together the bodies responsible for the communication functions of the terminal with the other terminals, on the other hand. The latter in particular protects against data transmission errors and introduces special so-called service information making it possible to ensure dialogue between the various terminals. The communication controller may or may not constitute a physically dissociable subassembly from the actual information processing units of the terminal. Between the communication controller and the transmission medium, there is generally a DCE data circuit terminating equipment (DCE), which is a body responsible, in particular, for adapt the electrical signal delivered by the terminal to the transmission media. This function is in current practice carried out by modulation-demodulation of an auxiliary carrier signal in a device called MODEM.

The complete information exchanged between the various terminals is most often in the form of a set of coded binary information (bits).

- 3 In general, the information sent by the data source is in the form of sets of eight bits, called bytes, sent in parallel, while these same bytes are transmitted by the serial transmission line. The coupler therefore transforms the parallel information bytes 5 into serial information bytes. Furthermore, it has multiplexing functions, that is to say it is intended to transmit several different communications in series on the same transmission line.

The trend of technological development of networks, with the appearance and rapid development of the use of mi ni computers has led to the use of programmed communication controllers, called front-ends.

A front end, or even front end processor, is made around a microprocessor connected to one or more memories, the function of which in the system formed around the computer with which it is associated, is to reduce the load on the unit. central unit of this computer by carrying out part of the management of the messages sent by the various terminals belonging to this system.

It is characterized by:

- a basic software much simpler than that of the central unit, containing specialized modules making it possible to manage the transmission line connecting between them the terminals of the computer and that of the network, and having facilities to constitute queues of 'waiting for messages (in main memory or in secondary memory).

This software must also allow the simultaneous execution of a large number of processes;

- The input and output functions are carried out to quickly manage numerous interrupts, which involves very efficient microprocessor context switching mechanisms, as well as multiple interrupt levels.

In other words, the front-end performs control functions of the telecommunications network, that is to say the lines and terminals of this' 2641925

- 4 last and ensures the temporary storage of the messages in the memory which is associated with it. The way in which the front-end is connected to the central and the distribution of workloads between them varies depending on the manufacturer. Thus, in the computer with the trade name DPX 2000 of the Company BULL SA, the communication controller consists of a base exchange unit which receives the data coming from the central computer or from the various terminals depending on that one. here, and manages the high communication layers of the OSI reference model (3 to 7 essentially) defined by the ISO (data storage, sharing of resources and data, access control, queue, backup, reprise, etc ...) and a peripheral unit arranged between the exchange unit and the DCE data circuit termination equipment itself connected to the transmission line. The peripheral unit 'manages the communications between the exchange unit base and the other terminals of the network (other than those dependent on the computer) as well as the temporal multiplexing and demultiplexing of the various data channels of the link between the terminal and the telephone exchange (layer 2 of the ISO model). It will be noted that a private type digital telephone exchange is also called a PABX.

One of the current trends in technological development in the field of data transmission networks is the regrouping of telephone traffic and data transmissions and more generally of all digital traffic on a common infrastructure. This is mainly due to the gradual introduction of digital techniques in the telephone network for switching and transmission between switches on the one hand, and for the distribution and connection of subscribers on the other hand. This is the objective of the integrated services digital network (ISDN, French acronym), the English equivalent of which is Integrated Services Digital Network (ISDN, English acronym).

The integrated services digital network makes it possible to offer, apart from digital telephony,:

- a greater variety of remote computing applications, in particular those which require file transfers at short notice;

- 5 2641925

- multiplexing, on the same subscriber line, of various low-bit rate channels supporting several simultaneous remote data processing flows, or even of remote alarm or telemetry or remote control signals;

- the transmission of still images under improved conditions of quality and speed with, for example, fast faxing;

-the prospect of transmitting moving images (television, videophone, videoconference, etc.) in the near future (by 1995).

ISDN is intended for use primarily in Europe and in particular in France. As a result, it comprises a certain number of interfaces standardized according to ECMA standards. For telecommunication communications between computers and PABX, the most interesting interface is the so-called S interface.₂ defined by European standard ECMA 104. The S interface₂ is also called a communications link of the type

S₂. This link therefore uses a telephone transmission line as a physical medium.

An S-type bond₂ has a throughput of 2048 megabits / s (or even Mbps) and has 32 distinct channels, namely 30 so-called type B channels for data transmission with a throughput of 64 kilobits / s (or even Kbps), a so-called type D said signaling at 64 kilobits / s and a frame alignment channel whose bit rate is also 64 kilobits / s. The principle of the S connection₂ is time division multiplexing, each time channel constituting a separate channel. The time multiplexing of the different channels or channels means that between two successive samples of the same channel, 125 microseconds are available to transmit eight-bit words (bytes) which constitute the coded values ​​of the samples relating to the other channels. Multiplexing therefore consists in allocating, within a time interval of 125 microseconds, a time interval for each sample of a channel equal to 3.9 microseconds. The various interlaced samples are transmitted successively, the same channel of index i occurring every 125 microseconds. A set of 32 bytes with a duration of 125 ys is thus formed, which will be designated by the name of the time frame (not to be confused with the information frame defined above). In practice, the operation of this requires the

- 6 presence of a locking word transported by the frame locking channel which allows the receiver to locate the start of the frame and therefore the different channels. In other words, any time frame has 32 8-bit time intervals (IT), marked from 0 to 31, i.e. the time intervals ΙΤθ to ΓΓβρ The time interval ΙΤθ indicates the start of the time frame and l The time interval ITjg conveys the signaling for all the data channels. This signaling D channel (to which the time interval ITjg corresponds of course) makes it possible to know the identity and the nature of each correspondent (that is to say of each terminal or of each computer) as well as the type of protocol on each of the other channels, and the overall load required to process the entire link (because not all channels are necessarily in use at the same time).

We can therefore see that each data channel, during each time interval, carries 8 bits every 125 microseconds, or 8 x 8000 = 64 kilobits / s. The total line speed is therefore equal to the sum of all the speeds of the 32 channels, ie 64 x 32 = 2048 kilobits / s.

It should be noted that each channel is intended to carry communications using any type of transmission protocol and any type of information encoding. The most frequently used protocols are the HDLC protocol or the ECMA 102 protocol. This means that on the same data channel, successive information originating, for example, from different terminals can be transmitted with different transmission protocols. This means that from one channel to another the protocols can be different, and that on the same channel over time the protocols used can also be different.

According to the needs that are felt in the exchange of communications between terminals connected by a type S link₂, it may be necessary for the communications controller of a computer to manage an S link₂ as a whole or on the contrary to manage several type S links₂ in which only a determined number of data channels are used. The main quality of the communications controller must therefore be great flexibility of use and great speed.

- 7 As the ECMA 104 standard is still recent (19 ..) communications controllers managing an Sg type link are rare.

Current solutions lie in the use of specialized components, that is to say of specialized communications controllers each managing a finite number of channels according to a given particular protocol. This is the case with the controller of the SIEMENS Company, whose trade name is ITA and which manages a single channel in ECMA102. In addition, the physical interface between the transmission line and the communications controller 10 is integrated into this controller itself. It follows that

The use of specialized components to manage a given protocol implies specialization of the controllers and it is necessary to have as many controllers as there are protocols to manage, which is quite heavy and expensive.

In addition, for protocols which are specific to a given manufacturer or whose standardization is recent, there is no specialized component.

In the current state of the art, in order to form a communications controller capable of managing one or more Sg type links, it is therefore necessary to constitute a set of specialized components, each of which is suitable for processing a given protocol. This is impractical, bulky and expensive.

The present invention makes it possible to remedy these drawbacks by constituting an extremely fast communications controller using a signal processor (it will be recalled that signal processors are processors whose usual use consists in carrying out mathematical operations on digital data: multiplication, addition, integration, Fourier transforms etc ...) and of a dynamic allocation device working under the control of the exchange unit base as defined above, making it possible to assign at a determined time a data channel using a given protocol to a determined physical transmission channel, the communications controller 35 comprising n different physical channels. The dynamic allocation device can, depending on the transmission requirements of telecommunications at a determined time, assign to the physical channel to

- 8 which corresponded a data channel having a first particular protocol, another data channel using a second protocol or even assigning the data channel using the first given protocol to another physical channel. This defines a dynamic allocation of the 5 communication protocols used on the different data channels to determined physical channels. Dynamic allocation therefore makes, on the same physical channel, change protocol (this change being transparent for the other channels) or change channels for the same protocol, all without resetting the other channels.

Thus, the communications controller according to the invention can manage one or more S-type links.₂ simultaneously, while having a small footprint and being inexpensive.

According to the invention, the multi-protocol ISDN communications controller ensuring the management of at least one type S communication link₂, physically supported by a transmission line and comprising a determined number of data channels managed according to a plurality of protocols, between a computer and a set of terminals connected by means of a telephone exchange, comprising:

- a base exchange unit receiving data from the computer or terminals via the link, and managing the high communication layers of the OSI model,

- a peripheral unit arranged between the exchange unit base and a data circuit termination device or DCE itself connected to the transmission line, the latter adapting the electrical signals coming from the exchange unit via the peripheral unit to the transmission media, the peripheral unit carrying out the management of communications between the computer and the other terminals as well as the time multiplexing and demultiplexing of the various data channels of the link, characterized in that the peripheral unit comprises, arranged in series between 1 ' DCE and the exchange unit, a dynamic allocation device, a double access random access memory comprising n distinct physical channels, of fifo type, both on transmission and on reception, a signal processor associated with a programmable memory, the allocation device receiving the

- 9 data and a synchronization signal sent by Ί 'DCE on a serial data bus carrying m time channels with m greater than or equal to n, transforming the sets of serial bits into sets of parallel bits sent to the dual access memory, ensuring the concentration of the m time channels 5 on the n physical channels of the dual access memory by dynamic allocation of the m time channels on the n physical channels under the control of the exchange unit, the processor reading (or writing) in each channel of the dual access memory, the data which are written there (or read) by the allocation device, storing them temporarily in memory, analyzing the state of the data frames according to the type of protocol used to transmit these, and by extracting the data to then transfer them to the exchange unit base.

Other characteristics and advantages of the present invention will become apparent from the following description given by way of non-limiting example and with reference to the accompanying drawings. On these drawings:

“ ^The Figure 1 recalls how information is transmitted from a first terminal to a second terminal,

- Figure 2 recalls how a type S communications link is made₂,

- Figure 3 shows a local network comprising a plurality of terminals 25 and computers connected by at least one type S link₂ to other terminals via a telephone exchange, or PABX

- Figure 4 shows how a communications controller according to the invention is connected to several S-type links₂ and to the connection bus of the computer to which it is associated,

- Figure 5 shows how an S link adapter works₂ to the serial data bus to which the communications controller according to the invention is connected,

- Figure 6 shows different signals sent by the link adapter of figure 5 to the data bus of figure 5,

- Figure 7 shows the essential characteristic elements of the communications controller according to the invention,

- Figure 8 is a more detailed view of Figure 7,

- Figure 9 is a detailed view of the essential components of the peripheral unit of the communications controller according to the invention,

FIG. 10 shows how the dual-access memory of the peripheral unit of the controller according to the invention is constituted,

- Figure 11 illustrates the detailed operation of the peripheral unit.

Consideration is given to FIG. 1 which shows schematically how the data is transmitted from a first terminal TA to a second terminal TB. The terminal TA includes a data source SDA and a communications controller CCA, while the second terminal TB includes a data source SDB and a communications controller CCB.

A first data circuit termination equipment (DCE) viz. MODA is connected between the CCA communications controller and the LT transmission line. Likewise, a second equipment of. MODB data circuit termination is connected between CCB communications controller and LT transmission line. This transmission line can consist of two patres of telephone wires, a pair for the transmission PE and a pair for the reception PR.

The communications controller CCA comprises an exchange unit UEA and a peripheral unit UPRA; likewise, the CCB controller comprises an exchange unit UEB and a peripheral unit UPRB. The role, nature and functioning of the various elements mentioned above have been detailed above. In particular, the data is transmitted by the data source STA in parallel to the communications controller CCA which transmits it in series to the MODA element which adapts the electrical signal to the transmission line LT. The CCA controller controls and manages the transmission of communications between the TA terminal and the TB terminal. The same is true for the CCB communications controller.

-11We now consider Figure 2 which shows how an LS communication link is made up₂ type S₂ defined by European standard ECMA 104. LS link₂ is composed of 32 channels Cq to Cjp which we saw above that they constituted a set of distinct time channels VTq to VT₃₁. The information rate transmitted on each channel or time channel is 64 kilobits / s, the entire LS link₂ having a data rate of 2.048 megabits / s. In one second, it is therefore possible to convey 8000 elementary temporal frames TRL comprising 32 bytes each transmitted during the time intervals ΙΤθ, ITj, IT₃₁. Each time interval IT allows 8 bits to be routed bg to by. The duration of an elementary time frame TRL. is 125 microseconds and the duration of an IT time interval_i is of the order of 3.9 microseconds. The time interval ΙΤθ makes it possible to locate the start of each elementary frame TRL, while the time interval ITjg carries signaling information making it possible to know the identity and the nature of each party sending via d '' a terminal and deduce the type of protocol on each of the time channels or channel and the overall load necessary for processing the LS link₂.

It is known that each terminal such as TA or TB transmits individual information messages, also called information frames which may be designated for example by MTR. Such an MTR frame is transmitted according to a determined type of protocol, by HDLC example, on one of the time channels VTq to VT₃₁ for example the time channel ντ_η·. The MTR-j frame is therefore sent in the form of successions of bytes, on the time channel VT₇·, Within each time interval IT, ·, and this every 125 microseconds. The same would apply for another frame or individual message MTRj sent by another terminal on the time channel VTj in the form of a succession of bytes sent during the time interval ITj, according for example to a different HDLC protocol. as it is ECMA 102 protocol. One of the particularities of the LS information link₂ defined by the European standard ECMA 104 is that, on the same time channel, it is possible to successively circulate information frames or individual messages according to different protocols. We see that a type S₂ offers considerable flexibility of use. In addition, it is the role of the CCA or CCB communications controller to receive all the bytes relating to the same MTR frame._not, And reconstitute.1 'all of this

26419.25

- 12 frame so that it can be read, understood and interpreted by one of the data sources SDA or SDB. In addition, it can be concluded from the above that it is not a question of confusing an information frame or individual message MTR, sent by any one of the terminals and which has a variable duration depending on the message sent. and an elementary temporal frame of TRL type which always has the same duration, namely 125 microseconds and comprises 32 bytes, each of these belonging to a different information frame MTR, ·, MTRj.

Consideration is given to FIG. 3 which shows a local network RLE of the ISDN type. Such a network comprises several so-called conventional terminals, only one of which, namely the terminal T₂ is represented in FIG. 3 and which transmits information at a rate which may be of the order of 1200, 9600 or 19200 bits / s and a set of ISDN type terminals of which only one is represented, namely Tj. Each of these terminals T | or T₂ is connected by a communication link LSq of type Sq defined by recommendation 1430 of the CCITT, physically supported by a telephone transmission line (of the type of line LT in FIG. 1), to a PBX. private telephone better known in the state of the art under the Anglo-Saxon acronym PABX. The LSq link has a speed of 64 kilobits / s. Therefore, between the classic terminal T₂ and the LSq link which is associated with it and which connects it to the PABX, there is a TAD adapter terminal which makes it possible to adapt the data rate transmitted by T₂ at the rate of 64 kilobits / s required by the European standard ECMA 104, for each data channel.

The local area network RLE also comprises at least one computer such as the computer COMP associated with a communications controller such as the communications controller according to the invention CCI. This is connected to the LS communication link₂ via CAS data circuit terminal equipment 30₂ also called adapter or S card₂.

LS link₂ connects the CAS adapter₂ and consequently, the communications controller CCI to the PABX switch. It should be noted that the PABX switch can be connected by an LT link₂ to the public telephone network RPT. As a result, the computer COMP can be linked to any geographically remote terminal, via the LS link.₂, the PABX and the public RPT network. The PABX acts as a line concentrator.

- 13 Considering FIG. 4 which shows a coupler according to the CCI invention connected between an SMB data bus connecting the central unit and the various terminals of a COMP computer, for example a DPX 2000 type computer from the BULL Company. SA, on the one hand, and on the other hand a BMIC bus and several S-type links₂, namely LS₂₁, LS₂₂, LS₂₃, LS₂₄. Each of these links corresponds to an adapter, namely CAS₂j to CAS₂₄. To each of the links and to each adapter corresponds a bus, namely BMICj to BMIC₄. The BMIC bus is therefore made up of the association of the 4 BMICj BUSes to BMIC₄. The time frames on each of the buses BMICj to BMIC₄ are transmitted synchronously. On each of these, the information is transmitted in series, while the SMB bus is a parallel type bus. The latter is for example of the type described in the CNET technical notice relating to the computer SM 90 (whose BULL designation is QUESTAR 700-DPX 2000), under the reference ST / PAA / 0GE / SML / 1 / SM90 edited by BULL SEMS. Note that this SMB bus is a 32-bit parallel bus.

Each of the LS communication links₂₁ to LS₂₄ comprising 32 temporal channels, it can be seen that the communications controller, in the exemplary embodiment which will be described below, is capable of processing 128 temporal channels which can each transport MTR information frames over time according to several protocols. determined.

We consider figure 5 which illustrates the role of a CAS adapter₂. The latter is connected to the transmission line LT and consequently to each of the pairs of telephone wires PE and PR which physically support an LS type communication link.₂ defined in Figure 2.

It is known that the information is transmitted on each of the time channels according to determined protocols, the data transported by each of these channels also being coded in a known manner. On the other hand, the communications controller CCI according to the invention operates, in a particular preferred example of embodiment of the invention in NRZ code. We can therefore see that the adapter S₂ has the role of transforming the data transmitted by the communication link S₂ according to known codes determined in understandable data for the communications controller CCI, that is to say coded in NRZ. The S adapter₂ carried out

- 14 therefore data transcoding. In addition, the adapter CASg recovers on each of the time channels a clock signal CLK used both on transmission and on reception, transmits the data DR to the controller CCI on reception and receives the data DE coming from the transmission. of the controller in NRZ code. It extracts from each time frame TRL a reception synchronization signal SYNR consisting of a series of pulses sent at successive instants tp tg, etc. separated from each other by a time interval equal to 125 microseconds, ie the duration of an elementary time frame TRL. The SYNE synchronization signal on transmission is synchronous with the SYNR signal.

The CLK clock signal is a square periodic signal which has a frequency of approximately 2.048 MHz.

The data DR and DE are such that each bit is validated at each rising edge of each signal CLK.

In fact, the data DR and DE which are transmitted by the buses BMIC ^ to BMIC4 are such that the time frames TRL comprise 31 useful channels, the ITq channel (used for the locking of the TRL frames on each of the links LSg ^ to LSg₄) being now used to convey on the one hand, specific control signals coming from the CCI controller to drive each of the CAS cards₂₁ to CAS₂₄, and on the other hand, on reception, signals indicating transmission or operation incidents of the links LSg ^ to ls₂₄.

It can be seen that the adapter CASg has a role quite analogous to a conventional data circuit terminal equipment such as the MODA or MODB element shown in FIG. 1. Furthermore, the transcoding techniques necessary to switch to NRZ code from codes conveyed by each of the channels of the LSg link (such as the HDB3 code for the entire link specified by ECMA104) are well known, as are the methods of extracting synchronization and clock signals.

Consideration will now be given to FIG. 7 which shows the essential constituent parts of the communications controller CCI according to the invention.

- 15 This CCI controller includes:

. - a base UEI exchange unit, which we will call exchange unit for simplicity,

- a UPRI peripheral unit,

- an INTIg interface between the exchange unit UEI and the peripheral unit UPRI.

The UEI exchange unit is connected by the 32-bit parallel bus SMB to the various terminals and to the central unit of the computer COMP, for example a DPX 2000 type computer from the company BlILL SA, while 1 ' peripheral unit is connected to the BMIC bus. shown in figure 4.

¹⁵

As was said above, the exchange unit UEI processes the top layers 3 to 7 of telecommunications of the OSI model after having received the data coming either from the central unit and from the various terminals of the computer COMP, or the data coming from the communication links

LS₂j to LS₂₄ through the UPRI peripheral unit and the INTI interface₂.

The UPRI peripheral unit therefore processes the lower layers (in fact layer 2) of telecommunications of the OSI model. It receives the different TRL time frames (see FIG. 2) and extracts the data from them, time channel by time channel, groups together the data transmitted on each of these to reconstitute all or part of the information frames MTRj or MTRj (see to the description of Figure 2). It checks that these frames MTRj and MTRj etc ... are correct and send this data through the INTI interface₂ to the UEI exchange unit. The UPRI peripheral unit therefore reports the state of the information frames MTRj to MTRj, etc., to the exchange unit UEI and indicates to it whether these frames contain errors or not. As a function of this, the exchange unit requests or not the re-transmission of the frame MTRj (or MTRj) from the terminal which previously sent it, depending on whether or not the latter contains an error. We can therefore see that the peripheral part 'UPRI analyzes and notes the state of the frames but does not decide on the use that should be made of them.

- 16 done. This is the responsibility of the UEI exchange unit. Conversely, when sending an MTR frame_i, the peripheral unit UPRI receives this sent by the exchange unit UEI via the interface INT ^, adds new information bits to it so that the frame MTRj conforms to the protocol, (for example example, HDLC), according to which the frame is transmitted (for example, in HDLC, the peripheral unit inserts 0s after a succession of 5 bits equal to 1, calculates the cyclic code of CRC errors, adds the flags or flags: flag in English, which will allow the receiving terminal of the network to understand that the MTR ^ frame is sent by UPRI according to an HDLC type protocol and to carry out the appropriate processing).

The peripheral unit receives the data sent by the UEI exchange unit in parallel and sends them serially over the BMIC bus. The peripheral unit sends each frame MTRj which is transmitted to it by the exchange unit UEI, in the form of a succession of bytes transmitted in series on any one of the time channels VT-j (except VTq, see more top) carried by one of the BMICi to BMIC buses₄.

The UEI exchange unit is similar, in the embodiment described here, to the exchange unit of the DPX 2000 computer from the BULL Company. Furthermore, it is built around a 68020 processor from the MOTOROLA SEMI-CONDUCTORS Company, for example, located at Colvilles -road, Kelvin Estate-East kilbride / Glasgow, Scotland. It is therefore described in the technical manuals relating to the 68020 processor from this manufacturer. This PCI processor is associated with a read-only memory MMI ^ of 64 kbytes, and a RAM MVIj of 512 kbytes. These different elements, namely PCI, MMIp MVIj are connected by means of the same internal 32-bit parallel Bip bus in the exemplary embodiment described here. The PCI processor is punctuated by a 16.6 MHz clock.

The RAM MVIj contains the programs for processing the high telecommunication layers of the OSI model as well as the data coming from the central unit and from the various terminals of the computer COMP via the SMB bus and the INTI3 interface before these are transmitted, under the control of the PCI processor to the UPRI peripheral unit. In the opposite direction, to. reception, the RAM MVIj receives and stores the data

- 17 transmitted by the peripheral unit UPRI via the interface INTIg before transmitting them, always under the order of the processor PCI to the bus SMB which routes them to the central unit or to the various terminals of COMP.

The UPRI Peripheral Unit includes:

a PCSI signal processor associated via its internal bus BIg with a random access memory MVIg and a read only memory MMIg, and with 1, 'interface INTIg,

- a DAMI double access memory,

- a device for dynamic allocation of the time channels on the physical channels of the dual access memory, namely DADI,

- an INTIj interface between the DADI device and the BMIC bus.

It can therefore be seen that the UPRI peripheral unit is structured around the PCSI signal processor. The latter, in the exemplary embodiment described here, is a signal processor of the TMS320C25 type from the TEXAS Company.

INSTRUMENT. This processor and its applications are described in the book of TEXAS INSTRUMENT Digital signal processing applications with the TMS 320 Family, as well as in the TMS 3200C25 User's guide. The TMS 320C25 signal processor is clocked by a 33.3 MHz clock, which corresponds to a memory access time of 120 ns. Programmable ROM has a capacity of 64 Kbytes while RAM has a capacity of 32 Kbytes. The read-only memory and the MMIg and MVIg RAM are accessed without waiting time (access time · 35 ju s). The PCSI signal processor has a BIg data bus width of 16-30 bits. The interface INTIg must therefore be designed so as to adapt the data bus BIg with a width of 16 bits of the signal processor PCSI to the internal data bus BIj of the processor PCI which has a width of 32 bits. For example, MMIg and MVIg are manufactured by Advanced Micro Devices under the reference AM 27S51A.

The MMIg read-only memory includes the communication protocol processing programs (HDLC, ECMA102, ... etc) of the different channels of the

- 18 LSgi to LS links_2Z|. These programs are written as firmware.

The DAMI dual-access memory is organized into 64 distinct fifo-type elements (first-in, first-out) of 16 bytes each, each fifo type element being assigned to a physical channel and to a direction of transmission (transmission or reception) . As can be seen in FIG. 10 which shows in more detail how the dual access memory DAMI is made up, the latter therefore contains 32 distinct physical channels Vq with each channel comprising a sub-channel (corresponding to a fifo element of 16 bytes) VE reserved for transmission and a second VR sub-channel reserved for reception. Thus, the physical path V_o is broken down into two sub-channels VEq and VRq, the sub-channel VEq corresponding to the transmission and VRq to the reception of data. The same is of course true for each of the other channels Vj to Thus the channel comprises two sub-channels VEj ^ corresponding to the transmission ët VR31 corresponding to the reception.

The dynamic allocation device DADI is for example constituted by an integrated component of the VLSI type having for example the reference DP3120 from NATIONAL SEMI-CONDUCTORS. The dynamic allocation device DADI is controlled via a link LI by the processor PCI of the exchange unit UEI, via the interface INTIg.

The interface between the dynamic allocation device DADI and the BMIC bus, namely INTIj is responsible for reshaping the signals coming either from the dynamic allocation device DADI on transmission or from the BMIC bus on reception. It therefore performs the electrical adaptation of the signals between DADI and BMIC. This interface is produced for example by components 74F244 from the manufacturer RTC for signals in the receive direction and by components 7406 for signals in the transmit direction.

The outline of the operation of the UPRI Peripheral Unit is as follows. It is assumed that we are operating in reception of signals. It is obvious that the reasoning which will be explained below would be exactly the same on emission, the operations taking place in the reverse order.

Information from the various terminals of the RLE network via the LS link₂ and the CAS adapter₂ and the BMIC bus are therefore transmitted on

- 19,128 time channels (4 x 32 time channels, since there are 4 buses BMIC ^ to BMIC4, see above in relation to the description of figure 4). These signals transmitted in series are reformatted by the interface INTI | and transmitted to the dynamic allocation device DADI. The latter, controlled by the PCI processor via the INTIg interface and the LI link assigns one of the 128 time channels, for example the 75th time channel, which we will denote by VT75, to one of the physical channels Vq to Vq of the DADI double access memory (for example channel V ·] where 1 is between 0 and 31). This means that within a time frame TRL (see figure 2) the information byte conveyed by the time channel VT ^ will be assigned to the physical channel V ·] of the double access memory DAMI (in made to sub-channel VR-j) and that the byte from the DADI device will be momentarily stored in this channel. The corresponding byte transmitted in series by the interface INTIj to the DADI device will be transformed into a byte .transmitted in parallel to the double access memory DAMI. The latter is therefore stored in channel V] then read by the processor PCSI which will process it according to the protocol of the frame MTRj to which the byte belongs, thanks to the protocol processing program contained in the memory MMI₂ (in HDLC protocol, for example, the processor PCSI removes the flags, deinserts the zeros, reads the cyclic code CRG, deduces therefrom if the frame contains an error). Once the processing has been carried out on the byte, the PCSI processor transmits the latter directly via the INTI interface₂ to the live memory MVIj of the exchange unit by a procedure of the well-known DMA type (direct memory access) such a procedure (and the corresponding interface, INTDMA, see below) being for example described in the manual of MOTOROLA SEMI-CONDUCTORS relating to the 68020 processor. Before transmitting the byte to the MVIp RAM, the PCSI processor can also store the byte in the MVI RAM₂ (if the traffic load is high, for example), before transmitting it to MVIp but this is less frequent in practice. After having been stored in MVIp, the data relating to the same frame are transmitted (in one or more times) to the central unit and the various terminals of the computer COMP via the SMB bus.

As soon as another byte of an information frame MTRj is transmitted on the time channel VTj, the dynamic allocation device DADI assigns the physical channel k to this time channel VTj. A process analogous to that

- 20 which has just been described above then takes place before the frame MTRj is transferred after processing its protocol, from the memory MVIj of the exchange unit UEI to the central unit and the terminals of 1 ' COMP computer.

It should be noted that the assignment by the DADI device, under the control of the PCI processor, of any physical channel Vj, Vj, etc. to a time channel VTj, VTj is not carried out, in practice, on the arrival of each byte ITj of a frame MTRj, or even when the last byte of a frame TRj arrives at the DADI device. In practice, your reassignment of a new physical channel different from Vj (or Vj,) to the time channel VTj (or VTj) only takes place when hundreds or even thousands of frames MTRj have passed through the same time channel VTj. The reassignment of the channels and therefore the corresponding reprogramming of the device only takes place when there is a need to change the communication mode.

In other words, we can therefore say that the dynamic allocation device DADI performs, under the control of the UEI exchange unit, the concentration of the 128 time channels of the 4 S-type links.₂ (see figure 4) on the 32 parallel physical channels Vq to V31 of the DAMI double access memory. It is also said that the DADI device performs the dynamic allocation of the various temporal communication channels on the physical parallel channels of the DAMI dual access memory. Given that the DAMI memory is of the fifo type, it can also be said of this fact that there is a concentration of the 128 time channels of the 4 S-type links₂ on the 32 parallel time channels of the DAMI double access memory. It is clear that this dynamic allocation of the serial time channels on the '32 parallel time channels is carried out as a function of the configurations, that is to say of the needs and loads of the conversation between the various terminals of the network in which is included RLE, these needs and charges being known to the UEI exchange unit.

A more detailed description of the operation of the UPRI Peripheral Unit will be made below in relation to Figures 8 and 9.

Consider FIG. 9. The INTIp interface comprises a DMA interface namely, INTDMA, an interrupt and synchronization interface between the

- 21.26 4 19 25 PCI processor and the PCSI processor, namely INTISI, and finally an interface between the PCI processor and the DADI allocation device, namely the INTIDADI interface.

The INTDMA interface communicates with the PCSI signal processor via the BI bus₂ and is connected to the BIj bus of the PCI processor.

The INTISI interface is connected to the BIj bus of the UEI exchange unit on the one hand to the BI bus₂ the PCSI signal processor on the other hand. The purpose of this interface is to allow all communication between the two processors, the PCI processor having to be able to send the PCSI signal processor at any time a connection or disconnection order, and the synchronization between these two processors. This INTISI interface is mainly used during the reset phases of the two processors. . The INTDADI interface is connected via the line LB to the bus BIj and via the line LI to the device DADI.

The line LB transmits at the same time the addresses of the registers of the internal table TABI of the DADI device (see below) corresponding to the n physical channels of the DAMI memory and the data which must be entered in these registers, i.e. that is to say the indication of the time channels VT ^, VTj, which must be entered in them. On the other hand, the line LI presents successively in time the addresses of the registers then your data which must be entered therein.

This INTDADI interface therefore transmits the allocation orders for each of the 128 time channels on each of the 32 parallel time channels of the DAMI double access memory (see description above).

. Consider now Figures 8, 9 and 10 which show in more detail how the UPRI peripheral unit is constituted and operates.

This unit comprises, in addition to the elements already mentioned above, the PTI pointer and the data transfer regulation device DRI.

- 22 The PTI pointer receives the SYNR synchronization signals coming from the BMIC bus on the one hand, and on the other hand an initial reset signal RAZI sent via the BI bus₂ by the PCSI signal processor when the work of the CCI controller begins. As can be seen in FIG. 9, the PTI pointer, which is in fact a modulo 16 counter, the content of which is incremented by one unit when it receives a synchronization pulse (SYNR) corresponding to the arrival of a time frame TRL (see FIG. 2) is also connected by means of a parallel link LPI on 4 bits to the double access memory DAMI. It is known that each channel Vj (sub-channel 10 VE | and sub-channel VR-j) can contain 16 bytes corresponding to 16 successive time frames. In fact, in practice (for hundreds, or even thousands of successive TRL time frames), the 16 bytes contained in the same V- channel are IT ^ bytes belonging to 16 successive time frames. Each lane V- | (VE- | sub-channel and V sub-channel_R]) 15 therefore comprises 16 zones each containing an IT ^ byte belonging to one of 16 successive time frames, these 16 zones having a rank between zero and 15 and being called VE_lq and VR_pq. (figure 10).

The PTI pointer which indicates the rank q of a TRL time frame_q among 16 20 successive frames (between 0 and 15) therefore indicates the rank of the area VE-jq (or VR-]_q) where the ITi byte of said TRL frame is temporarily stored_q in the way Vj.

The regulation device DRI is in fact constituted by a down-counting counter, on 4 bits, which makes it possible to know the state of filling of the double access memory. This counter receives the SYNR synchronization signal from the BMIC bus. This counter is incremented by one unit each time it receives a synchronization pulse, (and therefore each time a TRL type frame arrives on the DADI device) and is decremented by two units each time the processor signal has completed processing relating to two successive TRL frames. Indeed, the signal processor carries out processing on 16 bits, that is to say two successive bytes. The signal processor can read the contents of the DRI counters on its 4 least significant data bits. Moreover, at the start of the 35 operations, the signal processor PCSI resets DRI (and also PTI, see above) to zero, then as soon as it says it is ready to work, it authorizes the operation of this counter by sending a write signal. on a

- 23 special input of the latter (not shown for simplicity in Figure 8) via the link LI₂·.

The PCSI processor which also counts (thanks to an internal software type pointer) the time type frames TRL which reach it performs the comparison between the content of its internal counter and the content of the regulation device DRI.

In addition, the PCSI processor can generate three types of interruptions of operation of the controller CCI according to certain particular values ​​of the content of the regulation device DRI, which are, in the exemplary embodiment described here, 15, 12 and 5 (or 4 ).

Not a word

If the content of the controller is equal to 15, then the PCSI processor generates an interrupt to the PCI processor, via

The INTI interface₂ (INTISI). Everything is then reset to zero, and all the operations which were in progress and could not be processed by the PCSI processor must be resumed (both in transmission and in reception).

If the PCSI processor does not read the bytes contained in the DAMI memory fast enough, the contents of the DRI device will become equal to 12. (DAMI memory filled to 3/4). The latter sends a first interrupt signal (via LI₂) to PCSI. The latter, in order to absorb its delay (it does not read and / or write as quickly as the bytes reach the dynamic allocation device and in the DAMI memory), decides, for example, to process only the signals on reception. As a general rule, its delay is reabsorbed and the content of DRI will go down to 4 or 5 (DAMI memory 3/4 empty). It generates a second interrupt via LI₂ to PCSI which resumes its normal work, in transmission and reception. In general, when the traffic peak has passed, the content of the DRI counter never exceeds 12 and remains between 1 and 3 (normal traffic).

It is clear that, if, after the first interrupt (content equal to 12) the content of the counter continues to evolve so as to reach 15, we are brought back to the case described above, namely interruption of the processor PCI and reset to zero. complete. It should be noted that an interrupt which occurs when the DAMI memory is 3/4 empty (content equal to 4) does not

- 24 can only occur when the interrupt corresponding to a memory 3/4 full has occurred, and vice versa.

The dynamic allocation device DADI receives (or sends to) coming from the interface INTI ^ connected to the BMIC bus, the data signals DR (signals DE), the synchronization signal SYNR (SYNE) and the clock CLK. It contains a TABI table which establishes the correspondence between the time channel VT, · of the 128 time channels which are transmitted by the BMIC bus, and the physical channel V] of the double access memory DAMI. This correspondence is established on command of the PCI processor of the UEI exchange unit, via the INTI interface₂.

At the output, the dynamic allocation device DADI is connected via an 8-bit data bus in parallel, namely BD, a 5-bit address bus, namely BA and a Single-wire LRW link to DAMI dual access memory. The address bus BD transmits the data byte corresponding to the time channel VTj, the address bus BA transmits on 5 bits the address of the physical channel Vj of the double memoryDAMI access, while the LRW link indicates whether it is transmission data or reception data (DR or DE). The DADI device writes bytes in DAMI on reception (in the VR-j sub-channel) and reads them on transmission (in the VE-j sub-channel).

The detailed operation of the assembly is as follows:

It is assumed that the PCSI has initialized the PTI pointer and the regulation device DRI to zero (signal RAZI) and that it has then authorized their operation. We then consider a succession of 16 temporal frames (the reasoning would of course be identical for all the temporal frames 30 which will follow these first 16) namely TRLg, TRLp TRL₂, ...,

TRLg, ... »TRL ^ g. In addition, a first data byte ITj corresponding to the time channel VTj belonging to the information frame MTRj and a second byte ITj corresponding to VTj and belonging to MTRj is considered. (One could also consider other bytes 35 corresponding to other time channels but the reasoning would be strictly the same as for ITj and ITj). The bytes ITj and ITj corresponding to the time frames TRLg to TRL ^ are ITjg to ITj ^ g and^ITjO ^{to IT}jl5

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ent

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- 25 then the first TRL frame₀ and the corresponding bytes IT_i0 and

The SYNR synchronization signal arrives at PTI, DADI and DRI.

The content of the PTI pointer changes from zero to 1. The content of the regulation device DRI changes from zero to 1. The byte ΙΤ ^ θ is then transmitted in series (after having been reformatted by the interface INTIj) to the device DADI. The TABI table then contains the number 1 of the physical channel V] of which the sub-channel VRq will contain the byte IT ^ q which will go into the area VR ^ q. This table establishes the correspondence between i and 1. The DADI output BA address bus then contains the value 1 when it receives the byte ΙΤ ^ θ (for example, this IT byte_q-Q can be the 75th byte of the 128 that carries the BMIC bus and must go on channel 1 = 17). The byte ΙΤ ^ θ is stored inside the registers (not shown for simplicity in FIGS. 8 and 9) of the serial-parallel type of DADI for the time necessary for its transformation from a serial byte to a parallel byte. The byte ΙΤ ^ θ is then written by DADI in the area VR-jq, the line LPI of the PTI pointer then transmitting on 4 bits the value zero which is the number of the area VR-j₀ which contains 1 byte IT ^ -q (and which corresponds to the number 0 of the frame TRLq). Strictly analogous reasoning can be done for the ITjq byte, transformed by DADI from serial byte to parallel byte and written by the latter in the VR ^ q area of ​​the VR ^ sub-channel of the channel which is the physical channel assigned to the time channel VTj by the processor PCI and therefore by the device DADI.

Once ΙΤ ^ θ and ITjq are written, and before the new synchronization pulse corresponding to the frame TRLj arrives, DADI reads what is contained in the VE-jq and VE areas_kû sub-channels VEq and VE ^ of the channels Vj and Vj, where the processor PCSI is supposed to have written bytes belonging to transmission frames sent by the exchange unit UEI base. In fact, immediately after the reset, the processor does not write anything to DAMI until the content of DRI is equal to 3. Therefore, DADI will read VE-jq and VE areas._k0 the content of which is considered to be empty.

When TRLj arrives, then the contents of PTI and DRI go to 2. DADI writes the bytes ITjj and ITjj in the areas VRq and VR_kl, DADI reading what is supposed to be written in the VE ^ and VE ^ areas, and therefore reads content, empty.

- 26 When TRL₂ happens, then the content of PTI and DRI goes to three.

At the same time, DADI writes the IT bytes]₂ and ITj₂ θ^η VR]₂ and VR [_&lt;2 and reads what is supposed to be written in VE zones]₂ and VE_k2 and therefore reads empty content. Meanwhile, PCSI reads DRI, sees that its content is three, so knows that two bytes IT-j₀, IT.jp ITjq, ITjj etc ... have arrived and read these, in fact processing according to the transmission protocol used for MTR] and MTRj, then stores them before transmission to MVI ^ via the INTDMA interface. PCSI then writes two bytes of information TI-jq and TIjq belonging to two information frames sent by the base exchange unit UEI, namely TMR- and TMRj in the areas VE] q and VE | jq of DAMI and the two following bytes TIj £ and TIjj belonging to the same frames in the VE-jet VE zones_kp

Once this is done, PCSI decrements the content of DRI by two (which goes to 1) and keeps in memory (by its internal pointer) that it has read what was contained in VR-j₀ - VRp, VR_k0 - VR_kl.

Then comes the TRL3 frame. The content of PTI changes to 4. The content of DRI changes to 2. DADI writes IT]₃ and ITjj in VR] 3 and VR ^, reads the empty contents of VE-J3 and VE ^. PCSI does nothing. When TRL ^ arrives, PTI goes to 5 and DRI goes to 3. We then find a reasoning similar to what happened when TRL arrived₂. DADI writes ITj ^ and ITj-4 in VR-j ^.^et VRfcq. · PCSI reads the bytes contained in VR]₂ - VR] 3, VR_k2 - VR ^ g. The phenomena then reproduce themselves identical in themselves until the arrival of TRL ^ g or PTI passes to zero and DRI to 2 or 3 (depending on whether PCSI has had a normal rhythm or has been delayed).

^ITil6 ^ITjl6 ^{will be} written in VR]₀ - VR_k0 and so on, the process reproduces itself identical to itself.