Memory addressing circuit.

(54) ADDRESSING METHOD AND SYSTEM FOR DYNAMIC MEMORY (22) Date of filing: 15.11.83.

(□ O) Priority:

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References to other related national documents:

Applicants): SAT (SOCIETE ANONYME DE TELECOMMUNICATIONS). -FR.

Inventors): GERARD AGUILLE AND JEANCLAUDE RENE JOLIVET

Date of making the patent available to the public: April 28, 89 Bulletin 89/17.

List of documents cited in the research report:

Refer to the end of this booklet

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(73) Holder (s):

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Agent ^): BEATRICE CEREZ-BUSNEL, SAT.

The present invention relates to dynamic memories with row-column multiplex addressing and more particularly to the development of such addressing systems.

Such memories are, for example, used in digital systems of the television type where it is necessary to do interimage processing, an image memory then being essential.

Such memories generally have dimensions of 4K binary elements 16K, 64K or even 256K, each K being equal 4θ to 1024 binary elements. Thus, for 64K memories, it is necessary to be able to have 16 addressing bits. In order to limit the number of inputs due to addressing, for the integrated circuits performing these memory functions, the 16 binary elements are multiplexed in a 2/1 order so as to have only eight parallel channels.

The choice of information to be multiplexed is such that one must have eight least significant binary elements in parallel and in series with the eight most significant binary elements and this hangs each addressing cycle.

p_not cycle A of least significant binary elements and most significant binary elements multiplexed with a cycle B formed of least significant binary elements (Pf) and most significant binary elements (PF) follow each other d clock as follows:

<td>Pf A | PF A | Pf B</td><td>PF B</td>

Thus, cycle A can be a write cycle and cycle B can be a read cycle.

3θ In practice, the least significant binary elements (Pf) can be assigned to the row addresses of the memory circuit while the most significant binary elements (PF) correspond to the column addresses of this same memory circuit.

Addressing systems are already known; however, ii_s require a circuit formed by numerous counting boxes, multiplexers to multiplex the write and read addresses on eight binary elements in parallel. Thus, FIG. 1 represents a conventional addressing scheme for dynamic memory 64K binary elements. Two counters 1 and 2, respectively write and read, provide sixteen binary elements of addresses each. These addresses are multiplexed by a multiplexer 3 which places them on sixteen parallel bits at output then on eight bits parallel to the output of another multiplexer 4. In TTL technology for example, such a scheme requires four boxes for each 16 bit counter, four boxes for multiplexer 3 and two boxes for multiplexer 4, for a total of fourteen boxes.

The present invention relates to an addressing system for such memories, more economical in number of components.

The invention consists in designing a system making it possible to increment the least significant binary elements then the most significant elements each time that the dynamics of the least significant have been swept.

The invention essentially consists in having a digital accumulator operating at a period twice as high as the period of the random access memory, one clock pulse serving to increment the least significant binary elements, the other pulse serving to increment the elements most significant binaries.

The digital accumulator of the invention is essentially formed from at least one same area, from the previous state, looped over an addition circuit, said addition circuit also receiving as input a binary increment signal.

According to a characteristic of the invention, q storage flip-flops are placed in series, each operating at the rate q XH, q being a natural integer.

According to a first characteristic, q is equal to 2. According to a second characteristic, q is equal to 4. In addition, the particular writing address on which the reading is synchronized is put in an additional memory.

A first application of the addressing system of the invention consists in using the random access memory for reading and then writing to the same address.

A second application of the addressing system of the invention consists in using the random access memory for writing and reading alternately at different addresses.

Other advantages and characteristics will become apparent on

- 3 reading of the following description illustrated by drawings.

FIG. 1 represents a known diagram of an addressing system.

FIG. 2 represents a general diagram of an addressing system according to the invention for dynamic memory with simultaneous writing and reading.

FIG. 3 represents a diagram of an addressing system according to the invention for dynamic memory for reading then writing at the same address.

FIG. 4 represents a diagram of an addressing system with synchronization.

FIG. 2 represents a dynamic memory 5 operating at the rate h of a clock. The addresses of dynamic RAM type memories are most often developed according to the ascending order of whole numbers, namely from 0 to n or from 0 to 65535s for a circuit with a capacity of 64 Keb X 1.

To go from address n to address n + 1 is to increment.

FIG. 2 represents a general diagram of a multiplexed addressing system according to the invention. The dynamic memory 5 receives data d which is addressed in writing and reading by the signal S coming from the addressing system 6 of the invention.

This system 6 essentially comprises four octuples flip-flops 62, 63, 64, 65 of type D making it possible to store the states. It will be recalled that each eightfold flip-flop is made up of eight flip-flops placed in parallel.

These flip-flops 62 to 65 operate at the rate of a 4H clock which makes it possible to supply a clock pulse to increment the least significant binary elements, the other clock pulse to increment the most significant binary elements each time the dynamics of the least significant were swept for each cycle. The memory circuit 5 receives two clock signals h ′ and h supplied by a generator 51 which receives the clock signal 4H as an input. Indeed, the two signals h 'and h allow the memory 5 to recognize the least significant and most significant bits. In the following description, it will be assumed that in the same way the memory circuit receives the required clock signals without mentioning them explicitly.

States 0 (2 °) to 65535 (2¹^) are classified into a first series known as of least significant corresponding to the states θ (2θ) to 255 (2? - 1) modulo 256 while the other states are incremented during the most significant times which follow the state 255 in low weight. In summary, the address of a memory cell is Pf + 256 PF.

The Q output of flip-flop 65 is applied to the input of an addition circuit 61 which advances the flip-flops 62 to 65. Indeed, a signal which is a binary 0 or 1 is applied to the input of this addition circuit 61 and carries out the advancement of the state of the flip-flop 62 by applying + 0 or + 1 during the least significant times.

The retention of the result from the addition circuit 61 is also applied to the input of a flip-flop 66 which memorizes the overshoot of the low-weight dynamics to cause an incrementation of that of the most significant when the low-weight dynamics has been completely wiped out. An OR gate 67 can then apply, i.e. this retention from the circuit

66, or the advancement K (0 or 1) corresponding to the instant considered at the input of the addition circuit 61. The addressing signal S can then, depending on the phase of the clock signal, be the signal coming from the output Q of the flip-flop 62. Thus, the result of the addition is stored in flip-flop 62 and simultaneously the result previous is transferred to rocker 63.

Such an addressing system is in particular applicable for dynamic memories with simultaneous and alternate writing and reading, the writing and reading addresses being different.

During each clock period, four independent elementary times take place, writing during the first two and reading during the last two.

During the time low weight writing (Epf) and reading low weight 35 (Lpf), we perform + 1.

During the most significant writing (EpF) and most significant reading (EpF) time, + 1 is only done if the previous state Pf is at 255.

If the pace of reading is to be made slower than

- 5 the writing rhythm, just do + 0 instead of + 1 during the moments of low weight reading (Lpf) and vice versa.

The table below represents the state of the addresses during a clock period:

<td>E low weight</td><td>E high weight</td><td>L low weight</td><td>L high weight</td>

<td></td><td> 1</td><td></td><td>-...... i</td>

<td> ,+1</td><td>1 , + T or 0</td><td>1 1 ± —L ----- 1</td><td>+ 1 or 0.</td>

FIG. 3 represents a variant of the addressing system of a dynamic memory 5 operating at the rate of a clock H.

Indeed, if memory 5 is used for reading and writing at the same address, it suffices to use a 2H rhythm clock.

In the same way, the addressing system 8 essentially consists of two flip-flops 82 and 83 of type D placed in series, flip-flop 82 receiving as input the signal from an addition circuit 81. This addition circuit receives the signal obtained on the output Q of the flip-flop 83, a signal which it adds with the signal fi coming from the OR gate 87. The signal fi is formed from the signal and the carry signal from the flip-flop 86 making it possible to pass from the dynamics of low weight to the dynamics of high weight. The signal is a binary 0 or 1. The flip-flop 86 stores the signal from the adder 81.

The address signal is a signal formed of 8 bits in parallel coming, for example, from flip-flop 83 ·

Such an addressing system operating at the 2H rhythm would also apply to memories in permanent writing or in permanent reading.

The addressing system of FIG. 2 would also apply to the simultaneous addressing of two random access memories and M₂with permanent writing in one memory and permanent reading in the other.

If it is, for example, a storage of television images receives only if f. is the frame rate, the memory M does not read addresses during an image cycle while during this memory M receives only addresses in the same cycle. And during the next cycle, writing inversely, the memory receives only write addresses and the memory M read addresses as summarized on the table below:

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<td> 1---------</td><td></td><td>--F—</td><td></td><td> -1—</td><td></td><td> --------1</td>

<td></td><td>L</td><td></td><td>E</td><td></td><td>L</td><td> »</td>

<td> 1 '</td><td></td><td> 1</td><td></td><td> ... |</td><td></td><td> 1</td>

<td> 1--------</td><td>E</td><td>—F—</td><td>L</td><td> —1—</td><td>E</td><td> ---------1</td>

Television type digital image transmission systems require interimage processing in order to reduce the digital bit rate transmitted online. Thus, for example, for interimage processing of the conditional refresh type, the image memory can be a random access memory organized according to the write read mode at the same address as shown in FIG. 3 In other systems, for example for the coding of a color television type image on a 34 Meb / s channel, it may be necessary to scan the image memory faster in writing than in reading, therefore to repeat a reading on one or more particular addresses of the writing. The image memories are then most often of the circulating memory type.

FIG. 4 represents an addressing system for such memories. An addition circuit 91 receives the states stored in parallel on 8 bits in one of the boxes of the memory 93 and then performs the addition with the signal ^. The signal (3 is + 1 or 0 or + N, N being a natural integer depending on whether we want to go from the previous address n to the next address η + 1 or to the address n + N if the we want to make address jumps during reading as well as during writing as we will see later, this in order to allow to repeat or delete part of the information contained in the memory 5 ·

Advancement is carried out by means of a flip-flop 92 of type D which operates at the 4H rhythm and puts its result in a box in the random access memory 93 annex with capacity 8X8. Indeed, if one wishes to synchronize an image in writing on an address of type or S ^, one writes during appropriate writing times this address in the annex memory 93 and during reading times, the incrementation is done on the reading addresses of least significant and most significant identified above.

The address signal applied to the image memory 5 is the signal from flip-flop 92.

Such a synchronizing effect addressing system applies very particularly to the repetition or the deletion of certain addresses of television images and to the synchronization of these images.