Computer monitoring system

g Agent: AM Blain, 22, avenue de l'Opéra, 75001 Paris.

D

Sale of booklets at IMPRIMERIE NATIONALE, 27, rue de la Convention - 75732 PARIS CEDEX 15

The present invention relates to the field of equipment for monitoring the operation of a computer.

Monitoring the operation of a computer has given rise to an industry in the much broader field of the information processing industry. Monitoring of operation is necessary due to the high cost of equipment, the wide variety of software and hardware, and the need to optimize the use of such equipment. In general, monitoring equipment provides the user with information concerning the events occurring in the computer equipment, the times at which these events occur and the frequency of these events. Currently, hardware and software and a combination of hardware and software monitors are in use. The hardware picks up signals from the CPU processor or peripheral devices, notes the times when these signals occur, stores the signals, and / or when and where a signal arrives, and can provide visual output of such information to the user. The software is mainly used to format the information collected for a presentation useful to the user of the computer.

Standard monitors select signals for monitoring by attaching a plug to a line located in the CPU or in a peripheral device receiving the signals to be measured. The probes consist of differential amplifiers with high impedance on the line to which they are fixed. The two significant problems relating to this standard method are the lack of flexibility and the appreciable increase in the number of probes necessary to collect a wide variety of information. Thus, for example, once the probes are fixed, the signals measured are determined. To measure different signals, the probes must be removed and attached to other lines. Similarly if we need to measure the activity of the processor of a central unit and a set of peripheral devices to collect such information, a large number of sensors is necessary as well as long cables to connect them to the more or less distant peripheral units.

Monitors of the prior art have been the subject of several patents "US Pat. No. 3,399 * 298 provides a direct connection to the particular elements of the host computer" to be monitored. The monitor counts standard time pulses to provide an indication of the period during which a particular item is to be monitored. During this period, a second counter receives the mature time pulses but only during the times when the item is monitored for information according to a preferred embodiment of the present invention.

Figure 4 ** t Figure 4 a illustrate, in a block diagram, the event translator of Figure 3.

FIG. 5 is a block diagram of the short-occupancy detector of FIG. 2.

Figure 6 is a block diagram of the system recovery detector and the selective recovery detector of Figure

2.

Figure 7 is a block diagram of the serial input and output memory and its control device shown in Figure 3®

FIG. 8 is a block diagram of the input / output stop detector of FIG. 2.

FIG. 9 is a block diagram of an initial selection detector of FIG. 2.

FIG. 10 is a diagram in the form of end-of-operation detector blocks shown in FIG. 2.

FIG. 11 is a block diagram of the buffer information recorders generally represented in FIG. 3 "

FIG. 12 is a block diagram of the command selection and charge state means as well as the command / state register represented generally in FIG. 3®

A preferred embodiment of the invention is described in a set for monitoring the operation of an IBK computer system.

360or 370. We understand, however, that. the invention is applicable to all other computer systems.

An arrangement of a peripheral device and a processor of a central unit is shown in Figure 1 and includes the processor 10, the channel 11, the general cable 24, the controls 12 - 16, the terminals 12 to 30 12 f, the printer 14 a,. and the disc drives 16 a - 16 c. The nine peripheral devices illustrated represent only a sampling of the devices of this type which can be connected to the general 24® cable. The devices represented are connected to channel 11 of the processor by the communication control 12, by the control 14 of the printer and P^ar drive control 16 of the discs as well as by the general 24® cable As we know, the general cable carries information, address, commands, status information, data and indicators of control signals back and in advance. The particular arrangement and sequence of such signals on a channel of an IBM 360 /

370 is described in several publications® By way of reference, one can be active. Thus the report of the accounts recorded in these two counters indicates the measurement of the performance of the particular device placed under surveillance.

US patent 3,906,454 in the name of MARTIN relates to a monitor for a host computer. According to the MARTIN patent, the host computer must be specially programmed or adapted to provide signals to the monitor that certain other signals should be accumulated or otherwise processed for monitoring.

US Patent 3,818,438 in the name of DSESE deviates from this technique for counting or dating the time signals received from various places on the computer, but performs these operations by the sole monitoring of certain indications of particular states of computer and recording the time when there is a change in one of these status indications.

Other standard monitoring systems or devices are taught in the patent FREEMAN US 3,763,474, Murphy US 3,540,003, Murphy US 3-522,597 RACH US 3.5Ê8.837 and KANDÎEW US 3,692,989.

It is therefore an object of the present invention to provide a computer operating monitor which overcomes the problems mentioned above.

According to the present invention, the selection of indications to be measured is not predetermined by the installation of probes but is determined by the monitoring electronics and consequently can be modified electronically. Similarly, according to the invention, the measurement of the activity of the peripheral devices is carried out without direct attachment of probes to the peripheral devices.

These objects and advantages are obtained by connecting the monitoring equipment as if it were a peripheral device to a channel of the processor of the central unit, by taking signals from the channel, by controlling the combinations of signals and signal sequences, by developing event codes identifying combinations and sequences, by reducing the number of information taken from the channel according to the programmable instructions for each peripheral device on the channel and by collecting series of information according to the event code developed.

In the drawings î

Figure 1 is a block diagram of a preferred embodiment of the present invention and connected to a host system.

Figure 2 is a block diagram of a channel interface module according to a preferred embodiment of the present invention.

Figure 3 is a block diagram of a bonding module⁴ 2425674 refer to publication No. GA - 22-6974 entitled Channel to Control unit DEM Information (channel to a DEM Information control unit).

In general, each general cable comprises thirty nine lines, nine lines for the transmission of a word with eight bits in parallel plus the parity output of the processor of the central unit designated simply below processor, nine for the transfer of a word to eight bits in parallel plus the parity entered in the processor, two for the address input and output address indicators respectively, one for the output command indicator, two for the on and off indicators respectively, two for the data input and data output indicators respectively one for the input status indicator, two for the input operation and operation indicators output respectively, and one for the hold indicator. The eighteen lines that transmit eight-bit bytes plus parity are referred to as general input and output lines. These lines transmit address bytes, command bytes, state bytes, and data bytes.

Although there are several signal sequences on the channel, a typical sequence, designated as the initial selection sequence, is as follows. The processor sends an address byte on the output lines, designating a particular device, and activates the address output indicator; the device sends its address on the input lines and activates the address entry indicator; the processor sends a byte of command on the lines, output and activates the output command indicator; the device transmits a state byte on the input lines and activates the state input indicator; the device fulfills the command which can be to send or receive bytes of data on the input or output lines respectively.

According to the present invention, the activity of the device is monitored by directly connecting to the general channel a monitor composed of a channel interface module (CIM) 18 of a data acquisition module (d CK) 20. The monitor also preferably includes its own processor and main memory, represented generally by the microcomputer 22, to collate the data, and present it to the user in all varieties of standard formats. The collation and presentation of data, as well as the programming of the microcomputer, does not constitute a characteristic of the claimed invention and therefore the details of such a process need not be explained. However, microcomputers are well known as well as surveillance software. In addition, given the arrangement of the collated data for presentation by the DCM 20 data capture module, anyone with ordinary skill in the art of monitoring and software can program a known microcomputer to obtain the collation. desired and format information.

Among the typical devices which the invention makes it possible to monitor, mention may be made of communication terminals such as the ISM 3705 and COKTEN 3670 units; a set of recording units such as printers, card readers etc ...; direct access memory (DA SD) devices similar to the IBM 3330 and 3350 large capacity memory devices. The types of information that can be gathered in these three classes of data processing equipment are described below.

When the importance of channel communications increases; operations in this area are becoming critical. The monitor can perceive any event on the channel. As a result the user can combine the data in many ways to construct measurement data. The monitor can measure the delays in processing communications, or the time lost on a given operation of the hardware or software of the host processor, such as the time between the first action transmitted by the channel and arriving at the host processor of the unit. central and the excitation of this host processor by the same channel ”The monitor thus controls the signal sequences or the character strings. It can recognize character sequences ranging from 1 to 255 characters. In addition to measuring the length of messages, it can also measure message traffic: message direction to or from this processor and the distribution of message frequencies. The monitor can measure and query the data in a message to determine if the transaction codes and keywords match those adopted by the user. It can also recognize particular sequences of signals that are incorporated into a particular segment of the sequence.

Since any general channel signal appears on the monitor, unit / record events are particularly suitable for measurements. Primarily, significant resources were required to measure unit / record events. But since the unit / record events process the record elements one at a time, the monitor employs a minimum of means to obtain information which was originally difficult to obtain. For example, such measures as the following have become routine measures: determination of the number of cards read, the number of cards per second, minute, hour, day, etc. as well as the number of lines, pages, characters etc ... printed by page or by time unit. Even the determination corresponding to the identification

S42S6F4 of the most frequently printed character is a routine operation.

The monitor can perform measurements on direct access memory devices such as measurements relating to a mathematical analysis made by a device and a control unit; or relating to chronological programs for detecting angular positions; or to chronological programs reserved / free of a device; or counts of search time, address search, number of searches; or distribution of lengths of information blocks; or the occupancy statistics for devices, the control unit or the channel.

The interface module of channel 18 monitors all activity on the same block selector of the multiplexer channel but does not react in any way to it. The module itself is preferably located under the floor of the equipment room where it is connected directly in the wiring of the channel. The additional resistance due to the insertion of this module does not exceed 2 ohms for each of the conductors constituting the cable bundle. This condition remains true for cable lengths of the order of 2 meters provided with two compatible IBM connectors, such as the AKP 86? 19 - 1 and 86719 ~ 2 models fixed at their end. In addition, this module must not allow more than 5 milliamps to pass for a reference voltage of 3 ”11 volts from all general or particular lines. This module does not interfere with the operation of the channel so that repeated interruptions in the supply of the module have no effect on the normal operation of the channel. This module can be connected to the channel cables at any location between the channel controller and the channel termination device.

This module fulfills the detection functions! of combinations and sequences of indicators on the channel and develops event codes identifying combinations and sequences, the level and duration change functions modifying certain indicators to levels and durations usable by the plug module of data, as well as multiplexing functions of general input and output lines on a single group of general lines for presentation to the data acquisition module, It should be noted that the channel interface module collects and passes to the data collection every byte on the general lines, that is to say there is no selection or sampling of information in the interface module of the channel.

The data acquisition module receives the information presented to it by the interface module and operates either to ignore the information, or to collect series of information by excluding data relating to a particular device, or to collect sets of information as well as a specified part of data relating to a device or to collect sets of information as well as the addresses of disc drive drums, heads and sectors when a search or sector determination command is in play.

The data acquisition module contains a control word for each device address on the CPU channel of the central unit. The control word is accessible when this module receives the address of the device. The control word commands the module either to ignore any information relating to this device, or to accept and form a series of information, but without data for this device, or to form a

10 'series of information and collect data starting with a pultiplet X and ending with a byte Y of each data transfer.

A block diagram of a channel interface module is shown in Figure 2. It includes a set of event detectors 50 - 60, an event code generator 68, a si15 level circuit general 62, an information selector 64, a register 66 and a set of transmission circuits 70 a— 70- h. Each event detector detects a change of state of a signal or a certain state of conditions or sequence of conditions on the channel and generates a signal called True or l when the indicated conditions are satisfied. The six detectors provide a total of seven outputs, only one of which is representative of the True signal at any given time. The seven detector outputs lead to event generator 68 which provides a single three-bit output identifying the TRUE input line and therefore identifying the detected event. For each generated event code, the generator 8 also activates the event code repetition signal.

The signal level circuit 62 receives eight channel indicators and in response provides five repetition pulses of the level and the natural duration for use by the data acquisition module. Address entry, address exit, command exit, and

30; entering states result in the respective repeated signals of addresses, commands and states. The in-service, out-of-service, data entry and data output indicators provide repeat data indicators.

The information selector 64 receives the eight general input lines with parity and the eight general output lines with parity and multiplexes these lines on eight general lines and one parity line which are connected to a nine bit register 66. The transmission circuits 70 a - 70- h transmit the indicated codes, the repeating indicators and the data from the data acquisition module.

The low occupancy detector 60 is shown in detail in the

1425674 Figure 5 and includes a single rocker D. The output of the short-occupancy rocker indicates the TRUE state when the address exit indicator is in the TRUE state and the input state indicator passes in the TRUE state. The short occupation event appears when the controller of the peripheral device increases the level of the input status indicator while the address exit indicator is still at the top level. This avoids an initial run-to-end selection sequence. ''

Referring to FIG. 2, it can be seen that the restoration detector system 5 système and the selective restoration detector 56 depend on the operation output and deletion output indicators. In a real operation, the false state of the operation output indicator is connected to a possible input of the event code generator 68, bringing all the outputs to the zero state. The lowest order bit of the exit code is connected to a 0 U gate, the other input being the output® resulting from a connection of non-coincidence of the operation output and the deletion output. This is shown in Figure 6. Thus, if the operation output indicator is in the false state, the device generates either a system restore event code or a selective restore event code, depending on the state of the deletion output indicator.

The input / output stop detector 54 is shown in detail in FIG. 8 and comprises a type D rocker which is made active when the indicator. hold output goes to false and which is restored when the address output goes to false at its execution inputi being connected to its input D. As long as the address exit indicator is in the True state, the rocker can be set to the state of its input D which corresponds to the state of the operation input indicator when the holding output goes to False state.

The initial selection detector 52 of FIG. 2 is shown in FIG. 9 and comprises a rocker D and a door 0 D¹ with inverted output, ie a door not 0 U. The rocker is active to generate a True or False state output corresponding to the logic state of the input of the holding output when the address output goes to True state. The rocker is restored each time, the out-of-service or power-up restoration goes to the True state.

The end of operation detector 58 of FIG. 2 is represented in FIG. 10 as comprising a pair of doors QU with reverse outputs and a rocker D. The rocker is active by the passage of the state input to the True state if it is assumed that this state corresponds to that which is applied to the input D. The latter is in the True state only when the initial selection and the address output are in the False state. The rocker is restored by restoring either operation input or tensioning passing to the true state.

A block diagram of the data collection module is illustrated in Figure 3. The inputs are applied there from the channel interface module and the data collected by the data collection module which can be considered as the data output, are accessible to the microcomputer. The inputs of the interface module are connected to a series of receivers 100 - 112. The general lines, including nine bits in parallel, one of which is the parity bit, are connected to the data receivers 100. The information transmitted by the general lines can be a data, an address, a control byte or a state byte. The information applied to the data receiver appears at the output and is transmitted to the parity tester 116 and to the buffer information registers 114 · The party tester 116 provides an indication output d parity error each time the parity is wrong. Buffer data registers 114 include three seine bit registers arranged in six bytes. Consequently, the register stores the six bytes received by the data receiver 100. The buffer data register receives several control signals which determine by these control signals “” t these circuits if the data must enter the registers 114 “t if this is so, if the data must then enter the memory 128 or if it must be directly transmitted to the output of the buffer serial memory 152 · In this memory the first input data is the first output. The control inputs to the data buffer registers 114 are the lines; repeat data indicators, windows^svery data access, search, sector determination command. The buffer data registers 114 also receive an indication of the data byte counter 138 of the even / odd count of the data bytes and the complete indications of memories and record the active cycle of the memory control unit 134 · The outputs are data and in the case of commands for finding and determining sectors, the address information, this data and commands being transmitted to the data memory 128 and to the input selection I50 for the circuit 152 respectively. A control output designated memory storage is connected to memory control 134 to start writing data to memory 128.

The details of the buffer registers 114 of the data and of the associated logic are represented in FIG. 11 in which the three stages of register, each of which maintains two bytes of data are connected in

1425474 cascade, the bytes of data on the output of the third generic line of the receiver 100 in FIG. 3 being connected to the even-numbered sections of the multiplets of stage 1. The logical condition, represented in the form of simplified logic for controlling the passage of. bytes in the even and odd sections respectively are s

Data Repeating Indicator Multiplies by Ν '⁰ pair ac (Data window + Research + Sector determination);

Data Repetition Indicator s Odd multiplier x (Data window + Search -i- Sector determination).

The even number byte and its inverse are taken from the data byte counter 138. The data repetition indicator is transmitted from either receiver 102 a or 1Q2 b by the selector 102 c. Thus, if there is a window of data coming from the comparator and the logic 140 and a repeating indicator of the data coming from the selector 102 c, an even order byte goes into the section of stage 1 of the register 1102 and an odd-order byte goes to the bottom of the section of floor 1 of register 1102.₅the presence of a search command or of a sector determination command, when this presence is detected by the command decoder 124, causes the bytes to be entered in stage 1 of the register 1102.

If stage 2 of register 1104 is empty, the content of stage 1 is transferred to stage 2. If stage 3 of register 1106 is empty and stage 2 is complete, the content of the latter is transferred in stage 3. In this way, the data always travels to the last stage of the buffer registers 114 · The associated logic also provides a control signal for requesting memory recording which is connected to memory control 134 for start data transfer from floor 3 <read register 1106 to memory 128. The logic condition for generating a request for recording in memory esti

Research + Sector Determination + Complete Memory (Stage 3 complete x Recording Active Cycle + Stage 2 Complete). From this condition, it can be seen that the control signal is not established in the case of a command of

O research or sector determination. In these latter cases the information of stage 3 (representing the drive address information of the disk) is transmitted to the buffer memory with serial input and output by another logic described below. Similarly, the control signal is not generated if the memory 128 is complete. Such a condition results in the establishment of a Full Memory signal described below. However, if there is neither a search command nor a sector determination command and the memory is not complete, a memory recording request is established if one or other of the stages 2 and 3 is complete that the memory is not being transferred into the content of stage j. The active recording cycle of memory command 134 indicates that a recording cycle is in progress. The memory control 134, in response to a request for registration, transmits a write signal on the read / write line to the data memory 128 and, after the writing is completed, increases the address of the address register 130 write ”The word (two bytes) from the data buffer register 114 is therefore transferred into the memory at a location defined by the write address register 130.

The information collected in the data memory 128 may be requested by the microcomputer under the control of the memory control 134 and of the reading address register 132. The inputs of the microcomputer are not disseminated, for simplicity, but such inputs can cause a signal to be passed to memory control 134 and a read address to the read address register 132. As a result, the data memory 128 can transmit the data at the address indicated by the read address register 132. Likewise as long as the memory control 134 continues to receive pulses from the microcomputer, it continues increasing the address of the read address register and transferring the data from the data memory 128. If the microcomputer transmits a particular read address to register 132, the information series, read from the data memory 128, transmits only the data output starting with the address following just the last address read. Thus, under normal circumstances, the data is both read and written in series in the memory positions.

A comparison circuit 136 prevents the input data from being written when the data memory is complete and consequently destroys the recorded information which has not yet been read and transferred from the data memory 128. This is obtained by transferring the write address and the read address to the comparison circuit 136. When the two addresses are equal, a full memory output is transmitted to the memory storage request circuit of the unit 114 to inhibit subsequent requests to write to the data memory 128 (see FIG. 11). The complete memory output remains in the True state until new information is read from the data memory 128, thereby causing a change in the read address 132.

As mentioned above, the only data obtained in the data memory 128 is that which is transmitted to the buffer registers 114 during the existence of a data window control signal. The establishment of this last control signal constitutes one of the characteristics—

2425474 artistic yes allows the reduction of a data, that is to say the reception of all the data, but with selection of only a part of the data when the system is interested in its recording® The device for establishing the Information Window is described below. A receiver

5- 104 receives a repeating address indicator from the channel interface module and transmits this repeating indicator to an address register 118 "

When the repeating address indicator is received, the information on the general input line consists of the address of a device connected to the computer channel · - This address on the data is transmitted to the receiver 100 to be communicated to the address register 118 by means of an address repetition indicator. The address in the device of the address register 118 also addresses a direct access control memory 114 which comprises an address location separated by each device address. As a result, the outputs of the memory 144 transmit a control word which is recorded in the corresponding address of the address of the device. The control word recorded in the control memory

144 depends on the interest of the system in the particular device whose address is in the address register 118® The control word has milked parts: the account of the first byte, the account of the last byte and a pseudo address. The pseudo address, like the entry address, identifies a particular device. However, the pseudo address corresponds to the address in the memory associated with the microcomputer, in which all the information relating to the device can be collected. The designated part counts first byte contains the number of the first byte of the data that the system needs to collect. The part designated last byte count contains a number representing the last byte of the data that the system needs to collect. Suppose, for example, that the address corresponding to a certain device arrives on the given lines 100 and is selected to enter the device of the address register 118 by the repeating address indicator. Suppose, moreover, that the control word for this particular device contains its pseudo address as well as the count of the first byte corresponding to 16 and a last count byte corresponding to 31. The pseudo address will be transmitted directly by the input selection means 150 to the buffer memory 152. The numbers corresponding to the first and last bytes are transmitted to the comparator 140. Depending on the address of the device, the device and or the central processor will control setting up data on the channel »The data is taken by the interface module and transmitted to the data taking module on the general lines. Likewise, each data word on the channel is accompanied by a repeating data indicator which is also taken by the interface module and transmitted to the data taking module. The repeating data indicator is applied to receivers 102a or 102b and through them to a counter 13 & of data bytes. The data byte counter counts the bytes of data appearing on the channel during the particular sequence described. The output of the data byte counter 138 is transmitted to the comparator 140 where it is compared to the count of the first byte and to the count of the last byte. When the number in the data byte counter is equal to the count of the first byte, the data window is equal to the count of the first byte, the data window goes to True, and when the number in the byte counter becomes larger than the last byte count, the Data Window goes to False.

Consequently, the data window is in the True state for the duration during which the data comprised between the first and last multi15 plets is transmitted to the buffer register 114 · This way, the command word determines the particular part of the input data to be collected. The rest of the input data is ignored.

In the case of certain devices, the system may not be interested in the data. For these devices the control word in the direct control memory 144 has a first byte count part composed of 1 and a last byte count part composed of aero.

A simple log in the comparator 140- recognizes this condition and blocks the establishment of the data window. For some other devices, the system does not need information. For these devices, the control ®ot has a part of the first byte to the most significant bit is set to 1 and a part of the last byte whose most significant bit is set to zero. This condition is also recognized by the comparator 140. In this case, the Data Window is not generated, but an Address Rejection signal output changes to True and then blocks the recording of a series of information in the input and output buffer. series 152. It should be noted that the data byte counter is restored each time the repetitive command signal is in the True state. It suffices for the moment to know that the data byte counter is restored during each initial selection sequence on

I^e central processor channel ”The receivers 106 and 108 receive the repeated command and status signals respectively. The command repetition indicator intervenes each time a command byte appears on the general line. The same is true for the repeating indicator 4, 'state. · The indicators with repetition of state and of command, after reception by the receivers 106 and 108 respectively are transmitted to the device for selecting command / state recording 120. The input of the information receiver 100 is also connected to the record selection device 120. The function of this latter device is to decide whether the command byte or the state byte should be received by the command / state register 122 at the moment when the series of information is collected by the serial buffer 152. The record selection 120 and register 122 operate (the following generally follows. Each time a repeating command indicator is detected, the record selection device controls the recording of the command byte in register 122. If a subsequent state byte is of the form OOOOXXOO, or X may be either One or Zero, this indicates that the sequence on the channel which has been controlled by the central processor can intervene.

The record selection device 120, in this case, does not control the entry of the state byte in the register 122. The control byte remains in its original position to be transmitted to the serial buffer 152. D ' on the other hand, if the state byte is of a form other than OOOOXXOO, this means that the commanded sequence cannot intervene.

In this case, the recording selection device 120 controls the transfer of the state byte into the register 122 to replace the previously recorded control multi20. Likewise, the output line designated as initial non-selection enters into function and presents the state True when the state byte is not equal to OOOOXXOO.

A simple logic circuit for executing the logic of the selection device 120 and of the register 122 is shown in FIG. 12. An output

True of gate & U 1202 commands register 1214 to introduce the eight-bit byte appearing on the general line. This occurs under one of the following three conditions. First, if a command repetition indicator is in the True state, the recording command changes to the True state. Second, if the state repeat indicator is in the True state and the line NOT initial selection is in the True state, the AND gate 1204 produces a True input at the gate 0 U 1202 to pass the command. True. Third, if the repeat indicator e

state is in the True state and that any one or more of the byte lines 57, 56, 53, 52, 51 "t 5θ are in the True state, the combination of the logic circuit is not 0 U 1206, from the inverter 1208 and from the AND circuit 1210 causes the output of a recording command in the True state. The control line NON initial selection is the output Q of the rocker 1212 of type D, whose clock input receives the indicator with state repetition and whose input D is in the True state when the multiplet d state is equal to

OOOOXXOO. Thus when the state byte is not equal to OOOOXXOO, the input D is in the False state, and a flag with repetition of state is established simultaneously to change the output of the line NON initial selection to True state. In general, this indicates that the monitored device is not executing the initial selection sequence at the same time.

The general line, as well as the command repetition indicator, are also transmitted to a control decoder 124, which functions to decode the search and determination, sector commands and to detect the read-write condition of all the commands. Read and write is determined by the least significant bit of the control byte. If it is a Un, the command concerns the writing of the data transmitted by the channel in the control unit of the peripheral device. If it is a Zero, the command relates to the reading of data from the control unit for its transmission; to the canal. The read and write outputs of the command decoder are applied to the selector 102c to cause the selection, repeatedly, of the indicators with repetition of the data inputs and outputs.

In the central processor channel, the sector search and determination commands relate to the drive of the disks and result in a unique but short sequence of information circulating in the general lines of the channel. The single information is address information, but it must be distinguished from the multiplets of addresses accompanying the address indicator. These latest bytes address peripheral devices. The first which are accompanied by the data indicator represent the internal addresses of the disk drives. This training is treated as data by the monitor up to the entry included in the buffer information registers. When a search or sector determination command occurs, the monitoring system operates to short-circuit the data memory 128 and to transmit address information directly to the buffer registers

124 to 152 in order to be collected by the microprocessor. This is obtained using the command decoder 124 which receives the command words and provides a True output on the sector determination and search output lines when the commands are respectively determination; sector and research. The sector determination and search output lines are connected to the data buffer registers 114 as previously described to control the entry of the address information in the register 114.

A three-bit input event code is transmitted to the receiver 110 and introduced under control into the event translator 146 by the repeating event signal which passes through the receiver 112. In the

40- particular embodiment described here, there are seven entries of event codes §425 ^ 74 representing seven events on the channel of the central processor. The respective input events and event codes are s

<td>System Restauration</td><td> 000</td>

<td>Selective catering</td><td> 001</td>

<td>Stop i / o</td><td> 010</td>

<td>Linked initial selection</td><td> 101</td>

<td>Unbound initial selection</td><td> 100</td>

<td>Short occupancy</td><td> 011</td>

<td>Final procedure</td><td> 110</td>

<td colspan="2">The event translator 146 works to decode the event code.</td>

incoming event and provide an exit event code that depends on. part of the decoded input event code and part of the previous sequence of events. In order to determine the previous sequence of events, the event translator 146 also receives the following inputs: search, sector determination, initial non-selection, data received and data lost. The input designated data received is connected to the hashing machine 126 which is activated by the data repeating indicator and restored each time the address repeating indicator changes to the True state. Consequently, the line designated data received passes to the True state provided that the data was received following the presence of the half? repeating address indicator.

The input line designated data loss comes from simple logic, represented here as being a part of memory control 134 which makes the lost data output go to the True state when the complete memory output is True, the data buffer registers in the True state and that the data repetition flag is True ”The event translator 146 also provides an output to the controller 156 in the buffer with serial input and output to start the record in this buffer. It should be noted that the serial input and output buffer memory 152 which is a register stores the information which is transmitted to it in series, each series representing a group of data relating to a particular device connected to the channel of the central processor. Lp. buffer memory with serial input and output is shown as comprising a selection input part I50 and a buffer memory 152. The input of the selection part 152 selects the information order which is transmitted to it for its transmission in the buffer memory according to the output or the event code of the data acquisition module.

The information that is transmitted for recording in the serial buffer consists of the following parts s (l) Pseudo Address - The information identifies the particular device to which the information is attached, as well as an address in the memory from the microcomputer where all the information has to be collected.

(2) Write address - This information indicates the terminal address plus One in the data memory 128 where the information of the particular device is stored.

(3) The data byte count - This information which is obtained from the information byte counter 138 indicates the number of data bytes in the recording of the data transferred on the central processor channel.

{4) Data buffer output - This information, which is obtained directly from the data buffer registers 114, is only applied to the serial buffer if there is a sector search or determination command. This information is the address information for the training of the discs mentioned above.

(5) Command word / State - This information designates the particular command carried out by the device or the state of this device when the command is not executed or when the end of an asynchronous state has been given by a device to the channel. central processor.

(6) Exit or event code of the data acquisition module.

This is the information from the I46 translator indicating the particular event taking place on the central processor channel.

(7) Date - It is the time information of the date 154 Which indicates the time at which the information designated above is applied to the memory

152.

The buffer memory control device 156 is connected to the input counter 15 &amp; which keeps the recording track of the buffer memory 152. The purpose of the input counter 158 is to provide outputs indicating the time at which the buffer memory is empty, 75% full. The designation implying this fact is applied to register 160 of the state of the data acquisition module. When the serial buffer memory is completely filled, meaning that the most recent information which has been applied to it is lost, this indication is transmitted to the status register 160. The other inputs transmitted to the status register of the data acquisition module are given⁰ lost, the parity error of the parity checking device ll6 and the restoration of the system from the central processor channel ”. The content of register 160 of the state of the data acquisition module, which provides an indication of the conditions mentioned above, is available on the microcomputer. The data taking module also includes the address 148 of the data taking module which uniquely identifies the module of the particular collection of information. The last address is presented to the microcomputer accompanied by the content of the status register 160. The address of the data taking module is particularly useful whenever a set of data taking modules is connected to a single microcomputer.

The input event codes mentioned above are obtained by the channel interface module which monitors the signal groups on the central processor channel and provides the event codes corresponding to certain sequences of the channel. The particular sequences of the channel questioned above are standard sequences. The groups of signals arriving on the channel and the sequence of such signals corresponding to these events can be found in several publications, including the publication IB MN ° GA - 22 - In order to give a better understanding of the present invention, but at the risk of a certain simplification, the meanings of the above input sequences will be briefly explained.

The unbound initial selection sequence begins with an address sent on the channel from the central processor to a device and is followed in series by an address entry on the channel, a command output on the channel and an input of on the canal. The designated linked initial selection sequence is similar to the unbound initial selection sequence but it indicates that the channel is kept in communication with the particular device whose address is indicated even after the first command has been executed. In other words, this means that the previous command was for the same device. ”The system restore sequence indicates that all peripheral devices connected to a channel must be restored and the l / θ sequence indicates that the device selected for being in communication with the central processor receives an instruction to disconnect itself from this channel. The selective restore sequence restores one of these devices. The short occupation sequence occurs when an initial selection is attempted but the control unit or the device whose address is indicated are occupied. A terminal procedure sequence occurs either at the end of the transmission or when an asynchronous state indicates that an unselected device must be in communication with the channel, from the central processor.

There are eleven exit event codes from the translator

146 are ï

<td></td><td>Restoration of</td><td>system</td><td> 0000</td>

<td></td><td>Asynchronous state</td><td>following research or determination</td><td></td>

<td></td><td>sector</td><td></td><td> 0001</td>

<td> 40</td><td>Asynchronous state</td><td></td><td> 0011</td>

<td>Unbound initial selection</td><td> 0100</td>

<td>Linked initial selection</td><td> 0110</td>

<td>Short occupancy j Imperfect initial selection</td><td> 0010</td>

<td>Selective catering</td><td> 1000</td>

<td>Stop l / θ</td><td> 1010</td>

<td>Final procedure</td><td> 1110</td>

<td>Final procedure with data loss</td><td> 1111</td>

<td>Final search procedure</td><td> 1100</td>

<td>End of sector determination procedure</td><td> 1101</td>

The event translator 146 of FIG. 3 is shown in greater detail in FIG. 4. As shown in FIG. 4, the input event code of the channel interface module is transmitted to the register 502 for maintaining the code. and is synchronized with it by the True output of the Q terminal of the hashing machine 5θ4 which is controlled by the repeating event indicator. This event code maintained in register 502 is transmitted to an event translator which translates the event code into a data acquisition module, or output event code, depending on certain control signals which are given to it. transmitted. The True output at terminal Q of the monostable hashter 504 is also an output line of the event code translator 146 designated as the received event code. The True output of the terminal Q is associated with an AND circuit with the line buffer memory input serial output not complete coming from the control 156 of this memory to provide the control output of the recording in this memory. This logic head may be designated by a repeating indicator of the event exit code.

The inputs to the event translator 5θ0, in addition to the event code of the channel interface module, are data received, non-selection, initial, loss of data, sector search and determination. It will be noted that usually a control line and its inverse, that is to say, for example, search and non-search are connected simultaneously to all of the logic circuits of the system. However, in order not to unnecessarily overload the drawings and the description, often only one of these two control lines is indicated.

The logic of the event code translator 5θθ is shown in detail in FIG. 4 a as comprising a locking register 5θθ and a set of AND and 0 U gates connected as shown. The three bits of the channel interface module event code are recorded in the tap register 5θθ which provides the bits of the channel interface module event code and their reverse on six output lines. The command inputs are applied as shown, and the four

20 'output lines represent the four-bit event code for the data module.

Although the relationship between the three-bit event codes of the interface module and the four-bit event codes of the data acquisition module can be discerned by following the logic of FIG. 4, the following explanation is intended to provide a better understanding of this relationship.

Four event codes from the interface module lead respectively to four corresponding event codes from the plug module independent of the state of the control input lines. These are the designated events: system restore, selective restore, I / O stop entry / exit and short occupation. For example, the event code of the interface module 001 (selective restoration) leads to the exit event code 1000 (selective restoration).

The event codes of the interface module ï initial selection and linked initial selection result in corresponding event codes of the socket module if the control line not initial selection is in the False state. However, if the last control line is in the True state, each of the above event codes of the interface module results in

20; an event code 0010 from the plug module which designates a short occupation or an imperfect initial selection.

The event code of the final procedure interface module 110 can be translated into one of the five event codes of the plug module according to the state of several input control lines. If the lines

Data received is in the False state, the event code of the plug module is in the asynchronous state (0011). If the line: Data received is in the True state and one of the lines Search, Sector determination or Data lost is in the True state, the event code is final search procedure (llOO), final procedure sector determination (llOl) or final procedure with loss of data (llll). · If the Data line received is in the True state and none of the lines: Search, Sector determination, or Lost data is in the True state, the event code is final procedure (1110).

If we refer again to FIG. 4, we see that the data entered in the buffer memory 152 for each series is arranged in groups of words. Each series includes two groups of four words, each word includes eight-bit bytes. A diagram, in the form of blocks, of the memory 152 and of the associated device, that is to say input selection 152, control 156 and input counter 158, is illustrated in FIG. 7.

The eight bytes constituting the four words 0—3 of a series are selected by the data selector 150 of the buffer memory, one byte at a time in response to the address of the selector.

Each of the lines designated 0 -15, “t connected to the data selector 150 of the buffer memory, represents a byte with eight hits, the hits being in parallel. The particular byte selected to appear at the output depends on the four-hit selection address that is transmitted by the controller 156 of the serial buffer.

The relationship between words 0-3, input byte lines at selector 150, 1 ^ four-hit event code passed to control

156 from the buffer ° t the address of the selector is described below.

Words numbered 0 and 1 are part of each series regardless of the series event code. The pseudo address which is composed of eight bits is transmitted on the byte line 0 and constitutes the first eight bits of the word 0. The word command / state, composed of eight bits is transmitted on the byte line 1 and constitutes the second eight bits of the word 0. The event code output at four bits and the first four bits of the twelve-bit date stamp is transmitted by the byte line 2 and constitutes the first byte of the word 1, The last eight bits of the date stamp are transmitted by the byte line 3 and constitutes the second multiplet of the word 1.

The four bytes above always constitute the words 0 and 1 in the series. When the repeating indicator of the output event code goes to the True state, a counter of the control 156 of the buffer memory starts the counting, starting from the account 000 and transmits it to the address input of the selector 150. The count advances from 000 to 011 thus causing the selector 150 to transmit the bytes sequentially on the byte lines 0, 1, 2 and 3 on the output of the selector.

The resulting action depends on the exit event code and the state of the Sector Search and Determination inputs. If the most significant bit of the exit event code is 0, words 0 and 1 are the only words included in the information series'. Thus no other byte line is selected by the selector 150. If the most significant bit is a 1, the four words are to be included in the series. In this last condition which is easily detected by the control 156 of the buffer memory, we will note the state of the most significant bit of the event code 35 m * nt of output, the counter advances by four accounts in addition starting from 100 to finish to 111. The address of the selector, however, also depends on the state of the lines: Research and Sector determination. If the state of the latter is False, the addresses transmitted to the Selector 150 are successively 0100, 0101, 0110 and 0111. Thus the events on the lines of multi40 plets 3, 4, 5 6 are connected sequentially to the output of the selector to constitute the words 2 and 3 of the series. If the state of the lines Search or Sector determination is True, due to the AND gate 1304, the successive addresses are 1100, 1101, 1110 and 1111. The bytes on the lines of bytes 12, 13, 14 and 15 are selected successively .

The sixteen bits of the data byte counter I38 (FIG. 5) are transmitted to the selector on lines 4 and 5. The sixteen-bit address of the memory of the data acquisition module of the write address register 130 (FIG. 3) ) is transmitted to the selector on the byte lines 6 and 7. The sector search or determination address, consisting of four bytes obtained from the data buffer registers 114 (FIG. 3} is transmitted by the byte lines 12 - 15 ·

The bytes of the selector 150 are introduced into the serial input and output buffer memory 1306 under the control of a write input of the control 156 of the serial buffer memory, at an address corresponding to that recorded in the address counter 1308. When the buffer / serial control counter advances for placing the bytes on the output line of the selector 150, the registered address counter 1308 is advanced by the value UN and the write input is transmitted to the memory 1306; a unit is also added to the input of counter 158.

Each time the holding registers 1312 a and 1312 b are empty, the control of the serial buffer memory causes bytes to be output from the serial buffer memory 1306 and their recording in the holding registers.

Whenever a series is to be transmitted to the microcomputer for formatting and presentation to the user, a request is recorded in the control of the serial buffer memory. This entails for the latter the presentation of the information from the holding register to the microcomputer and the transmission of a read input to the memory 1306 for transmitting the byte recorded in the address maintained in the address counter 1310. Two successive bytes are read from memory 1306 and kept in the holding registers 1312 a and 1312 b respectively. The counter 1310 is advanced by one unit for each byte read from the memory I306. Similarly, each byte read results in the transmission of - 1 at the entry of the counter i58. The latter keeps track of the number of bytes recorded in memory 1306 and switches the empty output lines, filling to 75% and full to the True state when these conditions exist respectively in memory 1306. The address selector 1314 selects a read or write address according to whether a read or write operation is to be performed.