Stereophonic coder employing a multilevel switching system for the generation of the stereophonic signal
Abstract
PROCESS FOR THE PRODUCTION OF A STEREOPHONIC ENCODER, CHARACTERIZED IN THAT IT CONSISTS OF USING SIGNALS S1 AND S2, ALREADY PRE-EMPHASIS AND RELATING TO THE LEFT AND RIGHT CHANNEL OF A STEREOPHONIC SYSTEM, BY MODIFYING AND COMBINING THEIR LEVELS DURING INTERVALS OF SUCCESSIVE TIMES, TO FORM A WAVEFORM WITHOUT HARMONICS, UNTIL THE SIXTH INCLUDED; THIS RESULT BEING OBTAINED BY SWITCHES WHICH TAKE PLACE AT INTERVALS OF TIMES EQUAL TO 18 F, F BEING THE FREQUENCY OF THE CARRIER, SO THAT, IN SUCCESSIVE INTERVALS, A SIGNAL IS PROPORTED TO THE FOLLOWING VALUES: (CF DRAWING IN BOPI) THESE VALUES ARE THEN REPEATED IN THE REVERSE ORDER, STILL THEN IN THE SAME ORDER, AND THEREOF.

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4 claims: 3 independent, 1 dependent
- 1REVENDICATIONS 1 - Procédé pour la réalisation d'un codeur stéréophonique, caractérisé en ce qu'il consiste à utiliser les signaux SI et S2, déjà préemphatisés et relatifs au canal gauche et au canal droit d'un système stéréophonique, en modifiant et combinant leurs niveaux pendant des intervalles de temps successifs, de façon à former une forme d'onde dépourvue d'harmoniques, jusqu'à la sixième incluse ; ce résultat étant obtenu par des commutations qui ont lieu à des intervalles de temps égaux à 1/8 f, f étant la fréquence de la sousporteuse, de telle façon que, dans les intervalles successifs, on engendre un signal S proportionnel aux valeurs suivantes :1) Sj (8 -TT - Tv 1Γ2) + S 2 (8 + ΤΓ+ TT |)~2)
- 22) S (8 -ΤΓ ) + S, (8 + TT) 2 .(1)
- 33) Sj (8 +ΤΓ) + S 2 (8 - TT )
- 44) S x (8 + TT + TT J~2) + S 2 (8 - TT - TT 1Γ2) ces valeurs étant ensuite répétées dans l'ordre inverse, encore ensuite dans le même ordre, et ainsi de suite. 2 - Procédé selon la revendication 1, caractérisé en ce que ladite fréquence f est de 38 kHz. 3 - Procédé suivant l'une des revendications 1 et 2, caractérisé en ce que le signal pilote du codeur stéréophonique est réalisé en utilisant des commutations qui se suivent selon des intervalles de temps de 1/152000 sec. , de façon à donner en séquence des valeurs proportionnelles aux valeurs suivantes :1) 1 2) 1 3) - 1 4) - 1 -Ê ces valeurs étant ensuite répétées dans l'ordre inverse, dans le même ordre, dans l'ordre inverse, et ainsi de suite. 4 - Procédé selon la revendication 1, caractérisé en ce que l'on augmente le nombre des commutations en obtenant un signal où sont également supprimées les septième et neuvième harmoniques, et éventuellement, en outre, des harmoniques successives. 5 - Codeur stéréophonique, caractérisé en ce qu'il comporte plus de deux dispositifs interrupteurs pilotés de façon synchrone et associés à des 5 diviseurs de tnesion ou de courant, de façon à réaliser les harmoniques jusqu'à la sixième, et éventuellement, en outre, aussi des harmoniques supérieures, en mettant en oeuvre le procédé suivant l'une quelconque des revendications 1, 2 et 4. 6 - Codeur stéréophonique selon la revendication 5, caractérisé en ce 10 qu’il comporte des moyens interrupteurs et diviseurs qui réalisent le signal pilote par la commutation à plusieurs niveaux, éliminant les harmoniques dudit signal au moins jusqu'à la sixième incluse. 7 - Codeur stéréophonique suivant la revendication 6, caractérisé en ce que les commutations utilisées pour former le signal pilote ont lieu à des inter15 valles de temps de 1/152000 sec. Ρί.1.2 2425185
Independent claims4
64 paragraphs in 36 sections, as filed
© Holder: Idem © © Agent: Armengaud Aîné, 3, avenue Bugeaud, 75116 Paris.
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2425185
The subject of the present invention is a method and a device for obtaining, from two lines - respectively channel A (left) and channel B (right) - of a normal stereophonic program, the multiplex signal for the modulation of the transmitter. by frequency modulation according to the system recommended by the CCIR, and called the Pilot Frequency System.
The devices already known which perform this function, called stereophonic coders, are based on several operating principles. In particular, the best results have been obtained by the so-called time division principle.
Figure 1 of the accompanying drawings shows, in its essential lines, the block diagram of one of these coders. In this diagram, the references II and 12 designate the inputs of the two lines (channel A and channel B); Al and A2 are amplitude equalizers which must give the signal the necessary pre-emphasis (i.e. amplitude equalization, with enhancement of high frequencies) recommended by the CCIR, and Cl and C2 are two linear amplifiers . An oscillator L at 38 kHz controls the electronic switch formed by the switches DI, D2 so that they are alternately open and closed for 1/76000 sec.
Figure 2 shows the signal obtained downstream of the switch when the effect of resistors RI and R2 is neglected and a sinusoidal signal is applied only to input II.
The presence of resistors RI, R2, R3 modifies the signal obtained, as seen in Figure 3; the resistance values are chosen so that VI / V2 = (4 + 1T) / (4 -11), with the aim of obtaining at the output of the low-pass filter F, phase equalized and with border at 53 kHz , the signal shown in Figure 4. This signal is summed to the pilot sinusoidal signal at 19 kHz obtained from the same oscillator L at 38 kHz, followed by a module 2 frequency divider, indicated by G, by a filter R which eliminates the harmonics and by a phase shifter H.
The output signal of the summator S, amplified by M, modulates the frequency modulation transmitter.
This type of apparatus causes considerable difficulties for the adjustment of the filter F, since, to obtain a good quality of transmission, the amplitude response of the filter, up to 53 kHz, must be contained in a few tenths of dB, and since the associated phase curve must be linear between a few degrees. At the same time, the filter must attenuate the harmonic frequencies beyond 99 kHz which are generated, during the modulation process, by the electronic switch formed by DI and D2. Indeed, these switches produce a square wave of frequency 38 kHz, modulated in a balanced way, that is to say with carrier suppressed, by the signals of the program. Spectral analysis of the resulting signal shows that around frequency values corresponding to the odd multiples of 38 kHz, there is again a spectral distribution similar to the useful distribution existing around the value 38 kHz, but with amplitudes 1: n , n being the order of the harmonic considered. Consequently, the lowest value among the frequencies to be eliminated is the third harmonic of the signal at 38 kHz, from which the maximum value of the modulating frequency must be subtracted, which is equal to 15 kHz (3 x 38 - 15 = 99 kHz).
We also know that the waveform, a period of which is shown in Figure 5, is devoid not only of the harmonics, but also of the third and fifth harmonics, provided that the proportions are as seen in the drawing , that is to say that the transitions represented in FIG. 5 by the references 1, 2, 3, 4, 5, 6, take place in correspondence of the times Τ / 8, T / 4, 3T / 8, 5T / 8, 3T / 4 and 7T / 8, and that the signal levels indicated by I, H, 311 and IV are in correspondence, proportional to the numbers K, K 4 fz, K 4 2 4 Γζ, K 4 2 4 2] ^ z> K being any constant.
The object of the present invention is a multi-level switching method for applying the properties of the waveform described in the preceding paragraph and shown in FIG. 5, to produce a stereophonic coder in which the filters for the signal stereophonic and the pilot signal (corresponding respectively to the filters R and F of Figure 1), are considerably simplified. The method is implemented downstream of two amplification chains, of known type, of the two stereophonic lines (channel A and channel B) which give the electrical signals SI and S2 (Fig. 1).
The method according to the invention for producing a stereophonic coder consists in using the signals SI and S2, already pre-emphatized and relating to the left channel and to the right channel of a stereophonic system, by modifying and combining their levels in successive time intervals, so as to form a waveform devoid of harmonics up to and including the sixth, this result being obtained by commutations which take place at time intervals equal to l / 8 f (f being the frequency of the subcarrier, which, according to the standards currently in use, is 38 kHz), so that, in successive intervals, there is a signal S proportional to the following values:
1) S (8 -TT - TT | / 1) + S (8 + ΤΓ + TT /?)
X c *
2) Sj (8 -1Γ) + S<sub>2</sub> (8 + -ΓΓ) (1)
3) S<sub>1</sub> (8 + TT) + S<sub>2</sub> (8 - TT)
4) Sj (8 + TT + TT iTÏÏ) + S<sub>2</sub> (8 - TT -TT | / ~ 2), these values then being repeated in reverse order, again in the same order, etc.
According to a preferred embodiment of the invention, these switching operations take place at intervals of 1/304000 sec.
This solution has the advantage of allowing to move to 251 kHz (7 x 38 - 15 = 251) the minimum frequency beyond which the following filter must start to attenuate, since the waveform obtained is devoid of harmonics up to and including sixth.
The pilot signal is then produced using switches which follow each other at intervals of 1/152000 sec. , so as to successively supply levels proportional to the following values:
1) 1 + lFT
2) 1 (2)
3) - 1
4) - 1 - JT, these values then being repeated in reverse order, in the same order, in reverse order, etc.
The invention also relates to a device for implementing this method, this device being characterized in that it comprises more than two positive switches controlled synchronously and associated with voltage or current dividers, so as to produce a stereophonic coder.
Figure 6 shows the waveform downstream of the electronic switch in the hypothesis, already considered for Figure 3, where a sinusoidal signal is applied only to the input of channel A.
Figure 7 shows a preferred embodiment of a stereophonic coder implementing the method according to the invention.
In this figure, OSC designates an oscillator which gives a square wave at 304 kHz; the microcircuit 40163 is a digital logic circuit formed by 4 flip-flops connected in series, of which Q, Q, Q and Q are the outputs; the
VA u “J flip-flops are interconnected so as to form a binary synchronous counter which advances by one step at each transition from the LOW state to the HIGH state of the signal at 304 kHz applied to the GP input; the microcircuits 4028 are decoders which transform the binary code 1-2-4-8 coming from Q, Q, Q, Q in v * w ά the HIGH state of one of the outputs 0θ, 0 ^, 0 ^, 0 ^, 0 ^, 0θ, according to the decimal code corresponding to the binary code applied to the inputs; each of the microcircuits 4027 is formed by two flip-flops of the JK type, and, in this embodiment, a HIGH state is applied at the same time to the input J of a flip-flop, and a BAS state to the input K of the same rocker, or vice versa; in these two situations, the corresponding Q and Q outputs reproduce the state of the inputs at the time when a transition from the LOW state to the HIGH state is applied to the CP input. In a third situation, a BAS state is applied to the two inputs, and, in this case, after said transition, the outputs Q and Q remain in the previous state.
The SD5000B microcircuits are quadruple electronic switches, of which P and D are the poles, and G is the control input: if the state of the latter is HIGH, the switch is closed; if the state is LOW, the switch is open.
The signals of the two stereophonic channels A and B are applied, respectively, to the two inputs El and E2 and pass through the known circuits DI and D2, where the pre-emphasis circuits are connected; there are then the amplifiers F1, F2, of known type, with a low output impedance, which, through the capacitors C1 and C2, send the signals SI and S2 to the electronic switches. Each transition from LOW to HIGH of the signal emitted by the oscillator at 304 kHz advances the counter 40Γ63 by one step, so that its outputs Ωθ,, Ω ^ "have cyclically, during successive time intervals, the following states :
1) L, L, L, L
2) H, L, L, L
3) L, H, L, L
4) H, H, L, L
5) L, L, H, L
6) H, L, H, L 7) L, H, H, L
8) H, H, HjL
9) L, L, L, H
10) H, L, L, H
11) L, H, L, H
12) H, H, L, H
13) L, W, H, H
14) Η, Η, Η, Η
15) Η, Η, Η, Η
16) H, H, H, H, where L indicates the LOW state, and H the HIGH state.
These signals are applied to the inputs of the two microcircuits 4028.
For circuit 4028-1, in correspondence with the above intervals, the following outputs go to state H:
V ° 0
2) 0<sub>χ</sub>
3) 0<sub>2</sub>
4) none <sup>5)</sup> °4 <sup>6)</sup> °5
î) o<sub>6</sub>
8) none
9) 0<sub>0</sub>
10) Ο<sub>χ</sub>
H) 0<sub>2</sub>
12) none <sup>13</sup>> <sup>θ</sup>4
14) 0<sub>5</sub> !5) 0<sub>6</sub>
16) none while the outputs not mentioned remain in state L.
It can be noted that states from 1 to 8 are identical to states from 9 to 16, and therefore it is sufficient to examine states 1-8.
The outputs of the microcircuit 4028-1 are connected to the inputs J and K of the first and second sections of the microcircuit 4027-1 and of the first section of the circuit 4027-11. Correspondingly, in the time intervals described above, at the end of which there are the LOW to HIGH transitions of the signal at 304 kHz applied to the CP inputs, the corresponding outputs Qj - I, Q<sub>2</sub> - I, Qj - II pass respectively to the states:
1) L, L, L
2) H, L, L
3) H, L, H
4) H, H, H
5) H, H, H
6) H, L, H
7) H, L, L
8) L, L, L
These outputs are respectively connected to the control inputs G3, G4, G1 of the SD 5000 BI microcircuit, to close the corresponding switches. Through these, the signal is passed, in the successive time intervals corresponding to the above intervals, in the resistors:
1) R5
2) R5, R2
3) R5, R2, R4
4) R5, R2, R4, R3
5) R5, R2, R4, R3
6) R5, R2, R4
7) R5, R2
8) R5
At the same time, the signals from Qj-I, Q ^ -I, are applied to the control inputs G3, G4 and Gl of the SD 5000 B-microc microcircuit. In the corresponding time intervals, the signal S2 passes through the resistors
1) R8, R9, RIO, R6
2) R9, RIO, R6
3) R9, R6
4) R6
5) R6
6) R6, R9
7) R6, R9, RIO
8) R6, R9, RIO, R8
Since all the resistors are connected to the input of the jaA 715 amplifier microcircuit, arranged so as to have a low input impedance, the currents arriving at this input are proportional to the voltage applied upstream of the resistors, as well as to the conductance of these resistors. Consequently, with the resistance values indicated, the total current which arrives at input 4 of the amplifier fiA. 715 is proportional to the levels given by equations (1).
The operation of said switches introduces into the useful signal an impulsive noise of fundamental frequency 304 kHz, provided that these operations are followed regularly, every 1/304000 sec. In the sequences of time intervals described above for the control of the switches, there is no switching between the intervals 4 and 5 and between the interval 8 of a sequence and the interval 1 of the following sequence .
This would give rise to a noise component at 76 kHz. This drawback is remedied by sending the signal de to G2-II, so as to produce the two signals which are missing in each sequence.
The pilot signal is obtained by using the signals leaving the gates Q ^ -IH, and, by the resistors R11, R12, R13, the levels given by the relations (2) are obtained; in addition, the pilot signal is produced with a delay of 22.5 degrees from the exact position with which it is to be inserted. To sufficiently attenuate the seventh and ninth harmonics of the pilot signal, the low-pass filter formed by C3, C4, R14 is provided, which, in addition, delays in phase by 157.5 degrees (157.5 + 22, 5 = 180) the 19 kHz signal. The signal is then amplified by T1 and brought, through RI 5, to the same input 4 of the microcircuit pA 715.
The jiA microcircuit. 715 supplies the low-pass filter formed by C5, C6, C7, C8, L1 and L2, which has the border frequency of 200 kHz and supplies the transistor T2 whose network, formed by C9 and R16, performs a small correction of phase. Next there is the amplifier N of known type, with high input impedance, which supplies the output terminal U of the device.
Non-electrolytic resistors, inductors and capacitors must have an accuracy of at least 1%.
It is obvious that, according to the illustrated principle, one can increase the number of commutations by obtaining a curve similar to the curve of Figure 5, but devoid of harmonics beyond the sixth (for example, up to the sixth) ; this embodiment is also included in the field of the invention.
The circuits indicated in Figure 7 by their trade mark are manufactured respectively by the Fairchild Companies (circuits 40163, 4028, 4027, pA 715) and Signetics ”(circuit SD 5000 B).
There are also commercially available equivalent circuits, indicated by other acronyms.
The changes and modifications that can be made to Figure 7 do not present difficulties for experts in this field of technology.
Contents36
2 sheets
Sheet 1 Sheet 2
Every citation, both ways
| Document | Relation | Office | Category | Cited during |
|---|---|---|---|---|
| US3789323A | Cites | United States of America | A | Search report |
| US3902019A | Cites | United States of America | A | Search report |
| US3962551A | Cites | United States of America | A | Search report |
| GB875091A | Cites | United Kingdom | A | Search report |
11 members in 6 offices
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 6803178 | Italy | A | |
| 6803178 | Italy | A |
Members11
| Document | Office | Kind | |
|---|---|---|---|
| NL7901323A | Netherlands (Kingdom of the) | A | |
| DE2850555A1 | Germany | A1 | |
| GB2020519A | United Kingdom | A | |
| FR2425183A1This record | France | A1 | |
| US4264784A | United States of America | A | |
| GB2020519B | United Kingdom | B | |
| FR2425183B1 | France | B1 | |
| IT1159657B | Italy | B | |
| DE2850555C2 | Germany | C2 | |
| NL188005B | Netherlands (Kingdom of the) | B | |
| NL188005C | Netherlands (Kingdom of the) | C |
Numbers
- Publication
- 2425183
- Application
- 7901310
Titles2
- French
- CODEUR STEREOPHONIQUE ET SON PROCEDE DE FABRICATION
- English
- STEREOPHONIC ENCODER AND ITS MANUFACTURING METHOD
Classification
- CPC, 1
- H04H20/48
- IPC, 2
- H04H1 00
- H04H20 48