Data processing systems including cache stores

(74) Agent: Harlé and Léchopiez.

D

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The present invention relates to data processing systems and, more particularly, systems having a memory pre-extraction capacity.

In high power systems and multiprocessors, the performance of data processing units has been improved by introducing a cache memory or a fast buffer unit between a main memory unit or large capacity auxiliary memory of the system and the central processing unit. To further increase system performance, systems have also been provided with a prefetch capability which consists of the cache being able to automatically extract a next sequential line of data after providing the requested d ata line to the central processing unit. .

A disadvantage of these systems is that they do not take into account conditions which modify the basic principle according to which the following sequential line could be extracted directly from the main memory. To avoid this drawback, algorithms have been introduced into a system making it possible to pre-extract a following sequential line from the main memory by the rapid buffer and algorithms making it possible to replace the lines present in the rapid buffer which can be modified dynamically. compared to the type of program running through the use of a system control console. In particular, the system includes a maneuver register which corresponds to the variables of the pre-extraction control algorithm. Such variables are based on indications relating to previous rows requested.

Although the above provision constitutes a change with regard to access to a next sequential line before a request is made, it has the disadvantage of basing the request for pre-extraction on an arbitrary circumstance corresponding to the byte or part of a particular line that was indicated by a previous request. Although this has an advantage in certain types of operations, it may result in a decrease in performance in other cases. In particular, automatic accesses can increase memory congestion.

A first object of the present invention is therefore to have a data processing system having an improved memory pre-extraction capacity.

In systems with a cache memory, an associative memory is normally used to store block addresses which indicate which blocks are loaded or are in the fast cache or buffer. When an extraction or read request occurs, the associative memory is interrogated to determine whether the block containing the addressed word is in the cache memory. If this is not the case, this word as well as associated words of a block are extracted from the main memory and stored in the cache memory or buffer.

We generally recognize the cost advantages offered by the cache memory which contains a limited number of blocks and which minimizes the size of the associative memory. However, we have also highlighted the drawbacks which result from the memory size limitations in the case of block transfers. By avoiding such disadvantages, a fast memory system achieves a high degree of simultaneity of execution in which additional accesses to the memory system can be executed after the transfer of a block is started. US Patent No. 3,588,829 gives an example of such a system.

By obtaining such simultaneous execution, it is possible to receive more than one request specifying the extraction of data from the same block. To avoid the generation of multiple main memory or auxiliary memory commands, additional comparison circuits or associative memory circuits which are associated with multiple command bits are included in the system to detect incompatible requests. operation, additional, comparisons are made and the results are stored for use in command extraction. Such arrangements have resulted in increased cost and complexity. In addition, such arrangements are unable to process several different types of orders, resulting in increases in transaction recoveries.

Another object of the present invention is therefore to have a buffer or cache memory arrangement which allows a high degree of simultaneity of execution while minimizing the cost and the complexity.

The present invention provides a cache unit to be implemented with a data processing unit for

3.

obtaining rapid access to instructions and data extracted from a main memory coupled to said cache unit in response to. memory commands received from said data processing unit, each command comprising a command code and an address, said cache unit comprising:

a register for storing a memory command received from said data processing unit and to be transmitted to the main memory;

a buffer memory comprising a set of addressable word locations in a set of groups of word location blocks, each group and each block being defined by a group address and a block address, respectively;

a data directory comprising a set of locations corresponding in number to the number of groups in said buffer memory which can be accessed by said group addresses, each location of said data directory memorizing addresses of blocks of words in the associated group memorized in said buffer memory, said data directory responding to said group address which corresponds to a least significant part of said control address for reading said block addresses corresponding to a most significant part of said control address;

a command directory comprising a set of locations corresponding in number to said number of groups and which can be accessed by a group address, each location of said command directory comprising several command bits to indicate pending operations;

comparison means coupled to said data directory for comparing said addresses of blocks read in said data directory with the most significant part of said control address and for generating correspondence detection signals - no correspondence indicating whether the requested data are yes or no stored in said buffer memory;

a detection circuit coupled to said comparison means and to said command directory, said detection circuit for generating a detection signal of absence of cache match indicating whether the cache unit is requested to extract the requested data from said main memory; and control means coupled to said register, to said buffer memory, to said data directory, to said control directory and to said detection circuit, said control means operating to generate signals in order to switch a predetermined bit of said bits to a first state corresponding to the specified block and write the address of the control block in the associated location of the data directory when the control means are conditioned for a signal detecting no cache match generated in response to the read memory command loaded in said register, said predetermined bit of said command bits in said first state indicating that an operation to perform a transfer of requested data is pending , said control means being disabled on reading said predetermined bit of said control bits in response to a next memory command to issue said next command to of main memory for the same data.

The present invention further provides a data processing system comprising:

an addressable main memory comprising a set of word locations for storing information comprising data and instructions;

a fast buffer memory coupled to said main memory to provide immediate access to the data and instructions extracted from said main memory, said buffer memory comprising a set of addressable locations and comprising control means for extracting information from said main memory, and processing means coupled to said fast buffer memory, said processing means processing instructions, each instruction comprising a part of operation code, said processing means comprising control means for generating signals comprising memory commands necessary to execute said instructions, said control means comprising a decoder circuit responding to signals indicating a portion of coded operation code to specify a predetermined class instruction to generate memory control signals joined to coded control signals specifying a predetermined type of memory operation buffer reading, and the buffer control means operating in response to said coded control signals to generate signals transmitting said memory control signals to the main memory to extract the data specified by said control signals when said data is not loaded into said buffer for extracting this data in order to store it in advance in said buffer without interrupting the operation of said means of processing, which facilitates the execution of each predetermined class of instructions.

In a preferred embodiment of the present invention, a data processing system comprises a fast buffer or cache unit which connects at least one data processing unit and a main memory. The processing unit operates under microprogrammed control and includes logic control circuits to establish the different operating cycles of the processing unit. In addition, certain micro-instruction words accessed during the execution of certain types of instructions are coded to specify a read-ahead operation. Likewise, the logic control circuits also include means for generating a read-ahead command by the cache unit for such types of instructions.

The cache unit, in response to each advance command, operates to extract from the main memory a block of data specified by the instruction executed when the requested data has not been loaded first into the unit d cache. During operation, during the execution of certain types of program instructions, the control firmware or the control logic circuits generate read-ahead commands by the cache memory at predetermined points during the execution of these instructions In this way, the data normally required at a later point in the execution of an instruction can be extracted in advance from the main memory and loaded into the cache memory. while other operations included in this instruction are performed.

The cache unit comprises a set of word locations divided into several groups of blocks of word locations, a data directory comprising a set of locations corresponding in number to the number of groups and a command directory comprising a set of multiple bit locations corresponding in number to the number of blocks. The system further includes an input buffer for storing a set of memory commands, generated by the data processing unit and the logic control circuits. The logic control circuits include a decoder circuit coupled to the buffer and to said control directory.

The decoder circuit operates to selectively set one of the bit locations identified by the memory command to a predetermined state. This occurs when the order requests an operation which cannot be completed immediately but which must remain pending for a minimum of time. During the processing of the orders subsequently received, the contents of the order directory are accessible. When a next memory command is received that specifies information requested by previous commands, the contents of a bit location in the command directory indicate whether the operation that was started is still pending or pending. When the content indicates that the operation is pending, the control circuits signal to the data processing unit that it must stop operating in the cases where the requested information is immediately necessary. The control circuits further include sequencing control circuits. When all of the information necessary to complete the pending operation has been stored in the cache unit, the sequencing control circuits automatically re-execute the next command and authorize the processing unit to continue an operation.

By indicating the contents of the command directory during the processing of a normal command in parallel with the data directory, the system is able to detect the presence of incompatible commands and prevent the issuance of duplicate commands. In addition, the arrangement allows the processing of certain commands generated by the data processing unit which do not oblige to stop the operation of the processing unit.

Furthermore, the arrangement according to the present invention provides indications of states with regard to the accomplishment of these processed operations.

Embodiments according to the present invention will now be described, by way of nonlimiting example, with reference to the appended drawings in which:

Fig.l shows a functional block diagram of a system according to the present invention;

Fig.2 is a block diagram of the central processing unit 700 and the cache memory 750 of Figure 1;

Figs.3a to 3j show in more detail the different blocks of Figure 2;

Ιθ Fig.4 shows the cache unit in more detail

750 of Figure 2; . Figs.5a to 5e represent the lines from which the different interfaces of Figure 1 are made;

Figure 6a illustrates the format of the control memory control unit of Figure 1;

Figure 6b illustrates the format of the micro-instruction words of the execution control memory of Figures 2 and 3;

Fig.7 illustrates the format and coding of a formatting instruction used to explain the operation of the present invention;

Fig.8 is a diagram to illustrate the operation of the system of Figures 3a to 3j and 4, produced according to the present invention;

Fig.9 is a diagram which develops the different cycles necessary to process the instruction of Figure 8 according to the present invention;

Fig.10 is a flowchart showing the sequence order of the processing unit 700 for processing the instruction of Figure 8 according to the present invention;

Fig.11 is a state diagram used to explain the sequence order of the hardware of the device of the present invention;

Fig.12 is a flow chart used to explain the operation of the preferred embodiment of the invention;

Figs.13a to 13d illustrate the formats of certain types of instructions used to describe the operation of the present invention;

The system of FIG. 1, according to the present invention, comprises at least one input-output processing unit (I0PP) 200, a system interface unit (SIU) 100, a fast multiplexer (HSMX) 300, a slow multiplexer (LSMX) 400, a central processing unit 700, a cache memory 750, at least one memory module corresponding to a local memory module 500, and at least one memory module corresponding to a remote memory module 800. Some of these blocks are connected to a door of a group of doors of the interface unit. that of system 100 via a set of lines of different types of interfaces 600 to 603. In particular, the input-output processing unit 200, the cache memory 750, and the fast multiplexer 300 are connected to gates G, E and A, respectively, while the slow multiplexer 400, 1e local memory module 500, and the main memory module 800 are connected to gates J, LMO and RMO, respectively. The central processing unit 700 is connected to cache memory 750.

The input-output system of FIG. 1 can be considered as comprising several active modules ”, passive modules and memory modules. The IOP 200 processing unit, the central processing unit 700 and the fast multiplexer 300 act as active modules in the sense that each has the capacity to issue commands. The active modules are normally connected to doors A to H while the central processing unit 700 is connected to door E by via cache unit 750 and interfaces 604 and 600.A set of passive modules are connected to three doors J, K and L. These modules correspond to the slow multiplexer 400 and the system interface unit 100 and are units capable of intercepting and executing commands sent to the lines of an interface 601, 'as will be described below. The last group of modules constitutes local memory modules, and main memory modules capable of executing two different types of commands sent on the lines of an interface 603.

The input-output system of FIG. 1 normally functions as an input-output subsystem responding to input-output instructions issued by the central processing unit 700. The gates E and F include interfaces for connecting the multiplexer modules or the processing unit modules of FIG. 1. These interfaces are described in more detail in the following description.

With regard to the present invention, the central processing unit 700 is of conventional design and can be produced like that described in US Patent No. 3,413,613. In the preferred embodiment, the input-output processing unit 200 initiates and terminates channel programs necessary to execute input-output instructions, requests to interrupt processing received from the interface interface unit. system 100, and directly controls mechanography peripherals connected to the slow multiplexer 400. The unit 200 is connected to ZThe gate G via the data interface 600 and a interrupt interface 602.

The slow multiplexer 400 which can be considered conventional with respect to the present invention, makes it possible to connect slow peripherals by means of peripheral adapters each of which is connected to the lines of a device adapter interface (DAI) .These interfaces and adapters can be produced like the units described in US Patent No. 3,742,457, assigned to the assignee of this patent application. Slow peripheral devices include card readers, card punches and printers. As can be seen in FIG. 1.1, the multiplexer 400 is connected to the gate J via a programmable interface 601.

The fast multiplexer 300 directly controls transfers between groups of disk drives and magnetic tapes 309 to 312, which are respectively connected to channel adapters 303 to 306. Each of the channel controller adapters 303 to 306, to which can be connected to a maximum of 16 units by the interface lines of a channel adapter interface (CAI) 300-l, is connected to one of the channel doors 0 to 3. The fast multiplexer 300 is connected to the gate A corresponding to a data interface 600, to a programmable interface 601 and an interrupt interface 602.

With regard to the present invention, each of the channel controller adapters 303 to 306 can be considered as conventional and produced like the controller adapters described in US Pat. No. 3,742,457 mentioned above.

System interfaces

Before describing in detail the processing unit 700 and the cache unit 750, produced according to the present invention, each of the interfaces 600 to 604, mentioned previously, will now be described with reference to FIGS. 5a to 5e.

If we first refer to FIG. 5a, we can see that it represents the lines which constitute the data interface 600 representing one of the interfaces ensuring the exchange of information between an active module and the 'system interface unit 100. The exchanges are carried out by controlling the logical states of the different lines of signals / with respect to pre-established rules applied by a series of signals designated as dialogue.

The interface of FIG. 5a comprises an active exit door request line (AOPR), a set of data lines at SIU (DT5 OO-DIS 35, P0-P3), a set of maneuver data lines at SIU (SDIS 0-6, P), an active accepted request line (ARA), an accepted read data line (ARDA), a set of data lines from the SIÜ bus (DFS 00-35, P0-P3) , a set of SIU multiple door identifier lines (MIPS 0-3, P), a SIU double precision line (DPFS) and an accepted status line (AST). A more detailed description of the interface lines is given in the following section.

Designation Data interface lines

Description

AOPR The active exit door request line is a unidirectional line which extends from each active module to the SIU 100 unit. When set to 1, this line signals to the SIU unit that the module is requesting a route along which commands and data must be transmitted.

DIS 00-35, P0-P3 The data path lines constitute a unidirectional path four bytes wide (4 bytes of 10 bits) which extends between each active module and the SIU and which is used to transfer orders

AFTER

Designation

Data interface lines Description or data of each module active at the SIU 100 unit.

SDTS 0-6, P Maneuver data lines to

SIUs extend from each active module to the SIU 100 unit. These lines. are used to send maneuver control information to the SIU 100 when the AOPR line is set up. The maneuver control information consists of seven bits and one parity bit which are coded as follows:

(a) The status of a bit O indicates the type of command transmitted to the lines

DIS (if it is a programmable interface command or a memory command).

(b) Bits 1-4 are coded to indicate which module should receive and interpret the memory command (commands are interpreted only by memory modules and programmable interface commands will be interpreted by all modules except of the input-output processing unit 200).

(c) The state of a bit 5 indicates whether one or two words of control information should be transferred between the requesting active module and the designated receiving module (one word specifies simple precision transfer and two words specify one. double precision transfer).

<td></td><td>AFTER</td>

<td>Designation</td><td>Data interface lines Description</td>

<td>MHS 0-3, P</td><td>(d) The state of a bit 6 indicates the direction the transfer between the module requestor and the designated receiver module. (e) A P bit is a parity bit generated by the active requesting module which is controlled by a device included in the unit SIU 100. The four identifier lines of multiple doors to SIU * extend from an active module to the SIU 100 unit.</td>

<td>Macaw</td><td>These lines are coded to indicate which sub-channel or door of a module active caused the AOPR line to be set to 1. The active accepted request line extends from SIU 100 to each active modules. This line is</td>

<td>ARDA</td><td>set to 1 to indicate that the module designated receiver has accepted the request of the active module which authorizes the mo · dule active to remove information requested interface lines from data. The line of data read accepted extends from SIU to each of active modules. This line is set àl by SIU 100 unit to indicate to the active module that it must accept previously requested data a designated module.</td>

<td>DFS 00-35, P0-P3</td><td>Another set of data lines is the SIU data lines.</td>

AFTER

Designation Programmable interface lines

Description

<td></td><td>data path constituting a unidirectional path four bytes wide (4 bytes of 10 bits) which extends from the SIU to</td>

<td>MIFS 0-3, P</td><td>each active module. These groups of lines are used by the unit SIU 100 to route so-called read data to one of the designated active modules. The four identifier lines of multiple doors plus a parity line extend from the SIU 100 unit to each of the active modules. These li-</td>

<td>DPFS</td><td>genes are coded to indicate which gate or sub-channel of the active module should accept the resulting data from a previous read operation of the SIU 100 unit. The SIU double precision line extends from the SIU unit to each module active. The status of this line indicates if one or two words of data read</td>

<td>AST</td><td>must be accepted by the active module to complete a transfer (read command). The accepted status line extends from unit 100 to each active module. The state of this line, which excludes the ARDA line, signals to the active module that it must accept the status information sent on the DFS lines.</td>

The lines of the programmable interface 601 shown in FIG. 5b make it possible to transfer control information from an active module and from a designated module. The transfer is carried out by controlling the logic of the states of the different lines of signals with respect to pre-established rules implemented by a series of signals called dialogue ”. The programmable interface comprises a command line of programmable interface accepted (APC ), a set of SZU programmable interface data lines (PDFS 00-35, P0-P3), a ready programmable interface line (PIR), a read data transfer request line (RDTR), a set of programmable interface data lines to SIU (PD1S 00-35, P0-P3 ) and an accepted read data line (RDAA). A more detailed description of the interface lines is given in the following section.

Designation LINES D^y PROGRAMMABLE INTERFACE

Description

APC

PDFS 00-35, PO-P3 »

PIR

PDTS 00-35, P0-P3

The accepted programmable interface command line extends from the SIU 100 to each receiver module. When set to 1, this line signals to the module that command information has been sent to the PDFS lines of the interface by the SIU and must be accepted by the module.

The SIU programmable interface data lines constitute a unidirectional path four bytes wide (four 10-bit bytes) that extends from the SIU 100 to each module. These lines send programmable interface information from the system interface unit to a designated receiver module.

The ready programmable interface line extends from each module to the SIU. When set to 1, this line indicates that the module is ready for. accept an order. to send to a PDFS line.

The SIU programmable interface data lines constitute a unidirectional path four bytes wide (four 10-bit bytes) which extends from each module to the SIU 100. These lines are used to transfer information

AFTER

PROGRAMMABLE INTERFACE LINES

Description

Designation

RDTR

RDAA of programmable interface to the SIU unit.

The request line for data transfer extends from each module connected to the programmable interface to the SIU. When set to 1, this line indicates that the previously requested read data is available for transfer to a module and has been sent over the PDTS lines by the module.

The line of accepted read data extends from the SIU 100 unit to each module. When it is set to 1.1a line indicates to the module that the data sent on the PDTS lines has been accepted and that the module can withdraw the information from these lines.

The interrupt interface 602 is another interface, shown in FIG. 5c, which makes it possible to process interrupts by means of the input-output processing unit 200.

This is how the interface authorizes the transfer of interrupt information by an active module to the SIU 100 unit as well as the transfer of interrupt information by the SIU 100 unit to the processing unit. input-output 200 for processing, As with the other interfaces, the transfer of interrupt requests is carried out by controlling the logical states of the different signal lines with respect to pre-established rules implemented by a series of signals designated as 'dialogue'.

Interface includes an interrupt request (IR) line, a set of interrupt data lines (IDA 00-11, PO-PI) and a set of multiple interrupt door identifier (IMID) lines 00-03) for modules connected to doors A to L. For modules connected to doors G and H, the interrupt interface also comprises a line of level zero present (LZP), a line of higher level of interrupt present (HLIP), a line requesting data from interruption

2425ÎΤΟ (IDR), a release line (RLS) and a set of active interrupt level lines (AIL 0-2). As can be seen in FIG. 5c, the interrupt interface doors G and S do not include an identifier line for multiple interrupt doors. A more detailed description of the interrupt interface lines is given in the following section.

<td>Designation</td><td>INTERRUPTION INTERFACE LINES Description</td>

<td>IR</td><td>Interrupt request line extends of each module to the SIU 100 unit. When it is set to 1, this line indicates to the SIU that the module requests to be served.</td>

<td>IDA 0-3, PO</td><td>The interrupt data lines extend—</td>

<td>IDA 4-11, PI</td><td>tooth of an active module at the SIU 100 unit. These lines are coded to contain control information necessary for a transfer to the input-output processing unit when an interrupt request has been accepted by the processing unit. These bits are coded as follows: a) The state of a bit 0 specifies to the unit SIU 100 which processing unit (i.e., unit number) should process the interrupt request. b) Bits 1-3 are coded to indicate the priority or level number of the request for interruption to the SIU 100 unit. c) A PO bit is a bit parity bit 0-3. d) Bits 4-8 are encoded to provide part of an address necessary to be generated by the I / O processing unit 200 to indicate the correct procedure for handling the interrupt i.e. a common block number · ICBN).</td>

₁₇ 2425110

AFTER

INTERRUPTION INTERFACE LINES

Description

Designation

IMID 00-03

LZP

HLIP

IDR

RLS

AIL 0-2 (e) A Pl bit is a parity bit for bits 4-11.

The multiple interrupt door identifier lines extend from each active module to the SXU 100. These lines are coded to identify which specific subchannel of the active module has requested interrupt support.

The zero level line present extends from the SIU 100 to the I / O processing unit 200. When set to 1, this line indicates that there is a request for higher priority ( interrupt level 0) made to the processing unit 200 by the SIU 100 unit.

The upper level interrupt line present extends from the SIU to the input-output processing unit. When set to 1, this line indicates that there is an interrupt request having a higher level or higher priority than that of the procedure or operation being executed by the processing unit 200 .

The interrupt data request line extends from the I / O processing unit 200 to the SIU 100. When set to 1, this line indicates that interrupt data must be sent to unit 200 on DFS lines by unit SIU 100.

The release line extends from the input-output processing unit 200 to the SIU 100. This line, once set to 1, indicates that the processing unit 200 has completed the execution of the current procedure.

Active interrupt level lines

AFTER

Designation

INTERRUPTION INTERFACE LINES Description extend from the SIU to the input-output processing unit 200. These lines are coded to denote the interrupt level number of the procedure being executed. by the processing unit 200.

Another set of interface lines used by some of the modules in FIG. 1 corresponds to the local memory interface lines in FIG. 5d. The local memory interface 603 makes it possible to exchange information between the local memory gOO and the modules of the system. The exchange is carried out by controlling the logical states of the various signal interface lines with respect to pre-established rules applied by a series of signals designated as dialogue. The local memory interface includes a set of memory data lines (DTM 00-35, P0-P3), a set of memory request identifier lines (RITM 0-7, P0-Pl), a set of specification lines, in memory (SLTM 0-3, P), an accepted P1 command line (APC), an accepted ZAC command line (AZC), a PI ready interface line (PIR), a ready ZAC interface line (ZIR), a read data transfer request line (RDTR), a set of memory data lines (DEM 00-35, P0-P3), a set of memory request identifier lines (RIFM 0-7 , P0-Pl), double precision memory lines (DPFM), a QUAD line, an accepted read data line (RDAA) and a system clock line (SYS-CLK).

Memory and programmable interface commands are transferred outside the same data lines of the interface. The interface does not include a set of lines to process interruption requests; therefore the modules connected to the local memory by the SIU 100 unit cannot directly cause a memory interruption. local memory interface is made in more detail in the following.

LOCAL MEMORY INTERFACE LINES

Description

Designation

DTM 00-35, P0-P3

RITM 0-3, PO RITM 4-7, Pl

SLTM 0-3, P

The data path lines constitute a unidirectional path four mulets wide (36 lines of information and four lines of parity) which extends from the SIU 100 to the local memory 500.

These lines are used to transfer memory interface or programmable interface commands to local memory 500.

The memory requester identifier lines constitute two groups of four lines which extend from the unit 100 to the local memory 500. These lines are coded to convey information to the local memory identifying the module which launched the command and are used to return the requested data to the appropriate module.

Memory specification lines extend from SIU 100 to local memory 500 and include two door number selection lines, one line of

F read / write in memory, a double precision line in memory and a parity line. The information signals sent on these lines are coded as follows.

a) Bits 0-1 are coded door number selection bits to specify which door or sub-channel of the connected module should receive or interpret the memory command sent to the module.

b) A bit 2 is a read / write bit in memory included in the maneuver control information received from the active module which is transmitted by the §IU unit.

<td></td><td>AFTER</td>

<td>Designation</td><td>MEMORY INTERFACE LINES LOCAL Description</td>

<td>AZC</td><td>to local memory 500 when a new command is sent to memory by SIU 100. The status of this bit indicates the meaning of a data transfer. (c) A bit 3 is a double precision bit of memory coded to specify the amount of data to transfer. It is also included in the information for maneuver command provided by the active module which are transmitted to the module of local memory 500 by the SIU 100 when a new command is sent to the memory module * Accepted ZAC command line expands from the SIU 100 unit to the memory module</td>

<td>APC</td><td>locale 500. When set to 1, this line signals to the local memory module 500 that it must accept the ZAC command and the command information sent on the other lines by the SIU 100 unit. Setting this interface line to ONE excludes the PI control interface line accepted. The accepted programmable interface command line, as described for the programmable interface, ranges from SIU 100 to modular local memory 500. When it is set to 1 this line indicates that the control information sent on the DTM lines must be accepted by the module local memory 500.</td>

<td></td><td>AFTER</td>

<td>Designation</td><td>LOCAL MEMORY INTERFACE LINES Description</td>

<td>PIR / ZIR</td><td>The ready programmable interface line / ready ZAC interface line extends from the local memory module 500 to the SIU 100 unit. When set to 1, each line signals the SIU 100 that the memory module locale 500 is able to accept a programmable interface (PI) / memory (ZAC) command.</td>

<td>RDTR</td><td>The data transfer request line read extends from local memory module 500 to the SIU 100 unit. This line, once set to indicates that the data called read, previously requested by a ZAC or PI command, are available at the same time as the order information needed to send to the module requesting the data.</td>

<td>DFM 00-35, P0-P3</td><td>The data lines of the memory form a unidirectional bus of four bytes wide that extends from the memory module local 500 to SIU 100. These lines are used to return requested data called read to an active module via the SIU 100 unit.</td>

<td>RIFM, 0-3, PO RIFM 4-7, PI</td><td>The two groups of identifier lines memory requestor extend from local memory module 500 to SIU 100. These lines are coded to return the data read from module 500 to requesting module.</td>

<td>DPFM and QUAD</td><td>Double precision memory line and QUAD line extend from memory module local 500 to SIU 100. These lines are coded to indicate the number of words to be transferred through the unit SIU 100 to the requesting module during the transfer request time interval</td>

AFTER

Designation

LOCAL MEMORY INTERFACE LINES Description of data read. These lines are coded as follows =:

QUAD DPFM

OO a word, simple precision

O 1 two words, double preci_χ sion (whatever it is) four words The line of data read / status identifier extends from the local memory module 500 to the SIU 100 unit. The state of this line signals to the SIU unit if the information sent on the DFM lines is read data or state information when the RDTR line is set to 1. When it is set to 1.1 the line indicates that one or two word status information (QUAD = O) are being transferred. When set to binary ZERO, the line signals that at most four data words are being transferred, the number being specified by the coding of the QUAD and DPFM lines.

RDAA The line of data read accepted as mentioned in connection with the programmable interface extends from the SIU 100 unit to the local memory module. When it is set to 1, this line signals to the memory module that the data sent on the interface lines by the module, from local memory have been accepted and that the local memory module can remove the data from these lines.

The system clock line is a line that extends from the SIU 100 to each module in the system. This line is

SYS-CLK

AFTER

Designation

LOCAL MEMORY INTERFACE LINES Description connected to a clock source contained in the input-output processing unit 200 to synchronize the operations of each memory module from a clock source of the common system.

A final set of interface lines used as the internal interface between the cache unit 750 and the central processing unit 700 correspond to the cache / CPU interface lines of Figure 5e. The interface 604 allows information and control to be exchanged between the processing unit 700 and the cache unit 750. The exchange is carried out by controlling the logic states of the various signal interface lines. The cache / CPU interface includes a set of data lines to the processing unit (ZDÏ O-35, PO-P3), a set of lines of ZAD and written data (ZADO 0-23, RADO 24-35 , POPS), a processing unit request signal line (DREQ-CAC), a set of cache control lines (DMEM 0-3;), a maintained cache line (HOLD-C-CU ), a reset line (CANCEL-C), a presentation line (CAC-FLUSH), a read request line (RD-EVEN), a read instruction buffer line (RD-IBUF), a read data buffer line (DRDB), an initialization flag line (INITIBUF), a set of instruction lines (ZIBO-35 ), a set of address pointer lines (ASFA-M32-33), a command line (DSZ), a read-buffer data instruction line (RD-IBUF / ZDI), a set of area bit lines (DZD 00-33), a skipped cache line (ΒΥΡ-CAC), a write signal line (WRT-SGN), an empty instruction buffer line (IBUF-EMPTY), a ready instruction buffer line (IBUF- RDY) a full instruction buffer line (IBUF-FULL), a CP stop line (CP-STOP), and a CP command line (DATARECOV).

Instructions, cache commands, and data are transmitted to cache unit 750 through some of these lines. In addition, the operation of the central unit 700 is validated or invalidated by some of these lines as will be explained below. The description of the CP / cache interface lines is given in more detail below.

Designation

CP / ANTEMEMORY INTERFACE LINES Description

DREQ-CAC This line extends from the central unit

700 to cache memory 750. When the line is set to ONE binary, a ZAC command is transferred to cache 750. In the case of a ZAC write command, write data words are transferred during the one or two cycles following the ZAC command and the data words are sent from the central unit 700 to the SIU unit 100 via the cache memory 750 without modification.

DMEM 0, 1, 2, 3 These lines extend from the central unit

700 to cache 750. These lines are coded to designate the command that cache 750 should execute. The coding is as follows:

DMEM = O000 no operation. No intervention made and no cache request generated.

DMEM = OOQ1 Direct. The direct command validates the central unit 700 to carry out a direct transfer of an operand value without intervention on the part of the cache memory 750. No request for cache memory is therefore generated by this type of command.

DMEM = 0010 0-3- Return command on same address (ADD-WRAP). The return to the same address command is executed in 2 cycles. At the start of the first cycle, data and control information is transferred to

AFTER

Designation ÇP / ANTEMEMORY INTERFACE LINES

Description cache 750. The central processing unit 700 is then switched off before the next clock interval. During the second cycle, the central unit is switched on and_z at the end of the cycle_zthe data intended for it become available for the central unit 700.

DMEM = O1OO 0-3- Loading of instruction-Extraction instruction buffer 1 (LD-IBUF-IF1). The instruction buffer load command is executed in one cycle. At the start of the cycle, address and control information is transferred to cache 750 '. At the end of the cycle, the block specified by the address is written in the instruction buffer to a previously designated instruction buffer address, and the word addressed is transferred to the central processing unit 700 via the lines ZDI 0-35.

DMEM = 0101 0-3-Load of instruction buffer-Instruction extraction 2 (LD-IBUF-IF2). The instruction buffer load command is executed in one cycle. At the start of the cycle, address and control information is transferred to cache 750. At the end of the cycle, the block specified by the address is written to the instruction buffer at the buffer address. previously designated instruction.

DMEM = 0110-QUAD loading

The loading of QUAD is executed in one cycle. As for IF2_ybut the data is stored in another part of the buffer

AFTER

Designation

CP / ANTEMEMORY INTERFACE LINES Instruction description.

DMEM-OI11 0-3, Pre-reading (PR-RD). The pre-reading command is executed in a variable number of cycles at least equal to one. At the start of the first cycle, address and control information is transferred to cache 750. During the first cycle, when the specified address is that of a block that is in cache 750, the operation of pre-reading ends and no further action is taken. If the addressed block is not in cache 750, at the end of the cycle, the request is then transferred to the main memory. When the requested block has been read from main memory, the data is stored in cache 750.

DMEM = 10QQ 0-3 Simple reading (RD-SNG)

The simple read command is executed at the start of the cycle in one cycle. J The address and command information is transmitted to cache 750 ety at the end of the cycle,? The data becomes available for the central unit

700.

DMEM = 1001 0-3-Read-Reset (RD-CLR)

The read-reset command is executed in a variable number of cycles at least equal to 9. At the start of the first cycle, the address and command information are transferred to the main memory, and the central unit is shutdown. During the second cycle, when the word addressed is contained in a cache block, the block containing the word is extracted from cache 750. When

AFTER

Designation CP / ANTEMEMORY INTERFACE LINES

Description the requested word has been read from main memory 5 and transferred to cache memory '750, the central unit is then switched on.

DMEM = 1O1O 0-3- Double-odd reading 10 (RD-DBL-0) (DSZ line is at binary ZERO). The double odd reading command is executed in two cycles. At the start of the first cycle, the address and order information is transferred to. cache 750. At the end of the first cyclfe, the word at the odd address becomes available for the central unit 700. At the end of the second cycle, the word at the even address *₂Q becomes available for the central unit

700.

DMEM = 1010 0-3- Double-Pair reading (RD-DBL-E) (the DSZ line is ONE binary). The double-pair read command is executed in two cycles. At the start of the first cycle, the address and control information is transferred to the cache memory 750. At the end of the first cycle, the word at the even address becomes available for the central unit 700. At the end of the second cycle, the word at the odd address becomes available for the central unit 700.

DMEM = 1011 0-3- Remote reading (RD-RMT) 35 The remote reading command is executed in a variable number of cycles, at least equal to 10. At the start of the first cycle, the address and command are transferred to the cache

AFTER

Designation ήθ (25

CP / ANTEMEMOISE INTERFACE LINES Description

750. At the end of the first cycle, the request is transferred to the main memory and the central unit 700 is switched off. When the two requested words have been extracted from the memory, the central unit 700 is switched on and the data is then available for the latter.

DMEM = 1100 0-3- Simple writing (WRT-SNG)

The simple write command is executed in two cycles. At the start of the first cycle, the address and control information is transferred to the cache 750. At the start of the second cycle, the data is transferred to the cache 750. During the second cycle, the data is written to cache 750, if the block containing the word addressed is stored in cache 750. At the end of the second cycle, the write request and the data are transferred to the main memory.

DMEMd-110 0-3- Double writing (WRT-DBL)

The double write command is executed in three cycles. At the start of the first cycle, address and control information is transferred to cache 750. At the start of the second cycle (third), the even (odd) data word is transferred to cache 750. During the third cycle, the data is written to the cache memory, if the block containing the two addressed words is stored in the cache memory 750. At the end of the third cycle, the write request and the two data words can then pass into main memory.

Designation

HOLD-C-Cü

2θ CANCEL-C

CAC-FLUSH

RD-EVEN

ZADO 0-23 RADO 24-35 P0-P3

AFTER

CP / ANTEMEMORY INTERFACE LINES Description

DMEM: T111 0-3- Remote writing (WRT-RMT)

The remote write command is executed in three cycles. At the start of the first cycle, address and control information is transferred to cache 750.

At the end of the first cycle, the request is transferred to the main memory. During the next two cycles, the two data words are transferred to cache 750 which likewise transfers to main memory This line extends from central unit 700 to cache 750. When it is set to ONE binary , this command signal line specifies that cache 750 should take a HOLD state for requests or data transfers.

This line extends from CPU 700 to cache 750. When set to ONE binary, this control signal line stops any request made to cache 750.

This line extends from the central processing unit 700 to the cache memory 750. When it is set to binary ONE, it launches a preparation of the cache memory 750.

This line extends from the central unit 700. to cache 750. When the cache request for a double word is made to the SIU, the even word is kept in a special register. When the RD-EVEN line is set to ONE binary, the content of this register is transferred by gates to the ZDI lines.

These 40 unidirectional lines extend from the central processing unit 700 to the cache memory 750. The lines are used to transfer a ZAC command and write data words to the cache memory 750.

3Q

AFTER

Designation:

RD-IBUF

DZD 0-3

BYP-CAC

WRT-3GN

ASFA 32-33

INIT-IBUF

242S1U

LINES D^T CP / ANTEHEMOIRE INTERFACE Description

This line runs from CPU 700 to cache 750. When binary ONE, the line advances an instruction buffer output pointer to process a next instruction depending on the state of a DRDB line as shown below.

These four lines extend from the central processing unit 700 to the cache memory 750. These lines transfer bit signals from.

odd word area for double write commands.

This line extends from the central processing unit 700 to the cache memory 750. When it is set to binary ONE, this line causes a request by the cache memory 750 for data words coming from the main memory for reading instructions. .

This line extends from cache 750 to central unit 700 and is used to signal to central unit 700 during write commands that cache 750 has completed the transfer of ZAC commands and words from SIU 100 unit data.

These two lines extend from the central processing unit 700 to the cache memory 750. These lines are coded to specify the next word of a block stored in the instruction buffer I to be read by the central processing unit 700 when the buffer I is initialized under hardware order via the INIT IBUF line.

The command to initialize the instruction buffer is executed in one cycle. At the end of the cycle, a buffer entry pointer is reset to ZERO and the

AFTER

<td>Designation</td><td>CP / ANTEMEMOIRE INTERFACE LINES Description</td>

<td>DSZ1</td><td>buffer output is loaded with an initial value. This line extends from central unit 700 to cache 750. The state of this line specifies in cache 750 the order in the-</td>

<td>DRDB100</td><td>which words should be sent to the central unit 700 when a read command double is made. This line extends from the central unit 700</td>

<td>RD-IBUF / ZDI</td><td>to cache 750. It is used as corresponding to the most significant bit of the address instruction buffer reading I, This line extends from the central unit 700</td>

<td>ZDI 0-35</td><td>to cache 750. Through this line, cache 750 sends data to the ZDI lines through the ZIB lines. These 40 unidirectional lines extend from</td>

<td>^P0’ ^Pthe ^P2’ ^P3</td><td>cache 750 to the central unit 700. These lines send data from the cache memory.</td>

<td>ZIB 0-35</td><td>re to central unit 700. These 40 unidirectional lines extend</td>

<td>PP PP 0 '* 1' 2 '3</td><td>from cache 750 to CPU 700. These lines send buffer instructions cache instruction to the CPU</td>

<td>I BUF-EMPTY</td><td>700. This line extends from cache 750 to central unit 700. When set to ONE Binary, this line indicates that the instruction buffer does not contain an instruction</td>

<td>I BUF-RDY</td><td>at that time ~ there. This line extends from cache 750 to the central processing unit 700. When set to ONE binary, the line indicates that the instruction buffer contains at least one instruction.</td>

AFTER

<td>Designation</td><td>CP / ANTEMEMORY INTERFACE LINES Description</td>

<td>I BUF FÜLL</td><td>This line runs from cache 750 to CPU 700. This line indicates that the instruction buffer contains more than four instructions or that he has at minus one instruction and one request line</td>

<td>CP STOP</td><td>• pending instruction extraction. This line extends from cache 750 to the 700 central processing unit.</td>

<td>DATA-RECOV</td><td>set to ONE binary, the line indicates that, in consequence of special conditions detected inside the cache unit 750, the central unit 700 is forced to wait or stop its operation while cache 750 resolves special conditions. This line extends from cache 750 to the 700 central unit. It is used to resample registers of the central unit following the shutdown of the central unit 700 in response to the detection of a condition of lack of cache memory.</td>

While FIGS. 5a to 5e represent lines which connect the different modules of the system of FIG. 1 to the SIU unit 100, in addition to the connection to the central unit 700 and the cache memory 750, it will be noted that d other lines are also included to indicate other conditions, such as certain error conditions and operating conditions. For more details on the various modules of FIG. 1, reference may be made to United States patent No. 4,000,487. A more detailed description of the central processing unit 700 and the cache unit 750 will now be made.

General description of the central processing unit or processor 700 - Fig. 2

Referring to FIG. 2, it can be seen that the central unit 700 comprises an execution control unit 701, a control unit 704, an execution unit 714, a character unit 720, an arithmetic unit and auxiliary control unit (AACU) 722, a multiplication-division unit 728, which are interconnected as shown. In addition, the control unit 704 has several connections which connect it to the cache unit 750, as shown in FIG. 2.

The execution control unit 701 comprises an execution control memory preparation and connection unit 701-1 and an execution control memory 701-2.

Memory 701-2 and unit 701-1 are interconnected via buses 701-3 and 701-6 as shown.

The control unit 704 comprises a logic control unit 704-1, a control memory 704-2, an address preparation unit 704-3, data and address output circuits 704-4, a block of registers XAQ-704-5 which are interconnected as shown.

As shown in Figure 2, the SIU 600 interface provides multiple input lines to the cache unit 750. The lines of this interface have been described in detail above. However, some of these lines affected by the operation of the cache unit 750, are coded as follows:

1. MITS 0-3 for readings are coded as follows: bits 0-1 = 00;

bits 2-3 = ZAC buffer address read;

For a Write Operation, bit 0-3 = Odd word area.

2. MIFS lines are coded as follows: bit 0 = 0;

bit 1 = 0, pairs of even words (words 0.1); bit 1 = 1, odd word pairs (words 2,3); bits 2-3 = ZAC buffer address to memory.

Regarding the DES GO-35 interface lines,

P0-P3 these route read data to the cache unit 750. DTS lines 00-35, P0-P3 are used to transfer data from cache 750 to the SIU 100 unit.

In addition, the SIU 602 interface provides multiple input lines to the cache unit 750 which routes information in the form of PI commands. These commands are transmitted by the cache memory unit 750 to a group of logic control circuits via a set of internal interface lines, some of which are shown in FIG. 4. These circuits can be considered comparable to the circuits described in United States Patent No. 4,006,466 and United States Patent No. 4,017,836. The logic control circuits in turn transmit control signals for commands via decoder lines ZPI33 9-16 by the cache block 750-100 to read and write to the cache registers and memory, as will be explained later. The circuits also transmit address signals to block 750-100 via the ZPIDT lines

28-35. The use of the above lines will be explained in more detail with reference to Figure 4.

The control unit 704 provides the control necessary for carrying out address preparation operations, operations for extracting / executing instructions as well as the sequential control of the various operating cycles and / or of the machine states. The control is established by the logic circuits of the block 704-1 and by the execution control unit 701 for the different parts of the control unit 704.

The TAQ 704-5 register set includes a number of visible program registers such as index registers, an accumulator register and a quotient register, “This set will be described in detail below. in Figure 3. Other visible program registers such as the instruction counter and address registers are included in the address preparation unit 704-3.

As shown in FIG. 2, the assembly 704-5 receives from the unit 704-3 signals representing the contents of the instruction counter via the lines RIC 00-17. Also, the lines ZRESA 00-35 transmit output signals from the execution unit 714 in correspondence with the results of operations carried out on different operands. The 704-5 set also receives an output signal from the arithmetic and auxiliary control unit via the RAAUO-8 lines.

The assembly 704-5 provides signals representing the content of one of the registers of the assembly in the form of input signals applied to the address preparation unit 704-3. This address preparation unit 704-3 transmits the information via a switch to the execution unit 714 using the lines ZEB 00-35. Likewise, the contents of some of the registers of the set 704-5 can be transferred to the execution unit 714 using the lines ZEB 00-35. Finally, the contents of selected registers of said set 704-5 can be transmitted to the multiplication / division unit 728 via the lines ZAQ 00-35.

The address preparation unit 704-3 generates addresses from the content of the various registers thereof and transmits the resulting logical, real and / or absolute addresses for the

2425119 distribute in other units by lines ASFA 00-35.

The address preparation unit 704-3 receives the results of the operations carried out on two operands by the execution unit 714 via the lines ZRESB 00-35. The unit 704-3 receives signals representing the contents of two basic pointer registers from the logic control unit 701 via the lines RBASÀ and RBASBO-1. Output signals from the multiplication / division unit 728 are applied to the address preparation unit 704-3. Finally, the content of a secondary instruction register (RSIR) is applied to the input of unit 704-13 via RSIR lines 00-35.

The data and address output circuits 704-4 produce the cache address signals which are transmitted to the cache 750 via the RADO / ZADO 00-35 lines.

These address signals correspond to the signals applied to one of the groups of input lines ZDI 00-35, AFSA 00-35 and ZREBS 00-35, selected by switches intervening in the circuits of block 704-4. Also, word address signals are applied via ASFA lines 32-33. These circuits will be described in more detail below.

The logic control unit 704-1 establishes data paths which have an interface with different units intervening in the cache memory 750. As will be specified below, the lines ZIB 00-35 establish an interface with a buffer of instructions incorporated in cache 750. The lines ZDI 00-35 are used to transfer data signals from cache 750 to the logic control unit 704-1. Other signals are applied through other data and control lines of the cache-CP interface 604. These lines include the CP stop line shown separately in Figure 2.

As shown in Figure 2, the control logic unit 704-1 provides a number of groups of output signals. These output signals contain the contents of certain registers, such as for example a basic instruction register (RBIR), the contents of which are applied to the input of the control memory 704-2 via the lines RBIR 18- 27. The control memory

704-2 receives certain control signals extracted from the control memory 704-2 via the CCSDO lines 13-31.

The logic control unit 704-1 also contains a secondary instruction register (RSIR) which is loaded in parallel with the basic instruction register at the start of the processing of an instruction. The content of the secondary instruction register RSIR 00-35, as indicated above, is applied to the inputs of the address preparation unit 704-3. In addition, part of the content of the secondary instruction register is applied to the inputs of the arithmetic and auxiliary control unit 722 via RSIR lines 1-9 and 24-35.

As indicated above, the control memory 704-2 provides an initial decoding of the operating instructions of the program and is therefore arranged so as to include a certain number of memory locations (1024) which correspond each has a possible instruction operation code.

Signals transmitted by RBIR lines 18-27 are applied to the inputs of the control memory 704-2. These signals select one of 1024 possible memory locations. The contents of the selected memory location are transmitted by lines CCSDO 13-31 and CCSDO 00-12, as shown in Figure 2. The signals applied to lines CCSDO 00-12 correspond to address signals which are used to address the execution control unit 701.

The other parts of the central processing unit 700 will now be briefly described. The execution unit 714 ensures execution of instructions by performing arithmetic and / or shift operations on operands selected from the various inputs. The results of these operations are transmitted to selected outputs. The execution unit 714 receives data from an input bus which corresponds to the RDI lines 00-35 and which are produced by the logic control unit 704-1. The contents of the accumulator and quotient registers occurring in the set 704-5 are applied to the execution unit 714 via the lines ZEB 00-35, as mentioned previously. The signals transmitted to the input bus lines ZDO 00-35 from the address preparation unit 704-3 are transmitted, via switches intervening in ₃₈ 242S110 execution unit 714, in the form of output signals to lines ZRESA 00-35 and ZRESB 00-35, as shown in Figure 2.

In addition, the execution unit receives a group of memory-interpreter address signals from the arithmetic and auxiliary control unit 722 and transmitted via lines ZRSPA 00-06. In addition, unit 722 provides offset information to unit 714 via lines ZRSG 0005.

The character unit 720 is used to execute character-type instructions which require operations such as translation and preparation of data fields. As will be explained below, these types of instructions relate to instructions of the extended instruction group type (EIS). The instructions executed by the character unit 720 include instructions of the transfer, analysis and comparison type. Signals representing operands are transmitted via lines ZREA 00-35. Information regarding the type of character position in a word and the number of bits is applied to character unit 720 via lines d 'entry ZPB 00-07.

Information representing the results of certain data operations is applied to the unit 722 via the lines ZOC 00-08. This information contains exponent data and data in hexadecimal form. The character unit 720 transmits operand data and control information appearing at its output to the unit 722 and to the unit 728 via the lines RCHU 00-35.

The arithmetic and auxiliary control unit 722 performs arithmetic operations on control information such as exponents used in floating point operations, calculates lengths of operands and pointers, and establishes account information. The results of these operations are transmitted to the execution unit 714 via the lines ZRSPA 00-06 and the lines ZRSC 00-06 as mentioned above. Information signals corresponding to characters such as 9-bit characters, 6-bit characters, decimal data converted from input hexadecimal data, quotient information and sign information are transmitted to the set 704-5 via the lines RAAU 00-08.

As shown in Figure 2, unit 722 receives a number of input signals. Character pointer information is applied via ASFA lines 33-36.

EIS digital scaling factor information and alphanumeric area length information is transmitted to unit 722 via RSIR lines 24-35. Other signals relating to the extraction of specific instructions are applied via the lines RSIR 01-09. Exponent signals for floating point data are transmitted to unit 722 via lines ZOC 00-08, while floating point definition exponent data signals from unit 704- 1, are transmitted via lines RDI 00-08. Account shift information signals occurring in certain instructions (eg, binary shift instructions) are applied to the unit via RDI lines 11-17. For input signals applied to lines RCHU 00-35, lines 24-35 apply signals corresponding to the length of the EIS instruction zones while lines 18-23 apply address change signals to unit 722.

The last unit consists of the multiplication / division unit 728 which ensures rapid execution of multiplication and division instructions. This unit can be considered as of a conventional design and it can be in the form of the multiplication unit described in US Patent No. 4,041,292 issued to the applicant. Unit 728 highlighted in Figure 2 receives input from multiplier, dividend and divider through lines RCHU 00-35. Multicand input signals from register set 704-5 are applied through lines ZAQ 00-35. The results of the calculations performed by unit 728 are transmitted by lines ZMD 00-35.

As previously mentioned, cache 750 exchanges control signals and data with SIU 100 through the data interface line 600. Cache

750 exchange of control signals and data with the central processing unit 700 via the interface lines 604. Finally, the cache memory 750 receives address and data signals from the circuits 704-4 by via the RADO / ZADO 00-35 lines and the ASEA 32-33 lines.

Detailed description of the central processing unit 700

We will now describe the different parts involved in the central processing unit 700 shown in Figure 2 with reference to Figures 3a_ to 3_

With reference to FIGS. 3a and 3b, it can be seen that the central processing unit comprises two control memories: (1) the control unit control memory (CCS) 704-200 which is part of the control unit 704; and (2) the execution control memory (ECS) 701-3 which is part of the execution control unit 701.

The central processing unit with cache 700 corresponding to the preferred embodiment of the present invention comprises a three-phase pipeline. This means that the processing unit 700 requires at least three cycles to complete the processing of a given instruction of a program and can issue a new instruction at the start of each cycle. As a result, a number of program instructions may be in a certain processing phase at a given time.

In the preferred embodiment of the central processing unit 700, the following phases are provided: an instruction cycle (I) in which an instruction interpretation is carried out, an operation code decoding and a preparation address; a cache cycle (C) in which access to the cache 750 is established in order to obtain high operating efficiency; and, an execution cycle (E) in which an instruction execution is carried out under the microprogrammed command.

With regard to the command during cycle I, the instruction operation code applied via the lines RBIR 18-27 is used to access a location in the command memory 704-2. During a cycle C, the contents which have been accessed in the control memory 704-2 are transmitted by the lines CCS DO 00-12 and they are in turn used to access one of the memory locations of the control memory d 'execution 701-2. During cycle C, the microinstructions of the firmware used to execute the instruction are extracted from the execution control memory 701-2 in order to be transferred to a 144-bit output register 701-4. The signals designated by MEMDO 00-143 are distributed in the different functional units of processor 700. During a cycle E, the processor performs the operation specified by the microinstructions.

Referring more particularly to FIG. 2, it can be seen that the control memory 704-2 comprises a control unit control memory (CCS) 704-200 which is addressed by the operation code signals applied to the RBIR lines. 18-27. The memory 704-200, as mentioned previously, contains 1024 memory locations the contents of which are transferred to an output register 704-202 during a cycle I. FIG. 6a. schematically shows the configuration of the words stored in the control memory 704-200.

In FIG. 6a., It can be seen that each word of the control unit control memory contains five zones. The first zone is a 13-bit zone which contains a location for a DHW start address for the instruction containing a operation code which is applied to RBIR lines 18-27. The next area is a three-bit area (CCS0) which controls certain operations. The interpretations of the bits of this zone · depend on its destination and on whether it is decoded by specific logic circuits or else decoded under microprogrammed command. The next area is a four-bit area that provides certain register control operations.

The next area is a 6-bit sequence control area which is coded to specify a sequence of operations to be performed under the control of hardware logic circuits as well as the type of cache operation. In the example considered, this zone is coded in the form 75g. The last area is a 6-bit flag area which is not relevant to the understanding of the present invention.

As shown in Figure 3 a., Signals corresponding to the CCSA area of ​​a word in the control unit control memory are applied via a path 704-204 to the input of the circuits. generation of execution 701-7. Signals corresponding to the CCSR area are applied to the input of the execution unit 714 via the path 704-206. In addition, the same signals are applied to the input of the address preparation unit 704-3 via another path 704208.

Signals representing the sequence control area are applied to the logic sequence control circuits 704-100 through the path 704-210. These circuits decode the sequence control area and generate signals used to condition the cache memory 750 for the execution of the defined operation.

As mentioned previously, the execution address generation circuit 701-1 receives an input address which corresponds to the CCSA zone coming from the control memory 704-2. As shown in Figure 3b, these circuits contain an input address register 701-10, the output of which is connected to a position of a four-position switch 701-12, designated by ZECSA. The output of the switch serves as the address source for the control memory 701-2. The first position of switch 701-12 is connected so as to receive an address from the MICA register 701-14. The content of register 701-14 is updated at the end of each cycle with a view to pointing to the location of the ECS control memory which follows the location whose content has been read during this cycle.

The second position of the switch selects the address produced by the connection address selector switch ZCSBRA 701-18. The third position selects the address of the first microinstruction in each firmware supplied by the CCS control memory and which is loaded into the REXA 701-10 register. When CCS output is not available at the end of a firmware, a predetermined address (octal address 14) is automatically selected.

The first position of the branch switch 701-18 receives signals corresponding to a branch address extracted from the memory 701-2 and transferred to the register 701-4 with a view to its routing to a return command register 701- 20. The second, third and fourth positions of switch 701-18 receive signals from the register

RSCR 701-20, a MIC register 701-15 as well as the contents of a number of branch vector registers 701-36. The MIC register 701-15 stores an address which is pointed to the microinstruction word following the microinstruction word being executed. This address corresponds to an address from switch 701-12 and increased by one by a circuit 701-12.

The branch vector registers include a 4-bit branch vector register 0 (RVBO), a 2-bit branch vector register 1 (RGB1) and a 2-bit vector branch register 2 (RGB2). These registers are loaded during a cycle of address values ​​derived from signals stored in a number of flip-flops and indication registers and transmitted to inputs of a number of groups of selector multiplexer input circuits 701-32 and 701-34.

The output signals from circuits 701-32 and 701-34 are applied to the inputs of two position selection circuits 701-30.

These circuits in turn produce the ZVBRO output signals,

ZVBRI and ZVBR2 which are stored in registers 701-36.

Switch 701-36 provides an address based on the control of various indicator signals from the hardware, namely, flip-flop status signals selected through an INDGRP area. The connection decision is determined by masking (AND combination) of the selected indicator defined by the INDMSKU and INDMSKL zones with a microinstruction word. If a branch vector is selected, the INDMSKU area is treated as 4 bits at ZERO. The OR combination of the 8 bits is compared to the state defined by the microins areas - &lt;

TYPG and GO truction. The signals emitted by the hardware are applied via a number of data selector circuits 701-28, only one of which is visible in the figures and whose output signals are in turn applied to the inputs of a other five position selector-multiplexer circuit 701-26. The output of the multiplexer circuit 701-26 supplies a combination circuit which combines, according to the logic function AND, the indication signals with the masking signals in order to produce the resulting signals MSKCRBO-7.

The signals MSKCBRO-7 are applied to another comparison circuit which combines, according to the logic function AND, the signals with the conditional branch control signals TYPGGO in order to set to 1 or to reset a branch decision flip-flop 701- 22 which produces an RBDGO signal the state of which indicates whether a connection should be made. The RBDGO output signal is applied as a control signal to the first two positions of switch 701-12. When the connection control condition is not satisfied (that is to say when the signal RBDGO - 0), the address increased by one unit and coming from the MICA register 701-14 is then selected.

In some cases, as will be explained below, it is not possible to check the status of an indicator during the cycle following its formation. For this reason, HRO HR7 historical registers, not shown, are provided for memorizing Group 2 Indicators in the register. The states of these memorized indicators are selected and memorized in a manner similar to other indicators (for example example of masking areas).

In addition, the unit 701-1 contains a number of indicator circuits, some of which are used to control certain parts of the processor 700 when the information strings being processed by certain types of instructions have been exhausted. These indicator circuits are included in block 70142 and are set to one and reset to zero under the control of a zone located in the microinstruction word of FIG. 6a. (i.e. the IND6 area). The bits in this area which have been extracted from the ECS output register 701-4 are applied to an RMI register 701-38 for decoding by a decoder 701-40. Depending on the state of the indication signals state received from the various processor units (for example 714, 720, 7 22, etc.) of the auxiliary flip-flops are switched to the binary state UN. The output signals of these flip-flops are transmitted via the various positions of a four-position switch 701-44 to position GP 3 of the switch 701-26 for control. The same output signals are applied to a second position of a ZIR 701-43 switch for storage via the ZDO 704-340 switch. The switch &lt;3'un

ZIR 701-43 also receives indication signals from indicator register (IR) 701-41. This register is loaded via RDI lines 18-30 and 32 in response to certain instructions.

The indicator status signals contain, for example, the output signals of the various adding circuits (AL, AXP) of the unit 720. These signals set a different flip-flop for indicating the end or exhaustion of a group comprising the FEU, FE12, FE13, FE1E, FE2E, FE2 and FE3 flip-flops. The flip-flops FE1E and FE2E are set to one during an FPOA cycle of any instruction. These flip-flops in turn ensure the setting of one of the flip-flops FEU, FE12 and FE 13 under the impulse of the output signals from the adder circuits AL or AXP of the unit 720. The setting to one and the resetting of these indicators will be described in more detail below in the description of the operation of the system. However, the end indication flip-flops relating to the given example are set to one and reset to zero according to the following Boolean expressions:

RESET ZERO RESET RESET

RESET RESET

RESET RESET RESET

RESET RESET: FE1E = fPOA + INDSFLD zone.

: FE1C = IND6FLD zone.

: FE2E = f EOA + INDSFLD zone.

: FE2E = INDSFLD zone.

: FIRE = IND6FLD zone. FE1E (ALES + AXPES +

DESC1 .AP0-4 = 0) + zone IND6FLD.FE1E.DESÇ1. (AP0-5 = 0 + APZN +

ALZN) + INDSFLD zone .: FIRE = FPOA + IND6FLD zone.

: FE12 = IND6FLD zone. FE1E. (ALES + AXPES +

FE13).

: FE12 = FPOA + IND6FLD zone.

: FE13 = zone INDSFLD.FE1E.ALES + _zone INDSFLD.

: FE13 = ffOA + INDSFLD zone.

: FE2 = INDSFLD.FE2E.ALES zone + IND6FLD zone.

FE2E. DESC2. (AP0-4 = 0 +. AP0-5 = 0 + AZPN +

ALZN) + (IND6FLD zone) FE2E.DESC2 + IND6FLD.

: FE2 = FPOA + INDSFLD zone.

: FE3 = zone IND6FLD.DESC3. (AP0-4O + AP0-5 = 0 + AZPN + ALZN) + zone IND6FLD.DESC3 + IND6FLD.

1425110

RESET: EE3 = OA + IND6ELD area.

Expressions in which IND6FLD indicates a particular code;

ALES = AL = O or ÂL ^ C:

AXPES = AXP = O or AXP-C;

APZN = APO-7 4 °; and,

ALZN = ALO-11 &lt;O.

The ZCSBRA 701-78 switch is normally enabled when the RBD branch decision toggle has been set to 1 in the previous cycle. The first position selects a 13-bit branch address that is part of the microinstruction in progress and applied via the register RSCR 701-20. The connection address authorizes direct addressing of one of the locations in the DHW control memory. The second position selects the sequence of the 6 least significant address bits from the current microinstruction and applied via the MIC 701-15 register and the 7 most significant bits of the connection address from the microinstruction in progress and applied via the register RSCR 701-20. This allows connections to a page of 64 words defined by the content of the MIC 701-15 register (current location + 1).

The third position selects the sequence of the 4 least significant bits coming from the branching vector register RVBO With the 6 bits coming from the branching area of ​​the current microinstruction stored in the register RSCR and the three most significant bits of l address stored in the MIC register. This allows the establishment of 16 connection channels. The fourth position selects the sequence of the two least significant ZEROS with 4 bits coming from the branching vector register RVBO, with the 4 most significant bits of the branching address zone of the microinstruction in progress and with the 3 bits most significant of the current address stored in the MIC register. This makes it possible to establish 16 connection channels with 3 locations of control memory between two adjacent pairs of destination addresses.

The fifth position selects the sequence of 2

Least significant ZEROS with 2 bits from the RVBI branch vector register, with the 6 bits of the branch address of the current microinstruction and the 3 most significant bits from the MIC register. This allows connections with 4 possible destinations and with 3 control memory locations between two adjacent pairs of destination addresses.

The sixth position selects the sequence of 2 least significant ZEROS with 2 bits coming from the branching vector register RGB2, with the 6 bits of the branching address of the microinstruction in progress and the 3 most significant bits of the MIC register . This allows 4 connection channels with 3 control memory locations between two adjacent pairs of destination addresses.

2o The output of the switch 701-12 ensures the addressing of a specific location of the control memory 701-2 for the reading of a microinstruction word having the configuration indicated in FIG. 6b. Referring to this figure, it can be seen that this microinstruction word is coded so as to contain a certain number of different zones which are used for the control of the various functional units of the processor 700. On. will describe in the following only the areas which are related to the example considered.

Bits 0—1 Reserved for future use.

Bit 2 EUFMT Defines the configuration or mast of EU.

EUFMT = 0 specifies a first microinstruction configuration while EUFMT = 1 specifies another microinstruction configuration.

Bits 3-5

TEL Write command in TR low level.

Write command in temporary registers or EU maneuver TR0-TR3

Bits 6-8

Bits 9-12

Bits 13-16

Bits 17-1Ô

<td>oxx</td><td>No change</td><td></td>

<td> 100</td><td>TRO writing</td><td></td>

<td> 101</td><td>TRI writing</td><td></td>

<td> 110</td><td>TR2 writing</td><td></td>

<td> 111</td><td>Write TR3</td><td></td>

<td>TEA</td><td>Write command</td><td>in TR ni-</td>

<td></td><td>high calf</td><td> *</td>

<td>Order</td><td>writing in registers</td><td>temporary</td>

<td>EU TR4-TR7.</td><td></td><td></td>

<td>OXX</td><td>No change</td><td></td>

<td> 100</td><td>TR4 writing</td><td></td>

<td> 101</td><td>TR5 writing</td><td></td>

<td> 110</td><td>TR6 writing</td><td></td>

<td> 111</td><td>Write TR7</td><td></td>

ZOPA ZOPA switch control.

<td colspan="2">Selection of</td><td colspan="2">the output of the ZOPA switch.</td>

<td> 0)</td><td> 0000</td><td>TRO</td><td></td>

<td> 1)</td><td> 0001</td><td>SORTING</td><td></td>

<td> 2)</td><td> 0010</td><td>TR2</td><td></td>

<td> 3)</td><td> 0011</td><td>TR3</td><td></td>

<td> 4)</td><td> 0100</td><td>TR4</td><td></td>

<td> 5)</td><td> 0101</td><td>TR5</td><td></td>

<td>t</td><td>0110 Olil</td><td></td><td></td>

<td> 8-11)</td><td>10XX</td><td>RDI</td><td></td>

<td> 12)</td><td> 1100</td><td>ZEB</td><td></td>

<td> 13)</td><td> 1101</td><td>ZEB</td><td></td>

<td> 14)</td><td> 1110</td><td>ZEB</td><td></td>

<td> 15)</td><td> 1111</td><td>0 (invalidation)</td><td></td>

<td>ZOPB</td><td></td><td>Switch control</td><td>ZOPB.</td>

<td colspan="2">Selection of</td><td>switch output</td><td>ZOPB.</td>

<td>ZRESA</td><td></td><td>Switch control</td><td>ZRESA.</td>

<td colspan="2">Selection of</td><td>the switch output</td><td>ZRESA.</td>

Bits 19-20

ALU

Shift circuit 1Ô Interpreter / RDI switch 11 ZDO

ZRESB ZRESB switch control

Select the output of the ZRESB switch.

Bit 21

<td> 00</td><td>ALU.</td>

<td> 01</td><td>Shift circuit</td>

<td> 10</td><td>RDI interpreter memory switch</td>

<td> 11</td><td>ZDO</td>

<td>RSPB</td><td>Sampling command</td>

memory buffer interpreter

Bit 22

Bit 23

Bits '24 -25

RSPB sampling with ZRESB data.

No sampling 1 RSPB sampling

RSP Memory write command _ interpreter

Reading interpreter memory 1 Writing interpreter memory

ZSPDX Interpreter / RDI memory switch command.

Selection of the interpreter / RDI memory switch output.

Interpreter memory output

I RDI

ZSHFOP Operand switch control for the shift circuit

Selection of the operand on the left for the shift circuit

ZOPA output 01 EIS output 10 0

II Selects from 0 or -1 depending on bit 0 of the right operand for the shift circuit.

Bits 24-27

Bits 24-29 5 Bits 26-31

Bits 30-31

Bits 32-33

Bits 32-35

Bits 34-35

Bits 36-37

Bits 38-40

ALU ALU function command.

Selection of the operation carried out on the two inputs (A and B) of the ALU.

TS / &amp;.

RFU Reserved for future use.

ZALU ALU switch control.

Selection of the ZALU switch output. NXTB Next descriptor command.

Sampling of the RBASB and RDESC registers.

<td> 00</td><td>RBASB 4-</td><td> 00</td>

<td></td><td>RDESC 4-</td><td> 00</td>

<td> 01</td><td>RBASB</td><td> 01</td>

<td></td><td>RDESC</td><td> 01</td>

<td> 10</td><td>RBASB «-</td><td>Alt</td>

<td></td><td>RDESC &lt;-</td><td> 10</td>

<td> 11</td><td colspan="2">No sampling (default)</td>

<td>CCM</td><td>Reference of</td><td>constant area</td>

<td></td><td>control</td><td>through the CONTF area.</td>

<td>IBPIPE</td><td colspan="2">Pipeline / IBUF order.</td>

Selection of IBUF reading or pipeline operation.

No operation

IBUF / ZDI reading (Alt)

Type I restart restart or

Waiting for Type 4 restart.

FMTD

Selection of the loading of the different CU registers and indication of the interpretation to be given to the MEMADR area for a small CU command.

No operation

RADO «- ASFA

RADO &lt;- ZRESB

RADO &lt;- ASFA

MEMADR Cache control.

Selection of cache operations. The complete interpretation of this command depends on the FMTD command.

Bit 41

Bits 42-44

<td> 000</td><td>No operation</td>

<td> 001</td><td>Reading Sgi</td>

<td> 010</td><td>Quad charging</td>

<td> 011 &gt;</td><td>Pre-reading</td>

<td> 100</td><td>Sgi writing</td>

<td> 101</td><td>Dbl writing</td>

<td> 110</td><td>Read Sgi Trans (for FMTD = 11 only)</td>

<td> 111</td><td>Write Sgi Word (for FMTD = 11 only)</td>

<td>ZONED</td><td>Zone control</td>

<td>Indication</td><td>of an area or lack of</td>

<td>area for</td><td>small CU order</td>

<td> 0</td><td>Absence of zone</td>

<td> 1</td><td>Zoned</td>

<td>TYPA</td><td>Type A indicator.</td>

Indication of type A covered areas that are used.

000 Type A zones = 0

Bits 44-46

100 Type A zones = 4.

PIPE Pipeline control.

Selection of the type of restart to launch. 000 No operation

<td> 001</td><td>Restart</td><td>and</td><td>release</td><td>Type 1</td>

<td> 010</td><td>Restart</td><td>and</td><td>release</td><td>Type 2</td>

<td> 011</td><td>Restart</td><td>and</td><td>release</td><td>Type 3</td>

<td> 100</td><td>Restart</td><td>and</td><td>release</td><td>Type 4</td>

<td> 101</td><td>Restart</td><td>and</td><td>release</td><td>Type 5</td>

<td> 110</td><td>Restart</td><td>and</td><td>release</td><td>Type 6</td>

AUXREG Write command in auxiliary register.

Selection of an auxiliary register or combinations to be sampled with data selected by the AUXIN control area.

Bits 44-47

Bits 45-46

Bit 47

Bit 47

Bits 47-48 Bit 47

Ο) 0000 No sampling

1) 0001 RRDXA

2) 0010 R29

3) 0011 R29, RRDXA. FRL, RÏD

4) 0100 RRDXB

<td> 5)</td><td> 0101</td><td>RTYP</td><td></td>

<td>e)</td><td> 0110</td><td>RBASA</td><td></td>

<td> 7)</td><td>YES</td><td>RBASA,</td><td>RTYP</td>

<td> 8)</td><td> 1000</td><td>RBASB</td><td></td>

<td> 9)</td><td> 1001</td><td>RBESC</td><td></td>

<td> 10)</td><td colspan="2">RBASA, R29,</td><td>RRDXA</td>

TYPB Type B indicator.

Indication of Type B covered areas that are used.

Type B = 0 zones

Type B = 3 zones.

BSC Sampling order

RSC.

Sampling from the RSC register. (account shift)

RSPA Sampling control

RSPA.

Sampling of the RPSA register.

N / A

RAAU Sampling command

RAAU.

RAAU register sampling.

Bits 48-49 ZLX ... ZLX switch control.

Selection of the Z-LX switch output.

<td>Bits 48-49</td><td>ASPA</td><td>ZSPA switch control.</td>

<td></td><td>Selection of</td><td>the output of the ZSPA switch.</td>

<td>Bits 48-50</td><td>IN THE .</td><td>Register entry command auxiliary.</td>

Data selection To be sampled in auxiliary register (s).

<td rowspan="2">Bit</td><td rowspan="2"> 49</td><td colspan="3">ZADSP</td>

<td>Selection</td><td>of</td><td>the</td>

<td>Bits</td><td> 50-52</td><td>ZSC</td><td></td><td></td>

<td></td><td></td><td>Selection</td><td>of</td><td>the</td>

<td>Bits</td><td> 50-52</td><td>ZRSPA</td><td></td><td></td>

<td></td><td></td><td>Selection</td><td>of</td><td>the</td>

<td>Bits</td><td> 50-52</td><td>ZAAU</td><td></td><td></td>

<td>Bit</td><td> 51</td><td>RSIR</td><td></td><td></td>

ZADSP switch control. ZADSP switch output. ZSC switch control. ZSC switch output. ZRSPA switch control. ZRSPA switch output. ZAAU switch control. RSIR register sampling.

Bit 53

53-54

Bits

Bits 54-57

Bits 55-56

Bits 55-56

Bits 57-58

Bits 59-62

Sampling of the RSIR register as a function of the AUXIN zone.

RDW Sampling of registers

RIDW, R2DW.

Sampling of the R1DW or R2DW register according to the RDESC register.

ZLNA ZLNA switch command.

Selection of the ZLNA switch output. CONTF Order of various scales.

Selection of one of four groups of flip-flops for setting to 1 or setting to 0 by the constant control area (CCM). The scales include those of blocks 704-104 and 704-110.

ZSNB ZLNB switch command.

Switch output selection · ZLNB. ZSP1 (2) Type A = 2) Switch control

ASPA, RSPA Register.

Selection of the output of the ZSPA switch and sampling of the RSPÂ register.

ZPC ZPC switch command.

Selection of the ZPC switch output. ZXP Control of the ZXP switch, and of the BXP register group.

Selection of the output signal of the SXP switch and of the RXP register in which it must be written.

Bits 59-63

Bits 59-60

ZLN (1) Control of the ZLN switch, (Type A = l) and of the RLN register group

Selection of the output of the ZLN switch and of the RLN register in which it should be written.

ZPA Switch control · ZPA.

Selection of the ZPA switch output.

= RPO

Bits 61-62 = RP3

ZPB

Selection of

ZPB switch command the ZPB switch output.

= RPO

Bits 63-64

II = RP3

ZXPL Control of the ZXPL switch.

(Type A = 0)

Selection of the ZXPL switch output. 00. = RXPA

<td>Bit 63</td><td>1-1 = RXPD ZLN (2)</td><td colspan="2">Switch control ZLN βϊλ</td>

<td></td><td>(Type A = 2)</td><td>of the group</td><td>RLN registers</td>

<td></td><td>Selection of</td><td>signal from</td><td>switch output</td>

<td></td><td colspan="2">ZLN and RLN register</td><td>in which he must</td>

<td>Bits 63-66</td><td>be written. RDIN</td><td colspan="2">Entry command in the re-</td>

RDI register.

Selection of the data to be entered in the RDI register and selection of one of the modification control zones (MF ^ - MF ^, TAG),

Bit 64

Bits 64-68

Bits 65-66

Bits 65-66

Bits 67-68

Bit 67

Bit 67 of an instruction word.

RDI sampling can also be ordered through the MISCREG area.

ZXPL (1) ZXPL switch control.

(Type A = l)

Selection of the ZXPL switch output. ZRPAC Control of the ZRPA switch, (Type A = 2) of the ZRPC switch and of the RP0-3 register group Selection of the outputs of the ZRPC and ZRPA switches and of the RPÛ-3 register in which the ZRPA output signal must be written.

ZXPR Control of the ZXPR switch.

(Type A = 0)

Selection of the ZXPR switch output. ZXP (1) ZXP switch (Type A = 1) switch and RXP register group.

Selection of the output signal of the ZXP switch and of the RXP register in which it. must be written.

ZPD ZPD switch command.

(Type A = 0)

Selection of the ZPD switch output. ZRPAC (4) Switch control

ZRPA, the ZPRC switch, and the RPO-3 register group.

Selection of CP4 from the ZRPA switch and sampling of register RP1.

TYPD Type D Indicator.

Type D indicator which defines the areas covered with Type D.

ZRPB (4) Control of the ZRPB switch (Type A = 4) and of the register group

RP4-7

Selection of 0 in the ZRPB switch and sampling of the RP4 register.

Bit 68

Bits 68-71

MLM Cache Control

Selection of the cache operation in relation to the SZ command.

0) 0000 No operation.

Bits 68-70

Bits 69-73

Bits 69-73

Bits 69-71

Bits 72-74

15) 1111 remote writing.

IBÜF XBUE read command.

Selection of the destination of the data obtained after reading IBUF.

AXP Control of the ZXPA switch (Type A = 0), of the ZSPB switch, of the AXP adder of the ZAXP switch and of the RE register.

Selection of the output signals of the ZXPA and ZXPB switches, of the function of the AXP adder applied to them, and of the output signal of the ZAXP switch.

Also sampling from the RE register.

ZRPB Control of the ZRPB switch (Type A = D © of the group of registers RP4-7. Selection of the output signal of the switch ZRPB and of the register RP4-7 in which it must be written.

ZRPAC-3 (Type A = 3)

Control of the ZRPA switch, the ZRPC switch and the RPO-3 register group.

Selection of the output signals of the ZRPB and ZRPA switches and of the / RPO-3 register in which the ZRPA output signal must be written.

ZRPB (3) (Type A = 3)

ZRPB switch and RP4-7 register group control

Selection of the output signal of the ZRPB switch and of the register RP4-7 in which it must be written.

Bits 72-73 ₅ Bits 74-78 'Bits 74-78

Bit 74

Bits 75-77

Bits 75-78

Bits 75-78 30

Bit 78

Bits 79-83

SZ Capacity control / cache area

Control of cache operations in relation to the MEM control area.

ZRPB (0) Control of the ZRPB switch and of the register group (Type A = 0) RP4-7

Selection of the output signal of the ZRP switch and of the register RP4-7 in which it should be written.

AL Control of switch ZALA, (Type A = l) of switch ZALB and adder AL.

Selection of the output signals of the switches ZALA and ZALB and of the function of the adder AL which is applied to them.

TYPE Type E indicator.

Type E indicator which defines the Type E covered areas

ZXP (3) Control of the ZXP switch and (Type A = 3) of the RXP register group.

Selection of the output signal of the ZXP switch and of the RXP register in which it should be written.

MISCREG Order of various registers.

Selection of the various operations carried out on various registers (for example RBIR, RDI, PLEN, RSPP).

ZDO ZDO switch command.

Selection of the ZDO switch output.

ZIZN Control of the ZIZN switch.

Selection of the ZIZN switch output.

AP Control of switch ΖΑΡΑ of switch ZAPB and of adder AP.

Selection of the output signals of switches ΖΑΡΑ and ZAPB and of the function of the AP adder applied to them.

242511©

Bits 79-81

ZLN (3) Control of the ZLN switch (Type A = 3) and of the 'RLN register group

Bits 79-83

Bits 80-81

Bits 82-83

Bit 84

Bits 85-86 Bit 86

Bit 87

Bits 88-89

Selection of the output signal of the ZLN switch and of the RLN register in which it should be written.

ZLN (4) (Type A = 4)

ZLN switch and RLN register group control

Selection of the output signal from ZLN and the RLN register in which it should be written. RAAU Sampling of registers

RAAU / RE.

Selection of the data to be sampled in the RAAU and RE registers by command of different switches and adders operating in unit 722.

AP (3) Control of switch ZAP A, (Type A = 3) of switch ZAPB and adder AP

Selection of the output signals of switches ΖΑΡΑ and ZAPB and of the function of the AP adder applied to them.

ZRSC Control of the ZRSC switch.

(Type A = 0)

Selection of the ZRSC switch output. N / A

RLEN

RLEN sampling order (Type A = 3).

The RLEN samples are also controlled by the equipment or by the MISCREG area.

FMT

Indicates the TYPE

Indicate the

Indicator of conformation type of conformation type of covered areas.

= Interpreter memory address

Bit 90 Bits 90-93

Bit 90

Bit 90 Bits 91-97

<td colspan="3">01 = Character Unit Command</td>

<td> 10</td><td>= Order division</td><td>of Multiplication Unit /</td>

<td>11 RFU</td><td>= N / A</td><td>t Reserved for future use</td>

<td colspan="2">CHROP</td><td>Operation code of the character.</td>

<td colspan="2">Selection of a</td><td>main operation to be executed ·</td>

<td colspan="2">ter by unit</td><td>of character and interpretation</td>

<td>tion</td><td>to give A</td><td>the CHSUBOP area.</td>

<td> 0)</td><td> 0000</td><td>No operation</td>

<td> 1)</td><td>Q001</td><td>Data loading</td>

<td> 2)</td><td> 0010</td><td>MOP execution</td>

<td> 3)</td><td> 0011</td><td>Simple comparison</td>

<td> 4)</td><td> 0100</td><td>Double comparison</td>

<td> 5)</td><td> 0101</td><td>Register loading</td>

<td> 6)</td><td> 0110</td><td>CN update</td>

<td> 7)</td><td>YES</td><td>Undefined</td>

<td> 8)</td><td> 1000</td><td>Operation RCH update AT</td>

<td> 9)</td><td> 1001</td><td>RTF1 update</td>

<td> 10)</td><td> 1010</td><td>RTF2 update</td>

<td> 11)</td><td> 1011</td><td>RTF3 update</td>

<td> 12)</td><td> 1100</td><td>RCN1 update</td>

<td> 13)</td><td> 1101</td><td>RCN2 update</td>

<td> 14)</td><td> 1110</td><td>Updating of indicators edition</td>

<td>15) RCH</td><td> 1111</td><td>Resetting the CH Unit Register sampling RCH</td>

Bits 91-93

Sampling of the register RCH 0P1.

RFU Reserved for future use.

SPA Interpreter memory address.

Contains the address which can be used to address the EU interpreter memory.

N / A.

<td>CHSUBOP</td><td>Character Unit subcode-operation.</td>

<td colspan="2">Selection of the detailed function of the Unit</td>

<td colspan="2">of character or may contain a cons-</td>

<td colspan="2">aunt. The interpretation of this area is</td>

<td>depending on the</td><td>CHROP command, as shown</td>

<td>in the following.</td><td> -</td>

<td>CHROP = 0000:</td><td>No operation</td>

<td>chsubop_o_₃</td><td></td>

<td>XXXX</td><td>No interpretation.</td>

<td>CHROP = 0001:</td><td>Loading operation</td>

<td>data CHSUB0P_not_₁</td><td>(Sub-operation)</td>

<td> 00</td><td>Loading of OPI by Œ1 and</td>

<td></td><td>TF1</td>

<td> 01</td><td>Reverse loading of OPI by</td>

<td> 10</td><td>CN1 and TF1 Loading of 0P2 by CN2 and</td>

<td></td><td>TF2 and character control</td>

<td> 11</td><td>Sign loading</td>

<td>CHSUB0P₂_₃</td><td>(Fill order)</td>

<td>IX</td><td>Fill character</td>

<td>XI</td><td>loaded in ZCU Fill character</td>

<td>CHROP = 0010:</td><td>loaded in ZCV. MOP execution operation</td>

<td>CHSUBOP_O_₁</td><td>(Sub-operation)</td>

<td> 00</td><td>MOP set to one by CN2</td>

<td> 01</td><td>MOP execution</td>

<td> 10</td><td>Undefined</td>

<td> 11</td><td>Undefined</td>

<td>CHSUBOP₂_₃XX</td><td>No interpretation.</td>

<td>CHPOP = 0101:</td><td>Loading operation</td>

register

CHSUB0Pq_ ^ (Selects the output of

RCH)

<td></td><td></td><td></td><td>CHSUB0P₂_₃</td><td>(Selects the output of the switch Z0C)</td>

<td></td><td></td><td></td><td>CHROP = 1011</td><td>: RTF3 update operation</td>

<td></td><td></td><td></td><td>CHSUB0P₀_₁</td><td>(Selects data to</td>

<td> 5</td><td></td><td></td><td></td><td>check for 00, indicating a 9-bit character).</td>

<td></td><td></td><td></td><td>CHSUBÛP₂_₃CHROP = 1110</td><td>(Constant area) : Operation to set up an information</td>

<td></td><td></td><td></td><td>&lt;</td><td>editing.</td>

<td> 10</td><td></td><td></td><td>chsubop_q_₃</td><td>(Selection indicators constant to set to one)</td>

<td></td><td></td><td></td><td>IXXX</td><td>Update. one of ES (end of deletion)</td>

<td></td><td></td><td></td><td>X1XX</td><td>Setting of SN (sign)</td>

<td> 15</td><td></td><td></td><td>XXIX</td><td>Put to one of Z (zero)</td>

<td></td><td></td><td></td><td>XXXI</td><td>BZ update (Clear in case of zero)</td>

<td></td><td>Bits</td><td> 94-97</td><td>RFU</td><td>Reserved for future use.</td>

<td></td><td>Bits</td><td> 96-97</td><td>N / A</td><td></td>

<td> 20</td><td>Bit</td><td> 98</td><td>TYPG</td><td>Type G indicator.</td>

Indicates the type of areas covered.

O = BRADRU area = IND6 area

<td>Bit 99</td><td>GO</td><td>Branch status monitoring</td>

<td> 25</td><td></td><td>conditional.</td>

<td>Bits 99-106</td><td>BRADRU</td><td>Superior branch address</td>

<td></td><td></td><td>dearly.</td>

<td>Bits 99-106</td><td>IND6FLD</td><td>Indicator control.</td>

<td></td><td colspan="2">Select an indicator.</td>

<td>3θ Bits 99-106</td><td>Bit 99 =</td><td>0, specifies an instruction of</td>

<td></td><td colspan="2">change of indicators.</td>

<td></td><td>Bit 99 =</td><td>1, specifies an instruction of</td>

<td></td><td colspan="2">setting indicators to zero (setting one or</td>

resetting being indicated respectively by a bit X of binary value O or 1). '

Bits 100-104 105 = 1

0000

106=1

Bits 107-112

Bit 113

Bits 114-116

Bits 117-118 Bits 119-123

Bit 124

Bits 125-128

<td>1100X</td><td>End 1</td><td>End</td><td> 2</td>

<td>nuts</td><td>End 3</td><td>N / A</td><td> •</td>

<td>stainless steel</td><td>End 1</td><td>End</td><td> 2</td>

Eff. Eff.

BRADEE Lower connection address.

Contains the lower part of a DHW address used for connection.

EXIT Selection of an output switch command.

A selection of EXIT indicates an end of firmware.

ZCSBRA Switch control

ZCSBRA.

Definition of the position to be selected in a control memory branch address switch.

N / A

INDGRP Conditional branch indicator group control.

The first two bits (119-120) select the group of firmware indicators. The last three bits (121-123) select the series of flags within each group.

TYPH Type H area.

Indicates areas covered with Type H.

O = ÏNDMSKU 1 = VCTR area.

INDMSKÜ Top mask of conditional connection indicator.

Contains the 4 most significant bits of the indicator mask in the Type H = 0 area.

Bits 125-129

Bits 129-1-32

Bits 133-135 Bits 136-139

VCTR Vector selection.

Selection of branching vectors to be sampled in the RVBO registers,

RGBI and RGB2. The most significant bit (125) determines which of the two groups O or 1,2 or 3 and 4 or 5 which is sampled respectively in the registers RVBO, RVBI and RGB2. The remaining 3 bits select the vector within each group. INDMSKL Bottom mask of conditional connection indicator.

Contains the 4 least significant bits of the indicator mask.

N / A

CNSTU Upper part of the constant zone.

Contains the 4 most significant bits of the constant area.

Bits 140-143 CNSTL Lower part of constant zone

Contains the 4 least significant bits of the constant area.

Control logic unit 704-1

This unit comprises the logic decoding sequence circuits 704-100 mentioned above and the outputs of which supply several flip-flops of cycle control state I forming part of block 704-102. These flip-flops produce, in response to signals from circuits 704-100 and to microinstruction signals from register 701-4 (DEMRO33-4O which corresponds to the memory address area MEMADR of FIG. 6b). Cycle I control states required to execute program instructions. It will be assumed that block 704-102 also contains control circuits which generate register hold signals [holdeOO which are distributed in processor 700.

_θ4 2425110

As shown in FIG. 3c, the cycle control state flip-flops I receive control input signals via control lines, in particular a CPSTOPOO line connected to the cache memory 750. As will be specified below, the state of the line CPSTOPOO determines the continuation of the operation of the processor since, when the line is switched to the binary ZERO state, the signals for maintaining or enabling the flip-flops of Cycle I control state and other memory registers are also switched to ZERO state. The holding signals corresponding to the [HOLDIOO and (HOLDEOO) signals act so as to maintain or freeze the state of the processor 700. Since there can be no increase in the address of the control memory, the ECS control memory extracts the same microinstruction word. The signals [jSOLDI and [HOLDE are generated in accordance with the following Boolean expressions: [hOLDI = CACHE HOLD + TERMB (DREQ-IF-DIP) + HOLD REL, in which the state of the CACHE HOLD signal corresponds to the state of the CPSTOP signal, the states of the TERMB signals (DREQ-IF-DIR) correspond to binary DNS during the FPOA command state when the cache instruction specifies an I extract or direct operation and the HOLD REL signal in binary state UN until it is switched to state binary ZERO by generation of a firmware release signal; and HOLD E = HOLD 1.

According to the invention, each of the instructions which constitute the directory of the preferred embodiment of the invention is assigned one of a number of command sequence codes (CCSS), defined below and which allow the efficient processing of instruction cycles. These different classified of material sequence are established in order to obtain the desired performances during the execution of the whole of the repertoire of instructions listed in appendix A. The sequence of the material corresponding to each instruction is chosen so as to obtain the particular type of operation necessary for efficient operation in pipeline.

The instructions are symbolically designated in correspondence to an instruction index included in Appendix A. A number of instructions have been described in the publication Series 60 (Level 66) / 6000 MACRO Assembler Program (GMAP), published by Honeywell Information Systems Inc., 1977 Order No. DDO8B, Rev.O.

<td>ccs-s</td><td>SEQUENCE</td><td>TYPE OF INSTRUCTION</td>

<td> 000000</td><td>LD-SGL</td><td>LDA, LDQ, LCA, LCQ, ADA. ATWOQ ADQ, ADLA, ADLQ, AWCA, / SWOA,</td>

<td></td><td></td><td>SWCQ, CMPA, CMPQ, CANA, CANQ,</td>

<td></td><td></td><td>ANA, ANQ, ORA, ORQ, ERA, ERQ, SBA, SBQ, SBLA, SBLQ, LDE, SZN, FSZN, LX1N, LDI</td>

<td> 000001</td><td>LD-SGL-DEL</td><td>FLD, CNAA, CNAQ, ADE</td>

<td> 000010</td><td>LD-SGL-ESC</td><td>MPY, MPF, DIV, DVF, CWL, CMG, CMK, FAD, UFA, FSB, UFS, FMP, UFM, FDV, FDI, LDT, FCMP, FCMG, CCD, ADL, XEC, CIOC, LPDBR, LDDSA, LDO, LDPn, LDEAn, PAS, LARn, AARn, NAPn, LDWS.</td>

<td> 000011</td><td>LD / STR-SGL-ESC</td><td>ASA, ASQ, AOS, SSA, SSQ, ANSA, ANSQ, ORSA, ORSQ, ERSA, ERSQ, ARAn, nRNA, SARn.</td>

<td> 000100</td><td>LD-HWU</td><td>ADLXn LDXn, LCXn, ADXn, / SBXn,</td>

<td></td><td></td><td>SBLXn, ANXn, ORXn, ERXn, CMPXn.</td>

<td> 000101</td><td>LD-HWU-DEL</td><td>CNAXn</td>

<td> 000110</td><td>LD-HWU-ESC</td><td>LBAR, LBER, LMBA, LMBB</td>

<td> 000111</td><td>LD / STR-HWÜ-ESC</td><td>ASXn, SSXn, ANSXn. ORSXn,</td>

<td></td><td></td><td>ERSXh</td>

<td> 001001</td><td>LD-DBL</td><td>LDAQ, LCAQ, ADAQ, ADLAQ,</td>

<td> -</td><td></td><td>SBAQ, SBLAQ, ANAQ, ORAQ, ERAQ, CMPAQ, CANAQ, DFLD.</td>

<td>ccs-s</td><td>SEQUENCE</td><td>TYPE OF INSTRUCTION</td>

<td> 001010</td><td>LD-DBL-ESC</td><td>CNAAQ, XED, LDSS, LDAS, LDPS, LDDSDj DFSB, DUFS, DFMP, DUFM, DFDV, DFDI, DFCMP, DFCMG, DFAD, DUFA, QFLD, QFAD, QFSB, QFMP, QSMP.</td>

<td>οιοοοοο</td><td>STR-SGL</td><td>STA, STQ</td>

<td> 010001</td><td>STR-HWU</td><td>STXn</td>

<td> 010010</td><td>STR-DBL</td><td>STAQ</td>

<td> 010100</td><td>RD-CLR</td><td> -</td>

<td> 011000</td><td>EFF-ADR</td><td>ΕΔΑ, EAQ, EAXn, NEG</td>

<td> 011010</td><td>EFF-ADR-ESC</td><td>ARS, QRS, LRS, ALS, QLS, LLS, ARL, QRL, LRL, ALR, LLR, QLR, FTB, NEGL</td>

<td> 100000</td><td>TRF</td><td>TRA, TZE, TNZ, TMI, TPL, TRC, TNG, TOV, T-EQ, TEU,</td>

<td></td><td> -</td><td>TTF, TRTN, TRTF, TTN, TMOZ, TPNZ</td>

<td></td><td></td><td>RPD,</td>

<td> 100100</td><td>ESC</td><td>RCCL, LCCL, RPTj / RPL, STAC, STCQ, STBA, STBQ, MME, DRL, ILLOC, CCAC, AWD, SWD, A9BD A4BD, A6BD, ABD, S9BD, S4BD S6BD, SBD, CAMP, RPN, RIMPR SFR, LLUF , LIMR, RRES, EALT SDRn, EPAT.</td>

<td> 100101</td><td>ESC-LD</td><td>M MLDA, MLDQ, MLDAQ</td>

<td> 100110</td><td>ESÇ-ST</td><td>MSTA, MSTQ, MSTAQ.</td>

<td></td><td></td><td> 67</td><td> 2425110</td>

<td></td><td>CCS-S</td><td>SEQUENCE</td><td>TYPE OF INSTRUCTION</td>

<td></td><td> 101000</td><td>NO-OP</td><td>NOP</td>

<td> 5</td><td> 101001</td><td>TSXN</td><td>TSXN</td>

<td></td><td> 101010</td><td>ESC-EA</td><td>LREG, SREG, STC1, STC2, FSTR,</td>

<td></td><td></td><td></td><td>DFSTR, STE, SBAR, TSS, RET, SPL, LPL, STI, SBER, SMBA, SMBB, SAREG, SXLn, BPÂT,</td>

<td> 10</td><td></td><td></td><td>EPPRn, CLIMB, STWS, STPn, \ LAREG, QFSTR, LDDn, FST, DFES FRD, DFRD, FNEG, FNO, STDn, LDAC, LDQC, SZNC, DIS.</td>

<td> 15</td><td> 101100</td><td>DEL-STR-SGL</td><td>STT, STZ, SPDBR, STPDW, STPTW, STDSA, STO</td>

<td> 20</td><td> 101101</td><td>DEL-STR-DBL</td><td>STSS, STDSD, STTA, STTD, STPS, STAS, SDZn, QFST.</td>

<td></td><td> 110000</td><td>BIT</td><td>CSL, CSR, SZTL, SZTR, CMPB</td>

<td></td><td> 110001</td><td>• MTM-MTR</td><td>MTM, MTR.</td>

<td> 25</td><td> 110011</td><td>MRL</td><td>MRL</td>

<td></td><td> 110100</td><td>tct</td><td>TCT</td>

<td></td><td> 110101</td><td>TCTR</td><td>TCTR</td>

<td> 30</td><td></td><td></td><td></td>

<td></td><td> 110110</td><td>SCAN-FWD</td><td>SCM, SCD</td>

<td></td><td> 110111</td><td>SCAN-REV</td><td>SCMR, SCDR.</td>

<td> 35</td><td> 111000</td><td>NUM2</td><td>'MVN, MVNX, CMPN, CMPNX,</td>

AD2D, AJD2DX, SB2D, SB2DX, DV2D, DV2DX, MP2D, MP2DX

<td>ccs-s</td><td>SEQUENCE</td><td>TYPE OF INSTRUCTION</td>

<td> 111001</td><td>MVT</td><td>MVT</td>

<td> 111010</td><td>CONV</td><td>BTD, DTB</td>

<td> 111011</td><td>MLR</td><td>MLR</td>

<td> 111100</td><td>NUM3</td><td>AD3D, AD3DX, SB3D, SB3DX, MP3D, MP3DX, DV3D, DV3DX.</td>

<td> 111101</td><td>EDIT</td><td>MVE, MVNE, MVNEX</td>

<td> 111110</td><td>CMPC</td><td>CMPC '</td>

<td> 111111</td><td>CMPCT</td><td>CMPCT</td>

<td>affected</td><td colspan="2">The sequence differences that can be to the material intervene in the following way. MATERIAL SEQUENCES</td>

<td>LD-SGL</td><td></td><td></td>

This sequence forces the control unit to generate the effective address during an FPOA cycle and forces the cache memory to execute a simple memory read cycle. When indirect addressing is specified, the control function is transferred to a firmware routine used for address preparation. The requested data is entered into the RDI register at the end of the cache cycle and is then available for possible use during the execution cycle.

LD-SGL-DEL

This sequence of 2T material is the same as LD-SGL, except that a 1T delay state is introduced after the FPGA cycle (FPOA -&gt; FDEL -&gt; FPOA-NEXT).

LD-SGL-ESC

This sequence is the same as LD-SGL, except that the pipeline is stopped after termination of the current FPOA cycle (an escape state is introduced).

LD-HWU

Identical to the LD-SGL sequence, except that bits 00-17 of the RDI register are loaded from

The cache. Memory bits 00-17 and zeros are loaded into the RDI register ^^ g ^.

LD-HWY-DEL

This 2T hardware sequence is the same as the LD-HWU sequence, except that an IT delay state is introduced after the FPOA state. The sequence is FPOA -&gt; FDEL-&gt;

FPOA-NEXT.

LD-HWU-ESC

This sequence is the same as the LD-HWU sequence, except that the ^ ipeline is stopped after termination of the current FPOA cycle.

LD / STR-SGL-ESC

This sequence is the same as the LD-SGL-ESC sequence, except that, in addition to normal read checks, a write check is also carried out. This sequence is used for the READ-ALTER-REWRITE transaction types

READ-MODIFY-REWRITE.

LD / STR-HWU-ESC

This sequence is the same as the LD / STR-ESC sequence, except that bits 00-17 of the RDI register are loaded from bits 00-17 of the cache memory and zeros are loaded in RDI ^ g_gg.

LD / DBL

This sequence forces the control unit to establish the effective address during an FPOA cycle and it forces the cache memory to execute a double read cycle in memory. The requested data is returned to the RDI register for two consecutive cycles.

LD-DBL-ESC

This sequence is the same as the LD-DBL sequence, except that the escape state is introduced after termination of the current FPOA cycle.

STR-SGL

This 2T sequence (FPOA -&gt; STR) forces the control unit to establish an effective address and forces the cache memory to execute a simple memory write cycle (FPOA). During the second cycle (FSTR), the value to be memorized (selected by the contents of the RRDX-A register) is transferred to

242511G the RADO register as follows: ZX -? ZDO -? * ZRESB -&gt;

RADO.

STR-HWU

This sequence is the same as the STR-SGL sequence, except that the cache only modifies bits 00-17 of a storage location.

STR-DBL

This T3 sequence (F PO A -&gt; F STR-DBL - /

FSTR) forces the control unit to establish an effective address and forces the cache memory to execute a double write cycle in memory (command state FPOA). During the second and third cycles, the data words EVEN and ODD (PAIRS and ODD) (selected by the contents of the register RRDX-A) are sent to the cache memory.

RD-CLR

This sequence is the same as the LD-SGL sequence, except that the cache memory reads the storage location and also erases it.

EFF-ADR

This sequence obliges the control unit to load bits 00-17 of the RDI register with an effective address which is established during an FPOA cycle while bits 1835 of the RDI register are loaded with zeros.

EFF-ADR-ESS

This sequence is the same as the EFF-ADR sequence, except that lqfcipeline is stopped after the FPOA cycle (Introduction of the state of change).

TRF

This sequence forces the control unit to request two four-word instruction blocks (during FPOA and FTRF command states) for the instruction buffer in preparation for a command transfer or branching operation.

ESC

This sequence produces a pipeline stop after the FPOA cycle. No memory cycle is started and no address preparation is carried out.

ESC-LD &amp; ESC-STR

These sequences are the same as ESC and they are used to carry out control or test operations.

5_ ESC-EA

This sequence obliges the control unit to introduce an address pointer established during the FPOA cycle into a temporary register. The pipeline is stopped after FPOA. DEL-STR-SGL

This 3T sequence (FPOA-FDE-L-FESC) obliges the control unit to establish an effective address during the FPOA state and then to switch to a second FDEL state. This allows the cache to perform an additional cycle to retrieve the data to be stored. At the end of FDEL, the cache memory is forced to launch a simple memory write cycle and the hardware switches to the FESC state. The data to be written is transferred to the RADO register under microprogrammed control.

DEL-STR-DBL

This sequence is the same as DEL-STR20 SGL, except that the sequence is 3T. The sequence corresponds to

FPOA -&gt; FDEL-&gt; FESC. A double memory write cycle is started during the FDEL state. The data are transferred to the RADO register during cycles following the FDEL state under microprogrammed control.

EDIT (EIS)

This sequence corresponds to FP0A-FP0P1FP0E2 followed by FP0P3. A bypass occurs on a microgrammed command which, following the creation of registers, tables, etc ..., necessary for the processing of operands from mi30 is shaped, signals to hardware control circuits take the state FP0P3.

The other EIS sequences can be considered to have states similar to those of the EDIT sequence.

This sequence obliges the processor 700 to calculate the effective address and to update the instruction counter. During a second cycle (FTSX1), the updated instruction counter is loaded into the EDI register for trans₇2 2425110 subsequent fert in the specified index register. The calculated effective address is loaded into TEAO and the processor 700 transfers the control function to this location (FPI-INIT).

The control states of the equipment which are used during a processing cycle I, in accordance with the present invention, will be given below, as well as a brief description of the operations carried out during such control states or cycles.

CYCLE / ORDER STATUS

IN CYCLE I DESCRIPTION

FPOA

FPOP

FSTR

FSTR-DBL

The operand state of FPOA preparation constitutes the initial command state for all the instructions. During FPOA, an address is calculated and the operation code is translated via the CCS command memory for the control of other actions.

FPOP preparation operand pointer state is used to process EIS instruction descriptors.

The storage state FSTR is used to transfer memory data to the RADO register in the case of instructions requiring sequences, and to transfer the second (odd) word of double precision data to the RADO register in the case of instructions requiring double memory sequences.

The double storage state FSTR-DBL is used to transfer the first word (even)

DESCRIPTION

CYCLE / ORDER STATUS IN CYCLE I

FESC

FDEL

-FWF-IND

FTRF

FTRF-NG of precision duplicated data in the RADO register for instructions requiring double memory sequences.

The FESC escape state is used to create a variable delay in the processing pipeline I. During the FESC state, the ESC command memory has finished controlling the processor 700 and it determines when it is necessary to reset the processing pipeline. -I.

The FDEL delay state creates an IT delay in the processing pipeline I.

The waiting state for indirect word FWF-IND fulfills a control function for transferring signals in the RSIR register via the ZDI lines. The FTRF transfer state is used to request that the cache memory extract a second instruction block for loading into the buffer I and sample a first instruction for the introduction of a new instruction stream into the RBIR register. 700 processor.

The No transfer FTRF-NG state is used to reintroduce the address of the old instruction stream into the address registers of buffer-I.

CYCLE / ORDER STATUS IN CYCLE I

DESCRIPTION

FPIM-1

FPIM-2

FPI-INIT

The Instruction Address Preparation state for the Type 1 update in buffer I FPIM-1 is introduced when buffer I is operating with no instructions. During the FPIM-1 state, an instruction block is requested for the I-buffer. Also, during the FPIM-1 state, a processor hold condition is established when the cache signals a no cache condition. The State of instruction address preparation for updating Type 2 in buffer I ”FPIM-2 authorizes the request for a second block of instructions for buffer I. During the state FPIM-2, none processor hold condition is not generated when the cache signals a no cache condition. Also during the FPIM-2 state, the next instruction is sampled in the RBIR register of the processor.

The Etaf'Preparation of instruction address for initialization of the buffer-I FPI-INIT is used for reloading the buffer-I after a transfer (memory comparison) or else after a Type 3 reset.

DESCRIPTION

CYCLE / ORDER STATUS IN CYCLE I

FWF-IBUF

FPIM-EIS

FWF-DESC

FIDESC

FWF-IDESC.

FIT-I

The Buffer-I Ready state ”FWF-IBUF is entered when an instruction must be provided by the I-buffer and when the I buffer is not ready.

The instruction address preparation for EIS update in I-buffer FPIM-EIS state is entered after the FPOA cycle of an EIS multi-word instruction whenever the I-buffer does not contain enough descriptors to complete the processing of the instruction.

The FWF-DESC descriptor standby state is entered when a descriptor must be supplied by the I-buffer and when the I-buffer is not ready.

The FIDESC indirect descriptor state constitutes the command state used to process EIS indirect descriptors.

The command status with awaiting indirect descriptor FWF-IDESC provides a command to transfer the cache word applied to the ZDI lines to the RSIR register 704-154.

Indirect control and indirect counting state ”FIT-I is used to process non-EIS descriptors specifying changes of indirect address and indirect counting.

24251 ίθ

CYCLE / ORDER STATUS

IN CYCLE I DESCRIPTION

FIRT The indirect command and control or FIRT register test state is introduced during the processing of nonEIS descriptors specifying indirect address and register modifications in order to determine whether the processing of this type of address modification has ended.

FTSXl 'The FTSXl index transfer and update control state is used to transfer the updated content of the instruction counter into the RDI register in the case of transfer and update instructions. 'index.

As shown in FIG. 3 &lt;2, signals corresponding to the cycle control states I are applied to the inputs of several control flip-flops of block 704-104, to decoder circuits of block 704-106, to a certain number of circuits control logic of block 704-108 and with several control indication rockers of block 704-110. It can also be seen that the various indication flip-flops of block 704-110 also receive microinstruction input signals via the MEMDO lines 54-57 from the execution control unit 701-4.

As shown in Figure 3d, signals generated by the hardware logic 704-108 control circuits fall into one of three groups depending on the units whose operations are being controlled. control circuits for instruction buffers, hardware control, and hardware memory control.

In each case, the signals of each group are logically combined with equivalent signals generated by other sources and are then decoded. The other sources correspond to zones placed in the two formats- different from the word micro_ΊΊ 2425110 instruction of FIG. 6a_ and which are loaded into the register RCSR 704-112 from the output register ECS 701-4,

One zone corresponds to bits 32-83 of uni mat (large CU) and another zone (small CU) corresponds to bits 32-41 of another format. These areas are decoded by a decoder 704-114 so as to form the indicated series of bits which are combined inside the decoders 704-116, 704-124, 704-126 and 704-128 as indicated. Additional decoding is provided by the circuits of blocks 704-118, 704-135 and 704-120. The results of the decoding of these zones are either distributed in the processor 700 or stored in an RMEM register 704-130, a RSZ flip-flop 704-132, a FREQDIR flip-flop 704-136 and a FREQCAC flip-flop 704-134.

Additional decoding of the large and short CU zones as well as signals from the cycle status circuits I of block 704-112 is carried out via the decoders

704-106 and 704-107. The decoder 704-106 produces control signals intended to load different registers and to authorize the operation of different multiplexing / selection switches intervening in the processor 700. The decoder 704-107 generates set and reset signals two basic pointer scales B 704-144 (RBASB). Other combinations of these signals are used to set and reset the descriptor number flip-flops for blocks 704-140 and 704-142.

As shown in Figure 3 &lt;ï, the decoder 704-116 re25 receives a control signal [eXHOO generated by the decoder circuits of block 704-117. These circuits receive signals from the RDESC register 704-140 and signals from the end flip-flops or exhaustion of the block 701-1. In accordance with the states of these signals, the circuits switch the signal {EXHOOO

3q in the binary ZERO state in order to prevent the generation of a cache command when an end condition occurs. The signal ^ ΕΧΙΓΟΟΟ is generated in accordance with the following Boolean expression:

[EXHOOO = DESCO. FIRE + DECL.FE2 + DESC2.FE3.

The FNUM toggle is normally set to one in response to the CCS-OP area of ​​the microinstruction word. When set to 1, this toggle indicates that the descriptor being processed is of the numeric type.

The different flip-flops of block 704-104 will now be described in more detail below. The FCHAR toggle ensures certain changes in the address generation command. When the FCHAR flip-flop is set to 1 during the processing of a load-type instruction specifying a character modification, the content of the RDI register is not modified under the hardware command. This allows the RDI register to receive data under firmware control before the pipeline starts. Also, if the FCHAR flip-flop is set to 1 during a memorization type instruction specifying a character modification, the execution address of this instruction is modified under control of the hardware with a view to pointing to a unique address in the sequence. microinstruction of the DHW control memory which must process this type of instruction.

The FDT-FOUR flip-flop further commands the reading of the address register (ΖΑΕθ_ ^ θ) of block 704-304. The FADR-WD flip-flop performs an additional control function for the ZDO 704-340 switch. When this flip-flop is set to 1, the ZAR position of the ZDO switch is forced to select a word address. The FADR-B flip-flop provides additional control of the ZDO multiplexer switch. When set to 1, the ZAR position of the ZDO switch is forced to select a byte address. The FNUM toggle is normally set to one in response to the CCS-OP area of ​​the microinstruction word. When set to 1, it indicates that a descriptor being processed is of the digital type. The FIG-LEN flip-flop provides additional control of the loading of the registers intervening in the unit 722, (length registers) and also storage operations. When it is set to 1, the RXP and RLN registers intervening in the unit 722 are not loaded from the RSIR register 704-154 during the FPOP control states.

The FINH-ADR flip-flop prevents the operation of the address preparation unit 704-3. When set to 1, an addressing cycle (FPOA /^ZFPOP) consists in adding the content of a temporary effective address register REA-T + ZERO. The address was loaded into the REA-T register before the end of an FPOA / FPOP cycle. The FABS scale allows the generation of absolute a2425110 dresses. When set to 1, an absolute 24-bit address is used. With regard to the indicator flip-flops in block 704-110, the FID flip-flop, when set to 1, provides an indication that an indirect address modification during instruction must be carried out on the loaded descriptor in the RSIR register.

The FRL flip-flop, when set to 1, indicates that the length is specified in a register associated with the instruction entered in different instruction registers. The three low codes FINDA, FINDB and FINDC provide indications used for the processing of instructions of the memorization type. The FINDA toggle is set to 1 when a length is specified in a register or when the FAFI toggle is set to 1. The FINDB flip-flop is set to 1 when the descriptor does not contain nine-bit characters. The FINDC flip-flop is set to I when the descriptor contains six-bit characters.

The FAFI flip-flop is set to 1 when the processor circuits detect that an indicator bit 30 of the IR register 701-41 has been set to 1 during the execution of an EIS instruction indicating that an interruption in the middle of the instruction ( necessary to adjust pointer and length values ​​due to an interruption). The FTRGP, FINGO and FTRF-TST flip-flops are set to 1 in relation to transfer type instructions. More specifically, the FTRGP flip-flop provides a firmware indication by being set to 1 when the processor circuits detect the reading of a transfer type instruction during execution of a double execution instruction (XED) or repetition instruction (RPTS). The FTNGO flip-flop provides a firmware indication by being set to 1 when the transfer condition signaled by the execution control unit 701 corresponds to an absence of transfer (i.e. a transfer has not not been performed). The FTRF-TSF flip-flop of this group indicates, when it is set to 1, that the previous instruction executed by processor 700 was a transfer type instruction and that the cycle I in progress to be executed is conditioned by the presence of 'a transfer initiation signal (TRGO) coming from the control unit 701.

In addition, the circuits of block 704-110 contain a certain number of flip-flops used to carry out operations of indirect addressing under control of the material for instructions other than EIS. We are dealing with FIS, FIRT,

FIRL and FRI which are set to 1 according to the different types of indirect address changes to be made.

For example, the FRI toggle signals a modification of register address then indirect and it is set to 1 when an indirect register indicator (RI) has the binary state 1. The FIR flip-flop is set to 1 when an indirect then register indicator (IR) has the binary state 1. This toggle signals the start of an address change (indirect then register).

The FIRL flip-flop is set to 1 when an indirect then indirect counting indicator ”(IT-1) is in binary state 1. This flip-flop signals a last indirect operation. Another TSX2 flip-flop provides an indication used in transfer processing and index setting instructions, while a STR-CPR flip-flop is used during processing of memory instructions.

As shown in FIG. 3 £, the output signals of the control indication flip-flops of block 704-110 are applied to the inputs of the connection indication circuits of block 701-1. Also, output signals from the control indication flip-flops are also applied to the inputs of the cycle I flip-flops of block 704-102.

Set of registers 704-150

As shown in FIG. 3c, the logic control unit 704-1 also comprises a set of registers 704 150. This set contains the primary instruction register (RBIR) 704-152, the secondary instruction register (RSIR) 704154, a basic pointer register A (RBASA) 704-155 used to select one of the RARO address registers in RAR7 of block 704-304, a register A of read index (RRDXA) 704-158 used for the selection of index registers intervening in the set 704-5 (not shown) and for the selection of outputs of the switch-multiplexer ZDO 704-340, an auxiliary read index register A (RRDXAS 704-159, and a descriptor type register (RTYP) 704-160 indicating the type of data characters which are defined by the value of the descriptor (for example 9 bits, 6-bit, 4-bit) .The 704-150 set also includes a 1-bit EIS instruction / descriptor register, designated by R29 in block 704-162. The state of this bit is used in cooperation with the content of register RBAS-A 704-158 to select the particular address register involved in address preparation. When the register R29 of block 704-162 is reset to ZERO, this indicates that none of the address registers of block 704-304 is used during the preparation of an address. The last registers of the set 704-150 include the data entry register (RDI) of the block 704-164 and a register B of read index (RRDXB) pointing to registers used by the execution unit. 714.

As shown in Figure 3, the RSIR register 704-152 is loaded via a two-position switch 740-170 connected to receive signals from the indicated sources (i.e., a ZIB-B switch 104172 and ZDI lines 0-35). The RSIR register 704-154 similarly receives signals from the ZDI lines and from the switch 704-172. The RBASA register 704-156 receives signals from the ZDI 0-2 line in addition to another ZBASA switch in block 704-174. The RRDXA register and the RTYP register receive signals from the ZDI lines and also from switches 704-176 and 704-178. Also, the RRDXA register receives signals from the RRDXAS 704-159 registers.

The switch 704-172 is a two-position switch which receives input signals from the switches ZIB and ZRESB connected respectively to the cache memory 750 and to the execution unit 714. The switch 704-174 is a switch to three inputs which receives two signals from the execution unit 714 and the output signal from the ZIB switch of the memory year 750.

Switch 704-176 is a four-input switch that receives two signals from thread 714 and a single signal from cache 750. The first position of switch ZRDXA 704-176 selects the output of a switch 704-185. A position of this switch receives an indicator area value from bit positions 5-8,

14-17, and 32-35 of the RBIR 704-152 register and bit positions 32-35 of the RSIR 704-154 register, the selection being made using the ZIDD switch 704-180 and a two-way switch positions ZMF 740-176.

The second position of switch 704-185 makes it possible to obtain a constant value from the output of the DHW output register 704-1 (zone CCM 32-34). The signals from lines ZIDD 27-35 are applied to the inputs of the command indication flip-flops in block 704-110. The switch 704-178 receives an input signal from the control memory 704-2, an input signal from the cache memory 750 and an input signal from the execution unit 714.

The data input register 704-164 receives a series of signals from a ZIDD switch 704-180 which is connected in series with a ZDIA switch 704-181 whose output signal is applied to an input of another switch 704-182 which allows direct loading of the RDI register 704-164 "The ZDIA switch 704-181 is itself connected to an input of a three-input switch 704-183 whose other inputs are linked to the cache memory 750 and execution unit 714.

The ZIDD switch 704-180 receives an effective address via the switch 704-186 from the address preparation unit 704-3 and it also receives input signals from the PBIR register 704-152, RSIR register 704-154 and a two-position switch ZMF 740-187.

Positions 18 to 35 of the REA position of switch 704-180 are connected to ZDIA switch 704-181, as shown in the figures. The ZDIA 704-181 switch receives signals from the ZDI 0-35 lines, a constant value established from the inputs in a first position of the switch in addition to the signals from the output of the ZIDD 704-80 switch and the ZRESB switch. of thread 714. Switch 704-182 receives the output signal from the ZDIA switch as well as signals transmitted by lines ZDI 0-35. The RRDXB register 704-189 is loaded by a three-position switch 704-188. This switch receives in a first position signals from a register RREG forming part of the execution unit, in a second position a constant value coming from the control memory 701-2 and in a third position signals coming of the ZIDD switch.

The assembly 704-150 further includes a two-position switch 704-185 and a memory-interpreter pointer register 704-186, the output of which is used by the AACU 722 to establish addresses allowing access to the interpreter memory of the EU 714 unit. The first position of the switch provides a constant value and is selected under the hardware control (FP0A.R29). The second switch position ensures the transmission On leaving the content of the RBASA register 704-156. This position is selected both under hardware control and microprogrammed control (ie FP0A.R29 or MISCREG area).

Note that the synchronization signals necessary to operate the unit 704 as well as other parts of the processor 700 and the cache memory 750 are provided by central clock circuits. For example, in the preferred embodiment shown in FIG. 1, the clock circuits are placed inside the input / output processor 200. These clock circuits can be considered to be of conventional design and can include a crystal controlled oscillator and counting circuits. The synchronization or clock signals supplied by such circuits are distributed in a conventional manner to the various parts of the system of FIG. 1 in order to obtain synchronized operation. Address preparation unit 704-3

The address preparation unit 704-3 includes a number of registers and adders. The registers include a number of base registers (i.e., TBASEO A TBASEB) that are part of block 704-300 and used to store instruction descriptor values, two temporary effective address registers (TEAO, TEA1) and two instruction counters (ICBA, ICBB) forming part of block 704-302 and used for addressing the instruction buffer and eight address registers (RARO A RAR7) of 704-304 used during address preparation operations. The 704-3 unit also includes an instruction counter 704-310.

The adders include an adder 704312 used for updating the instruction counter 704310 via switches 704-311 and 704-314, and two adders 704-320 and 704-322. The adder 704-322 is used to establish an effective address value which is stored in a register 704-342 and which is applied to an input of the control unit 704-1. The effective address is established from a certain number of sources which include the ZY switch 704-326, the output signal of which is transmitted via a number of AND gates of block 704-327, selected address registers from block 704-304 or selected temporary address registers TEAO and TEA1 from block 704-302 for transmission via another switch 704-328 or alternatively ZX0-20 index address from unit 704-5. In addition, the adder 704322 is used to update the content of the instruction counter of the instruction buffer of the cache memory.

As shown in Figure Sci, the output signals from the adder 704-322 are also applied to the inputs of the adder 704-320. The adder 704-320 is used to combine a base value stored in one of the temporary base registers TBASEO to TBASEB with the address signals ACS0S0-10 from the adder 704-322. The resulting bits are applied to the inputs of another adder circuit 704320 which generates a logic address, which is itself applied to the lines ASFA0-36 via an adder 704-321. This adder performs the summation of the incoming operands with the reports from blocks 704-300 and 704-320. The effective address is used to obtain an absolute address when the system operates in a page-by-page mode. Since this procedure does not fall within the scope of the present invention, it will not be described in more detail below. For further information concerning this addressing establishment, reference may be made to US Patent No. 3,976,978.

The temporary basic registers of block 704-300&gt; are loaded via a switch 704-322. This switch receives a signal from the execution unit 714 and the output signal from the block 704-300-, The execution unit 714 supplies other input signals to the registers of the block 704-302 by l via a switch 704-334 as well as the address registers of duBLoc 704-304. An output switch-multiplexer (ZDO) 704-340 validates the selection of the different registers placed in the address preparation unit 704-3 and in the unit 704-5 with a view to transferring their content to the unit 714 through ZDO lines 0-35. Also, the ZDO switch 704-340 allows the reading of the content of the various registers and flip-flops of control of the unit 704-1 via a fourth position (ZDO-A). The fifth position makes it possible to select for examination the states of the various indicators intervening in the control memory circuits of block 701-1.

Set of registers XAQ 704-5 and

Data address output set 704-4, Figures 3e and 3f

The set 704-5 contains the accumulation register RA 704150, the quotient register QA 704-52 and the temporary index register (RTX) 704-54 used by the logic control unit 704-1. In addition, it includes a group of eight index registers (XO-7) contained in block 704-51. These registers are loaded via the ZRESA bus of the execution unit 714. The selection of the register to to load is controlled by the contents of the register RRDXB 704-189. FIG. 3jf shows that the selection of the outputs of the registers of block 704-51 is controlled by the contents of the registers RRDXA 704-158 and RRDXB 704-189. The contents of the visible program registers RA, RQ, XO-7 and RTX are transferred to the unit 704-3 via a switch ZXA2

704-56, a ZXOB switch 704-57 and a ZX switch

705-58. Then, the contents of registers can be transferred to the execution unit 714 or to cache memory 750 by the intermediary. diary of the ZDO switch belonging to unit 704-3.

As shown in Figure 3_f, the output of switch XA2 704-56 is transmitted via an AND gate 704-61 and an OR gate 704-62 in accordance with the content of the RRDA register 704-158.

The selection of the outputs of the aforementioned switches is controlled by the content of the RRDXA register 704-158, of the FNUM flip-flop of block 704-104 and of the RTYP register 704-160 in addition to bits 55-77 (bits Z-). The ZXA2 switch 704-56 ensures the extraction of the 18 most significant or weak bits from the registers RA 704-50 and RQ 704-52 for a change of address. The selected output signals from the ZXA2 switch and the ZXOB switch are applied to the ZX switch together with the signals from the RAAU, RTX and RIO registers, as shown.

The ZX switch selects, as output, bits of the RA / RQ / X registers for a 9-bit character string via a first position, bits X / RA / RQ for a 6-bit character string via a second position, RA / RQ / X bits for a 4-bit character string via a third position and X / RA / RQ bits for a word modification.

A fifth, sixth and seventh position are used to select the contents of the RAAU register, the RIC register and the RTX register respectively. Another ZXB2 switch 704-59 establishes a second path to the unit 714 for reading the visible program registers via the ZEBO-35 lines. A similar route to unit 728 is established via lines ZAQO-35.

. Set 704-4 contains the registers and switches used to transfer commands and data to cache 750. Transfer operations of this kind normally require at least two cycles, namely at least one cycle for transmitting an address and another for transmitting data. Bits 5 to 8 of an instruction word or control are derived from the output of a four position switch 704-40. This switch receives a first constant value via a first position, the content of a register RZN 704-42 via a second position, a second constant value via a third position and a third constant value via a fourth position.

Bits 1 to 4 of an instruction are transmitted by the circuits of block 704-1 to an OR gate 704-44 at the same time as bits 5 to 8. The OR gate 704-44 also receives ^ via d 'a ZADO 704-46 switch, bits 1 to 8 of a RADO 704-48 register. The RADO register 704-48 is an address and data output register which receives, via a first position of a ZADOB switch 704-48 a logical (virtual) address originating from the preparation unit address 704-3 via the lines

ASFAO-35 as well as data output signals from the EU 714 unit via the ZRESBO-35 lines.

The positions of the ZADOB 704-48 switch are under the control of the FMTD zone for a small CU format and the RADO zone for a large CU format.

As shown in the figure, the ZZN1-8 bits or the ZADO 1-8 bits are applied to the RADO / ZADO lines according to the state of the control signal £ rAD0-ZAD0. Bits 0 and 1 are always in the binary UN state while bits 10 to 35 are supplied by the RADO register 704-46.

In addition, the unit 704-5 of the preferred embodiment includes a four-position ZREG selector switch 704-53 which is controlled by coding the CCSR area.

The output of the ZREG switch is used to load the RREG register 714-42 with constant values ​​or with signals corresponding to bit positions 24-26 of the RBIR 704-152 register. During a following cycle, signals corresponding to the content of the RREG register 714-42 are transferred to the register RRDXB 704-189. In the case of instructions which relate to instructions specifying co30 of the reference CCS falling into the classes STR-SGL on STR-DEL, the same signals are transferred in the register RRDXA 704-158. In addition, the contents of the RREG register 714-42 can be loaded into the RBASA register 704-156 under the microprogrammed command.

Execution unit 714 - Figure 3 ^

The unit 714 comprises / main elements of the groups of temporary registers or addressable maneuvers 714-10 and 714-12, an arithmetic logic unit (ALU) .714-20, a shift circuit 714-24 and an interpreter memory 714- 30. In addition, the unit 714 includes a number of multi-position data selector switches 714-15, 714-17, 714-22, 714-26, 714-28, 714-34, 714-36 and 714- 38 so as to obtain flexibility in the selection of operands and output results.

In service, the operands are selected by the intermediary of the ZOPA switch 714-15 and the ZOPB switch 714-17 from one of the registers of groups 714-12 and 714-10 or from other lines of input such as ZEBQ - 35 or RD10-35 as shown in the figure. The ALU 714-20 and the fired cir15 with offset 714-24 carry out the operations on the selected operands and the results are chosen via the switches 714-24, 714-36 and 714-38 in order to be applied to the ZRESA 0-35 and ZRESB0-35 output bus lines. Likewise, the contents of an interpreter memory location selected through the contents of an interpreter buffer 714-32 can be retrieved via switches 714-34, 714-36 and 714-38.

The selected results or other data are then loaded into other registers located in the processor 700, in particular the groups of temporary registers 714-12 and 714-10 or else the interpreter memory 714-30 of the execution unit 714.

For more precision, the sources of operands are identical for the two switches ZOPA 714-15 and ZOPB 714-17.

The positions of the ZOPA and ZOPB switches are selected under the control of bits 9-12 and bits 13-16 of the half-instruction word. The ALU 714-20 unit performs logical, decimal or linear operations on the operand data selected under the control of bits 24-28 of the microinstruction word of FIG. 6a_.

The shift circuit 714-24 is constituted by a logic network used to align, shift or scroll through binary data under microprogrammed command. The data signals from the ZSHFOP 714-28 and ZEIS 714-22 switches can be considered to be combined to form a single double input word. The shift circuit 714-24 provides 36 bits at output which are shifted according to the shift count. The ZSHFOP switch 714-28 is controlled by bits 24-25 of the microinstruction word while the shift count is defined by the sequence control constant zones (bits 138-143 of the microinstruction word of FIG. 6a_ which is appropriately selected via the auxiliary arithmetic control unit 722). The units 714-20 and 714-24 can be considered to be of a conventional design.

The interpreter memory 14-30 establishes a workspace for storing different data necessary for the execution of certain instructions as well as different constants and values ​​of descriptors. For example, octal positions 10-15 are used to store a formatting instruction table value necessary to perform formatting operations. A write in the interpreter memory 714-30 involves a first loading of the RSPB buffer register 714-32 with input data transmitted by means of the ZRESB switch 714-38. During a following cycle, the content of register 714-32 is introduced into the location specified by the signals applied to lines ZPSPA 0-6 by the unit AACU 722. Writing occurs when bit 22 of the microinstruction instruction (ZONE RSP) is set to 1.

For the other switches mentioned above, the results produced by the 714 unit are transmitted via the ZALU switch 714-26, the BSPDI switch 714-34, the ZRESA switch 714-36 and the ZRESB switch under microprogrammed control. The ZALU and ZSPDI switches establish a first level of selection for the ZRESA and SRESB switches which establish a last level of selection. Since the two switches ZRESA and ZRESB have identical input sources, they can provide the same output data. ZALU switch data selection is performed under the command of bits 30-31 (ZALU area) while ZSPDI data selection is performed under the control of bit 23 (area

ZSPDI). The selection of data ZRESA and RRESB is carried out respectively under the control of bits 17-18 and bits 19-20 of the microinstruction word of FIG. 6a.

The registers of groups 714-12 and 714-10 are addressed independently by bits 3-5 (TRL area) and bits 6-8 (TRH area) respectively. The first bit of each area specifies whether one of the four registers should be addressed while the other two bits select the register to be addressed. Finally, the four-position switch 714-40 is used to load an RREG register 714-42 with constant values ​​or signals corresponding to bit locations 24-26 of the RBIR register 704-152.

Character unit 720 - Figure 3h

We see that the unit 720 includes a group of 4 registers 720-10, a certain number of registers 720-22, 720-24,720-28, 720-30, 720-42, 720-46, 720-54, 720- 63, 720-64,720-68 and 720-70, 720-27 conversion logic circuits, 720-32 and 720-34 adder networks, a 720-72 comparator network and a number of decoder / detector networks 720-36, 720-38 720-44, 720-48, 720-50, 720-56, 720-58 and 720-74 interconnected by a number of multi-position selector switches 720-26, 720-40, 720-62, 720-12 up to 720-20. The control and selection of the switches and the sampling of the different registers are carried out under the control of a certain number of flip-flops intervening in the block 720-80 and of two zero detector circuits 720-82 and 720-84.

The registers 720-10 of the RCH group are used as buffer registers of operands so as to store information received from ED 714 via the lines ZRESA 0-35. A first register (0P1) is used to store the operand specified by descriptor 1 or a data item addressed to the unit 728 or to the unit 722. A second register (0P2) is used to store the operand specified by the descriptor 2. The third and fourth registers (TABLE ENTRY 1, TABLE ENTRY 2) are used to store table entry values ​​from EU 714.

The RCNI register 720-28 contains the actual character position data for descriptor 1 which is used to select a character to be selected by the ZCU switch 7-12. The register RCN2 720-30 contains signals defining the character position data of descriptor 2. The story2425110

91.

Bare registers are used to select a character from the 720-14 switch.

The ZCU 720-16 and ZCV 720-18 switches are controlled by the ZCU and ZCV flip-flops in block 720-80. The registers

RCN 1 and RCN 2, designated by 720-28, are loaded under the control of flip-flops CN1 and CN2 of block 720-80 in response to signals generated by the decoder 720-56. This operation is performed according to the type of characters (4, 6 or 9 bit characters) defined by the contents of registers RTF1 720-42 and

RTF2 720-46 and by the initial character position signals generated by the logic conversion circuits of block 720-27. The circuits in block 720-27 convert signals ZCN0-2 applied via the switch 720-26 in correspondence from a character input position to a character output position. For characters .. at 9 bits, there is no need to convert (i.e. the character input position corresponds to the character output position).

The two-bit RFTI register 720-42 contains the character type information relating to descriptor 1 while the two-bit register RTF2 720-46 contains the character type information corresponding to descriptor 2. The RTF3 register 720-52 at 1 bit contains the character type information corresponding to descriptor 3. When descriptor 3 consists of 9-bit characters, the detector 720-50 sets the register RTF3 to 1. In all other cases, the RTF3 register is set to 0. As shown in the figure, these registers are loaded via the switch 720-40, ·

The five-bit RMOP register 720-70 stores the micro-operation values ​​'' necessary for processing a formatting instruction, while the four-bit RIF register 720-63 stores the information area values ​​( IF) for said instructions. The 9-bit RCD 720-64 register is used during certain instruction comparison operations to store a first operand value. The 5-bit register RTE8 720-68 stores the 5 most significant bits of the eighth shaping insertion table input value in response to a loading signal generated by the decoder 720-74 in response to a loading command. The register REFÎLL 720-22 is used to store signals from the unit 704-150 via the lines ZIDD 0-8. RAD register 720-24 stores character position bits from unit 704-3 via ASFA lines 34-36.

The indicator flip-flops of block 720-80 store the result of an operation specified by the content of the RMOP register 720-70. The flags include a 2-bit MOP flag (ΜΟΡΙΑ), a 3-bit MOP B flag (MOPIB) and a 1-bit END flag. The indicators ΜΟΡΙΑ are decoded as follows:

go to the MOP execution operation go to the LOAD MOP operation MOPIB control

N / A '

The MOPIB indicators provide an additional state when the ΜΟΡΙΑ indicators have the value ”10. They are decoded as follows:

000 checks the status of a length 1 indicator for a negative overflow (LlüDF set to 1 when the output signal from the AXP adder equals 0 means that Ll is finished) and the status of the indicator Positive capacity overrun CNI (OVF CNI).

001 checks the state of a length 3 indicator for a negative capacity overflow (L3UDF set to 1 when the output signal from the adder AL is equal to 0 means that L3 is finished) and the state of the indicator CN3 positive overflow (CNLOVF) which is set to 1 when the output of the AP adder is equal to 0.

010 checks the states of the LIUDF, CN10VF, L3UDF and CN3QYF indicators.

011 reduces the value of length 2 by 1 and checks the states of the L3UQF and CN30VF indicators during a first cycle and checks the states of a length 2 negative overflow indicator (L2UDF) and the CN20VF indicator during a second cycle.

100 controls the states of the L3UDF indicators_} CN30VF, LlUDF and CN10VF during a first cycle. Transfers the contents of the RAAU register to EU 714, decreases the value of length 3 by 1 and increases the value of CN3 by 1 during a second cycle. During a third cycle, check the states of the L3UDF and CN30VF indicators.

101 loads the table entry value.

110 changes table values.

111 N / A.

The END flag is set to one to indicate that the operation specified by the MOP value is complete.

Arithmetic and auxiliary control unit (AACU) 722 Figure 3i

The AACU 722 unit comprises three parallel adding networks 722-2, 722-6 and 722-8 designed respectively as a pointer adding network, an exponent adding network and a length adding network . The pointer adding network 722-2 includes two groups of 4 registers (RP0-RP3 and RP4-RP7) 722-20 and 722-22. Each group has its own multi-position switch (722-23 and 722-24) for selecting the data to be written and a pair of four-position output switches for selecting the data to be extracted (i.e., switches 722-27, 722-28, and 722-29,722-30).

In addition, group 722-20 includes a second input switch 722-32, the output of which powers the ZRPA switch 722-23 and ensures the selection of additional input data.

ZRPC switch 722-32, ZRPA switch 72223 and register group 722-20 are jointly controlled by bits 64-68 (ZRPAC area), bits 69-71 (ZRpAC-3 area) or bit 67 (area ZRPAC-4) depending on the microinstruction format. The ZRPA 722-23 switch can select one of the outputs of the ZRPC 722-32 switch via a first position, a load value of a charac offset 2425110

1st for address modification / address loading instructions in register for the character unit 720 via a second position and a character pointer value for a 9-bit character via d 'a third position.

The ZPA switch 722-27 and the ZPB switch 722-28 select data from the register group RPORP3 722-20 under the control of bits 59-60 (ZPA) and bits 6162 (ZPB). The ZRPB switch 722-24 and the register group 722-22 are jointly controlled by a single control area according to the / fcype of the microinstruction format, namely by bits 74-78 (ZRPB-O) of bits 69- 73 (ZRPB), bits 72-74 (ZRPB-3) or bit 68 (ZRPB-4). The ZRPB switch 722-4 can select the output of the adder output switch 722-36 via a first-position, an information area from the character unit 720 via a second position, a word or character pointer value for a 9-bit character via a third position and a character pointer value for a 9-bit character via a fourth and from a fifth position.

ZFC switch 722-29 and ZPD switch 722-30 select data from register group RP4RP7 722-23 under the control of bits 57-58 (ZPC area) and bits 67-68 (ZPD area). As shown in Figure 3, the outputs of switches 722-27 to 722-30 are applied to the operand switches A and B 722-25 and 722-26. The outputs of the switches are passed to a pointer adder 722-34.

The switch ΖΑΡΑ 722-25, the ZAPB switch 722-26 and the adder 722-34 are controlled jointly by a single control zone, namely by bits 79-84 (zone AP) or bits 82-83 (zone AP-3), depending on the microinstruction format. As shown in the figure, switches ΖΑΡΑ 722-25 and ZAPB 722-26 select outputs from switches ZPA, ZPC, ZPB or ZPD or else a constant value for application; to the adder 722-34.

An XLX 722-36 switch, a ZXC 722-38 switch, an RSC 722-40 register and a ZRSC 722-42 switch operating under microprogrammed control are arranged to provide offset counts to the unit shift circuit of execution. The ZCC 722-38 switch can also be used to load data into the RPO-RP3 722-20 register group via the ZRPC 722-32 and ZRPA 722-23 switches or in the RP4-RP7 register group. 722-23 via the ZRPB switch 722-24.

The selection of the positions of the ZLX switch is controlled by bits 48-49 (ZLX area). The ZSC 72238 switch is used to select one of the outputs of the ZLX 722-38 switch or to control bits 50-62 (ZSC area). The RSC 722-40 register is loaded with the 6 most significant right bits from the output of the ZLX 722-38 switch, under the command of bit 47 (RSC area). The two-position ZRSC switch 722-42 selects which of the two sources must supply an offset account to the execution unit 714. Bit 84 (zone ZRSC) selects either bits 138-14 3 (zone CNSTU / L), i.e. register RSC 722-40 as the source of the shift account.

The last group of circuits shown in block 722-2 includes a ZAAU switch 722-44 and a RAAU register 722-46 which are connected to receive the output signals from switch 722-44. The ZAAU switch 722-44 is used to transmit data to the register 722-46. From this register, the data is transferred via the assembly 704-5 to the execution unit 714 at the using lines ZRB 0—35.

The inputs of switch ZAAU 722-44 are selected using bits 50-52 (zone ZAAU). The first position of the switch applies a 9-bit character from character unit 720 via lines ZOC 0-8. The second and third positions are used to separate the outputs of the length adder and the exponent adders from blocks 722-6 and 722-8. The RAAU register 722-46 is loaded from the ZAAU switch 722-44 in response to bit 47 (RAAU area).

2425110 i

As shown in the figure, the 722-6 exponent adding network includes a single group of 4 registers (RXPARXPD). The .722-60 group includes a multi-position switch 722-62 for selecting the data to be written as well as a pair of four-position output switches for selecting the data to be read (i.e. switches 722-64 and 722-66). Switch ZXP 722-62 and register group RXPA-RXPD 722-60 are controlled by bits 59-62 (zone ZXP), bits 65-66 (zone ZXP-1) or bits 75-77 (zone ZXP -3).

A first position of the ZXP switch 722-62 is used to load the exponent result in the register group 722-60. The second position is used to store the result from the length adder 722-8. The third position is used to store values ​​of exponents received from the character unit 720. Finally, the fourth position is used to store digital scaling factor information from the RSIR 24-35 lines.

ZXPL switch 722-64 and ZXPR switch 72266 select data from register group 722-60 under the control of bits 63-64 (area ZXPL) or bit 64 (area ZXPL-1) and bits 65-66 (zone ZXPR) respectively. The output signals of switches 722-64 and 722-66 are applied respectively to an operand switch A 722-66 and to one. operand switch B 722-70. These switches apply selected inputs to two 12-bit adders (AXP and AXM) from block 722-72 which produces an exponent value at its output, which is passed to an output ZAXP switch 722-74. A single AXP control zone (bits 69-73) controls the operation of the ZXPA 722-68 switch, the ZXPB 722-70 switch, the adders, the ZAXP 722-74 switch and the loading of a RE 72276 register.

An AXM adder is arranged to receive the contents of the RE 722-76 register to supply an absolute value when the sign of an absolute value generated by the AXP adder is negative (i.e. the indicator of AXP sign, not shown, controls the selection of the ZAXP switch).

The ZXPA 722-68 switch can select the contents of the RE 722-76 register via a first position or the output of the ZXPL 722-64 switch via a second position. The ZXPB 722-70 switch can select a constant value through a first position, through a second position of binary floating point exponent signals which are applied to RDI lines 0-7, via a third position, a digital scaling factor value applied to the RSIR 24-35 lines, via a fourth position the output of the ZXPR 722-66 switch and via a fifth position the output of the ZLNA 722-84 switch.

The third adder network 722-8 used to provide an operand length data, in a similar manner to the network 722-6, comprises a single group of 4 registers (RLN1-RLN4). Group 722-80 includes a multi-position switch 722-82 to select the data to be written and two four-position output switches to select the data at life (i.e. switches 722-84 and 722- 86). Switch ZLN 722-82 and register group RLN1-RLN4 722-80 are controlled by bits 59-63 (zone ZLN-1), bit 63 (zone ZLN-2), 'bits 79-81 (zone ZLN-3) or bits 79-83 (zone ZLN-4) depending on the microinstruction format.

The switch ZLN 722-82 transmits the output signal of the length adder via a first position, the output signal of the switch ZAXP 722-74 via a second position and a value of length zone coming from RSER 24-35 lines via a third position.In addition, it provides a numeric length zone value coming from RSTR 30-35 lines via a fourth position, an offset count value from RDI lines 11-17 through a fifth position and a length value from RCH lines 24-35 through a sixth position, all of which are applied to group registers 722-80.

ZLNA switches 722-84 and ZLNB 722-86 select data from register group 722-80 under the control of bits 53-54 (ZLNA area) and bits 55-56 (ZLNB area)

242511Θ in order to transmit them respectively to an operand switch A 722-88 and to an operand switch B 722-90.

The output signals from these switches are passed to a 12-bit length adder AL 722-92. The ZALA switch 722-88, the ZALB switch 722-90 and the adder AL 722-92 are all controlled by bits 74-78 (area AL). The ZALA 722-88 switch selects as an operand the output signal of the ZLNA switch via a first position, a constant zone via a second position, the output signal of the ZPC switch via the through a third position and a numeric length area through a fourth position.

The switch ZALB 722-90 can select as operand a constant zone via a first position, the output signal from the switch ZLNB 722-86 via a second position, the output signal from the ZXPL switch through a third position, · an offset count value from RDI lines 11-17 through a fourth position, the output signal of the ZPC switch through a fifth position, the output signal of the ZPA switch via a sixth position and the positions of bits 6 and 7 of the ZPC switch 722-29 through a seventh position.

Unit 722 contains another group of circuits for providing an interpreter memory address to unit 714. The circuits include a ZSPA 722-100 switch, an RSPA 722-102 register, and a ZRSPA 722-104 switch which are each controlled by bits 48-49 (ZSPA area), bit 47 (RSPA area) and bits 50-52 (ZRSPA area). The ZSPA switch 722-100 can select as output bits 91-97 corresponding to a memory address area interpreter via a first position, and the output of the pointer adder 722-44 through l 'through a second position.

The ZRSPA switch 722-104 can select as output the content of the register 722-102 via a first position, a memory address area interpreter via a second position and a description value coming from RSIR 32-35 lines via a third position troi2425110 as well as a value from the RSPR register of unit 704-150 via a fourth position. In addition, the unit 722 has two registers 722-106 and 722-108 which receive signals corresponding to bit positions 215 23 of the RSIR register 704-154. A register is loaded when the bit of the microinstruction word of FIG. 6b or else the flip-flop FPOP are in binary state 1. The registers are selected for a loading according to the states of the register RDES 704-140 (00 or 10 = RlXW; 011 = R2DW).

The different zone control signals used by the AÂCU 722 unit are supplied by a decoder 722-110 which receives at its inputs the different microinstruction word bits which have been loaded into a register 722-112.

ANTEMEMORY 750 - Figure 4

General description

The 750 cache is divided into five main sets: a 750 - 1 command buffer set, a 750-3 control set, a 750-5 cache directory set, a 750-7 cache memory set, and a instruction buffer set 750-9.

750-1 control pad assembly

The 750-1 control buffer assembly includes a 750-100 four-word write control buffer and a 750-102 four-word read control buffer which are addressed through the 750-104 and 750 counters. -106. The ZAC 750-100 write buffer stores one ZAC write command while the ZAC 750-102 read buffer stores four ZAC read commands.

The processor 700 transfers the commands via the intermediate 30 of the RADO / ZADO lines of the interface 605 by bringing into play the first position of a selector switch 750-110. Processor 700 transfers cache control information via the DMEM and DSZ lines by involving the first position of a selector switch 750-112. The states of said lines are stored in a register 750-114. As the figure shows, this information is also stored in buffers 750-100 and 750-102.

100

In addition to transferring the cache control signals, the processor 700 puts a DREQCAC line to one. The processor 700 also puts on one of the other command lines (for example HOLD-C-CU, CANCEL-C, CACFLUSH, BYBASS-CAC, READ IBUF,

READ EVEN) when it wants the 750 cache to perform other types of operations.

The states of the other control lines are decoded by a 750-116 decoder, the output signals of which are used to validate the ZAC buffers 750-100 and 750-102. In addition, the processor 700 transmits zone bit signals for certain types of write commands via DZDO-3 lines. These signals are loaded into an RDZD 750-132 register via a 750-134 switch. The contents of this register are then transmitted via a 750-136 switch to a series of CBYSEL by-byte lines. In addition, the signals applied to the DZO lines are transmitted to the MITS lines via a switch 750-139. Other zone signals (bits 5-8) are loaded into an RC address register 750140 and then they are applied to another series of CBYSEL byte selection lines via a switch 750142.

Several occupied bit registers 750-120 and 750-122 are used to determine the locations available in the RZAC buffer 750-102. The states of these registers are decoded via a priority decoder network 750-130 which selects the first available location in the buffer. The value obtained is stored in register 750-106 and is used as a write address for the read buffer ZAC 750-102. When the cache request involves an extraction in auxiliary memory (MEM memory) (absence of cache signaled by the status of a BSPC signal), the corresponding occupied bit or else the two occupied bits are set to a match with the number of SIU responses (ARDA signals) that have been produced. The occupied bits are set to one by signals applied to two lines SETBOTHBSY and SETONEBSY by a decoder, not shown, which decodes the particular command resulting in the application of a signal to one of the lines BSY. For example, a single read command - without bypass - produces two

101 SIU ARDA responses, each response occurring in a pair of words. As a result, two busy bits are set to one. In the case of a single read bypass command, a single SIU ARDA response is produced. As a result, a single busy bit is set to one. The occupied bits are reset to zero in response to the ARDA signal and via an RSPB register 750-124 which receives signals from the SIU 100 unit via the RMIFS lines.

In more detail, the contents of the registers

750-120 and 750-122 are set to match the ARDA response number when a PENBÏT signal has the binary state UN (i.e., when the bit corresponding to the block is not set ).

The decoder circuit 750-130 decodes the states of the occupied bits and passes the counter register 750-106 to the value of address15 appropriates specifying the next empty location in the read buffer RZAC 750-102,

The same PRACWO-1 address signals are also applied to a second position of switch 750-139 in the case of read commands. Then the signals are loaded into a 4-bit MITS 750-138 register and applied to the MITS lines. The main memory 800 ensures the return of the coded signals in the cache memory 750 via the MIFS lines during the transfer of the requested pairs of data words of a block. Then the signals are loaded into a register

RMIFS 750-125 at 4 bits then in the register RSPB 750-124 when the command status signal THCEFD has the binary state 1. The value received produces a reset to the appropriate occupied bit indications stored in the registers 75G -120 and 750-122,

Note that bit signals 2 and 3 RMIF are used to address the read buffer RZAC 750-102 for the extraction of the appropriate command. In addition, signals from a pointer output circuit (COUT), not shown, are used to access commands stored in the ZAC 750-102 read buffer. The occupied bit indications stored in registers 750-124 and 750-126 are applied to exclusive OR circuits of block 750-132. These circuits are used to produce signals indicating the number of bits occupied.

102

These signals are in turn applied to positions other than a 4-position selector switch 750-133. By selecting the appropriate position, in response to bit signals 2 and 3 RMIES, the switch 750-133 provides at its output a signal SECRCV whose state determines when cache memory 750 has received the second pair of words from a block. The SECRCV signal is applied to block 750-3.

The outputs of the ZAC 750-100 write buffer and the 750-102 read buffer are applied to different two-position switches of a group 750-150, 750-152, 750-154, 750-156 and 750-158 . The output of the ZAC 750-150 buffer switch is loaded into an SIU 750-174 output register via switches 750-170 and 750-172. The output of the ZAC switch 750-152 is loaded into two data registers 750-180 via the switches 750-177 and 750-178.

The outputs of switches 750-154 and 750-158 are applied to another switch 750-160 and are stored in a memory register 750-162. The output of the 750-156 switch is applied to a 750-156 decoder at the same time as the DEM outputs of the 750-160 switch. The other outputs of this switch are applied to a 750-168 decoder. In addition, the output of com = mutateur 750-158 is applied to a 750-164 decoder.

The 750-166 decoder decodes the cache commands from processor 700 through the DMEMO-3 lines as well as commands from buffers 750-100 and 750-102 and produces signals used to transfer commands to the cache memory 750-7 and in directory 7505. Thus, the cache decoder 750-166 is used to control the information to be written to the cache memory 750-7 from processor 700. The 750-168 decoder decodes the states of the BYPAC and DSZ1 signals. It should be noted that the source of the signals mentioned last corresponds to the processor 700 or to the switch 750-154.

The 750-164 decoder decodes the commands extracted from buffers 750-100 and 750-102 and produces signals used to transfer these commands to a memory MEM (auxiliary memory) via the SIU 100 unit. decoder S 750164 is used to control the transmission of information from the control buffers 750-100 and 750-102 and to the SIU.

103

In addition, the ZPSW switch 750-178 selects, via a first position, the ZAC command originating from the processor 700 via the RADO / ZADO lines with a view to its transfer to the SIU 100 unit by the DTS lines and via the switch 750-172, or it writes the main memory data to the cache memory 750-7, via the data registers RDOjRDI 7_50-180. The second position of the switch ZPSVf 750178 transmits the data coming from the switch ZALT 750-177 to the lines DTS (ZAC data) or else it writes the data of main memory coming from the lines D, FS in the cache memory 750-7 through RDO registers,

RDI 750-180, or else it transfers ZAC commands to processor 700 via the ZDI lines.

The ZACSW2 J750-170 switch is used to transfer a ZAC command (first position) or data from the ZAC buffer into the SIU 100 unit via the DTS lines (second position).

750-3 control assembly

This set includes a number of command state flip-flops which produce signals for sequencing the cache memory 750 to execute the necessary cycles of processing the various commands. In addition, the assembly contains the logic circuits necessary to generate the necessary control signals during the necessary operating cycles. In the context of the present invention, these circuits can be arranged in a conventional manner. Consequently, to simplify the description of the system, only a brief description and the Boolean expressions corresponding to certain logic control circuits and certain control state flip-flops will be given insofar as this is necessary for understanding the operation of the present invention.

The command state flip-flops produce a series of synchronization sequences which control the following data transfer sequences:

(1) processor to cache, SIU (operation on cache and on SIU);

(2) processor to SIU (transfer of write data to SIU)

104 (3) ZACBUF to cache memory (operation on cache memory);

(4) ZACBUF to SIU (operation on SIU);

(5) processor to ZACBUF (writing of con5 data served in buffer);

(6) SIU to cache memory, processor (2 words transferred);

(7) SIU to cache memory, processor (1 word transferred).

The transfers involve the following flip-flops: Command status flip-flops

The OATB flip-flop is the first flip-flop involved in a first sequence which allows information transfer between the SIU 100 unit and the cache memory 750 and the processor.

750. __

The CATB flip-flop is set to one for a cycle in accordance with the following Boolean expression: ARDA. DPFS,

The THCFD flip-flop is the next flip-flop which is set to one in the first sequence in order to allow the information received during the OATB cycle originating from the SIU unit 100 to be transferred to the processor 700 via the intermediary ZDI lines. The THCFD flip-flop is set to one during a cycle in accordance with the following Boolean expression:

UPDATE: OETF = ARDA.DPFS.

»

The UG COGTH flip-flop, when set to one, allows the setting of 1 / reset to 0 of an F / F bit, the setting of a pending bit, the setting of an RR bit, l writing MSA to the address of the directory set, and writing data from a simple write command to the cache memory. It is set to one and reset to zero in accordance with the following Boolean expressions:

HOLD. SET-COGTH

UPDATE

RESET (HOLD): CAC-BSYL „NO-HOLDCÂC. CACBSYL + NO-HOLD-CAC

105

The UGSOGTH flip-flop is the first flip-flop set in a CPU to SIU sequence. When set to one, a first data word is applied to the DTS lines. It is set to one during a cycle in accordance with the following Boolean expression:

SET TO ONE: HOLD. DWRT when DWRT = CWRT.

SNG + CÏÏRT. DBL + CWRT.RMT.

The CAOPR flip-flop is set to one in response to the reading of an AOPR response. It is set to one during a cycle in accordance with the following Boolean expressions:

UPDATE: SSET-IN. CLD-IBUF (CBYP-CAC +

BPSp) + CPR-RD. CBYP-CAC.BPSD + (CRD-SNG + CRD-DBL). (CBYP-CAC + BPSD) + CRD-CLR + CRD-RMT + CWRTSNG + CWRT-DBL + CWRT-RMT.

The CPR-FF toggle is used to determine when the cache responds to a DREQ-CAC signal from processor 700. When this toggle is set to 1 during a previous cycle, the cache does not respond to a request except in cases from PREREAD, INST-F1, INST-F2, LDQUAD, RD-SINGLE or RD-IBL type commands. It is set to and reset to 0 in accordance with the following Boolean expressions:

UPDATE (CINST-F1 + CINST-F2 + CLD. QUAD + CRD. DBL + CRD. S.ng). (CBYP. CAC + BPSD) / CPR-RD. CBYPREMISE A ZERO

HOLD = RD-BSY.

The RBPSD base is used to switch off the processor 700 in the eas of a HOLD-ON MISS or ΒΥΡ-CAC condition. When the data returns from the SIU 100 unit, this flip-flop is reset except for an INST-F1 cycle.

In the case of IF-1, after reception of 4 words coming from SIU, this rocker is reset to 0. It is set to 1 and reset to 0 in accordance with the following Boolean expressions:

UPDATE: SSET-IN. HOLD-CAN.CRP-RMT + CRDCLR + (CINST-F1 + CRD-SNG + CRD-DBL). (CBYP-CAC + .8PSD)

RESET: (HOLD) = THCFD.SEC-RCV.CINSTFl + DATA-RECOV.INST-F1-FF.

106

The ZC-DL flip-flop is the first binary ONE to trigger a ZAC buffer synchronization sequence with respect to the cache memory. This toggle remains at one until all requests requiring the completion of such sequences are processed. It is reset and reset according to the following Boolean expressions:

UPDATE: SSET-ÎN. PENBIT + UGCOGTH. CAC-BSY-1 + PRE-OK. CAC-BSY ?! + TLTHM. CAC-BSY'l RESET: HOLD = HOLD-CAC + CAC-BSY-1 +

PREOK + UGTLTHM + PENBIT - WAIT.

The PRE-OK toggle is the first binary ONE during the ZAC buffer synchronization sequence with respect to the cache. It is reset and reset according to the following Boolean expressions:

UPDATE _: ZC-DL. HOLD-CAC. CAC-BSY-1.PRE.0.

OK. TLTHM. PENBIT-WAIT. THAT ~

RESET ; H0LD = HOLD-CAC.CAC-BSY1.

The UGOK flip-flop is the second binary ONE during the ZAC buffer synchronization sequence with respect to the cache memory. This toggle validates operations similar to those performed during a DREQ-CAC cycle. It is reset and reset according to the following Boolean expressions:

SET TO ONE: PRE-OK. CAC-BSYl .. HOLD-CAC

RESET J HOLD = HOLD-CAC.CAC-BSYl.

The PENBIT-WAIT flip-flop is set to ONE binary when a so-called read request specifies the same address as a previous request for which the data set was not received from the main memory. It is reset and reset according to the following Boolean expressions:

107

UPDATE: SSET-IN. PENBIT

AZERO DISCOUNT: HOLD = RDBSY.

The PENBIT-EF flip-flop is set to ONE binary in response to a single read or double read request specifying the address of a previous read request whose data has not been received from main memory. This switch is used to stop the operation of the processing unit. It is reset and reset according to the following Boolean expressions:

UPDATE

RESET

SSET-IN. PENBIT. (CRD-DBL + CRD-SNG)

HOLD = PRE-OK + HOLD-CAC + CAC-BSY-1.

The TLTHM flip-flop is the third binary ONE during the ZAC buffer synchronization sequence with respect to the cache memory. This flip-flop is set to one in response to a double read command following an OK operation cycle. It is reset and reset according to the following Boolean expressions:

UPDATE

RESET: 0K.CAC-BSY1. (BPSD + CRD-DBL); HOLD = HOLD-CAC. CAC-BSY1.

The FRE-DBL flip-flop is used to establish a TLTHM synchronization cycle. When CAC-BSY1 is forced to ONE binary during the TLTHM cycle, a ZDBL-FF flip-flop is set to one by the FRD-DBL flip-flop in the case of a double read command. This allows the cache unit to stop the operation of the processing unit when it is disabled to transmit a second word to the processing unit during the TLTHM cycle. The IRD-DBL flip-flop is set to one during a cycle in accordance with the following Boolean expression *:

UPDATE: CRD-DBL.

108

- LOGIC ORDER SIGNALS

1. The CPSTOP signal is the signal used to switch off processor 700.

CPSTOP = FBPSD = REQ CAC. [rDTYP. RZAC-ALL-BSY + PRFF. (PR + RD + INST-F2 + LDQüAD + RD-SNG + RD-DBL) + CAC-BSYl + CAOPR + UGGOGTHj + RBSSD + DBL.FF + PENBIT.FF-f (RD-IBUF / ZDI.CAC-BSY- 1) t (RD-IBUF / ZDI.

LD-QUAC-FF) + (UGCOGTH. RD-DBL. CAC-BSY i).

2. The CAC-BSYl signal indicates when the cache memory is occupied. CAC-BSYl = 0ATB4THCFD.

3. The signal [SF / E-WRT is a write validation signal used to set to 1 and reset to 0 the full / empty bits -_ [SF / E-WRT = CAC.BSYl. (UGCOGTH) .UGSOGTH.RD-DBL.BYP-CAC

DLY-BPSD. (INST-F2 + LD-QUAD) .BYP-CAC-DLY.BPSD.

4. The signal [SPENl-ffRT is a write enable signal used to set the pending operation bits to one.

[SPENI-WRT = CAC-BSY 1. (UGCOGTH). 4INS T-F2-Î-LD-QUAD + PR-RD-h

RD-SNG.DLY-BPSD + RD.DBL.DLŸ-BPSD).

!

5. The signal (SPEN2-HRT is a write validation signal used to reset the pending bits to O when all the data associated with a request have been received from the main memory [SPEN2-WRT = THCFD.SEC-RCV . (INST-F2 + LD-QUADrPR-RD + RD-SNG +

RD-DBL.BYP-CAC).

6. The signal RZAC-ALL-BSY indicates the occupied state of the RZAC buffer established in accordance with the states of the occupied bits.

RZAC-ALL-BSY = (RB3-00 + RBB-01). (RBB-10 + RBB-11).

(RBB-20 + RBB-21). (RBB-30 + RBB-31).

7. The SRMIFS signal is a write sampling signal that enables. Multiple door identification hits to be stored when data or status information is received from the main memory. These bits identify the location of the RZAC buffer which contains the word ZAC associated with the data received (that is to say the data belonging to several possible requests for readings),

109

SRMIFS = ARDA + AST.

8. The ALTSWO-DT signal validates incoming data from the main memory to be stored in the RDO and RDI registers.

ALTSWO-DT = CAC-BSY 1.

9. The ALTSW2-DT signal allows data from the ZAC buffer to be transferred to the RDO and RDI registers.

ALTSW2-DT = DS-ALT + ALTSWO-DT;

where DS-ALT = DS-11 + DS-12 + DS-13.

• 10. The OPSWO-DT to 0PSW2-DT signals control the ZDI switch for transferring data words from the cache memory to the processor 700 via the ZDS lines.

OPSWO-DT = RD-IBUF / ZDI

OPSWl-DT = RD-IBUF / ZDI (REQ-CAC + UGCOGTH) .WDSELO.

0PSW2-DT = RD-IBUF / ZDI + WDSL01, (RD-SNG + INST-FI) + REQ-CAC.UGCOGTH⁷) .INST-FI + REQ-CAC.UGCOGTH) .RDSNG + REQ-CAC. UGCOGTH. DBL-FF.

11. The ZACSW1-LC1 and ZACSW2-LC2 signals control the 750-702 switch which selects the source address for all the pads in the cache. The sources are the processor 700 when receiving commands, the ZAC buffer and the CADR address register.

ZACSW1-LC1 = ZÀCSW1-LC4.CAC-BSY-1-UGCOGTH.

ZACSW1-LC2 = CAC-BSYL + UGCOGTH.

12. The DATA-RECOV signal allows the processor 700 to recover from a stop condition (for example resampling of registers).

DATA-RECOV = THCFD. (CINST-Fl + CRD-SNG).

(FMIFS-1. WDSELO + THCFD.

CRD-DBL (FSMIFS-1.WDSELO +

FMIFS-1.WDSELO + FMIFS-1

WDSELO + CBYP-CAC) + THCFD.

CDR-RMT.

13. The RD-BSY signal defines when certain state flip-flops are reset to O.

110

RD-BSY = RBB-00 + RBB-01 +. RBS-10 4RBB-11 + RBB-20 + RBB-21 +

RBB-30 + RBB-31.

14. The SSET-IN signal is used when setting certain state flip-flops.

SSET-IN = RBPSD.CDBL-FF, PENBIT-FF.UGCOGTH. CAOPR.CAC-BSYL.

(CPR-FF.ÇPR-RD.CINST-F2.CLD.QUAD.CRO-SNG.CRD-DBlX (CRD-TYP.RZAC-ALL-BSY] .DREQ-CAD.

15.

SEC-RVC = RMIFS-2. R.MIFS-3 [RBB-00 ® RBB-Ol) +

RMIFS-2.RMITS-3 ÎRBB-10 © RBB-lïî +

RMIFS-2. RMIFS-3 * [RBB-20 φ RBB-21] +

RMIFS-2 RMIFS-3. [RBB-30 © RBB-3 #

16. BPSD signal indicates cache match condition ^

BPSD = BYP-CÀC (ZAD010-23 = SP-i-00 -&gt; 14).

i = 0

F / Ei.? ÉNi where SP-iOO -14 corresponds to the outputs of the address directory (the stored address bits), F / Ei corresponds to the bit i "full / empty and PENi corresponds to the bit i" pending .

It should be noted that, in the expressions indicated above, the symbols. defines an AND operation, + defines an OR operation, and © defines an exclusive OR operation.

750-5 cache directory set

This set includes a 4-level order directory-&gt;

750-500 calves and a directory of associative addresses at 4 levels 750-502. The 750-502 directory has 28 columns which are each divided into 4 levels, over a length of 15 bits in order to provide space in each column for four blocks. The 750-500 command directory has 128 slots of 10 bits each containing a 10-bit command information word. The control information corresponding to each of the blocks comprises two permutation bits (RR), 4 full / empty F / E bits) and 4 bits of operation in progress, as shown in the figure.

_U1 2425110

The full / empty bits indicate whether a particular address in the directory has meaning (that is, if it is valid). When a cache match occurs, the F / E bit should be set to 1. A binary O indicates the presence. 5 this from an empty block. The swap bits define a count that indicates which block was last replaced. This count is increased by one unit under full / empty bit control by a 750-512 counter and is used to identify the next block to be replaced. As shown in Figure 3, this is done when the permutation and full / empty bits are transferred to two registers 750-704 and 750-706. The full / empty bits are also transferred to a register 750-105 which controls the progression of the permutation bits. Thus, the permutation bits are used after all the full / empty bits have been set so as to establish which of the full blocks is to be used for new data. The resulting value (ADDRRO-1) is applied to the input of switch 750-518. All full / empty bits are reset to 0 by an initialization signal. Full / empty bits can be set to one via a^z register 750-516. When the processor 700 issues a read request which corresponds to an absence of correspondence during the flip-flop state UGCOGTH, a value 1000 ”is loaded into the register 750-516. This value is written to the 750-500 command directory. On the next request, the value 1100 is loaded

- in register 750-516 and etc ... until all the full / empty bits are set to one.

Current operation bits are used to indicate when a particular operation is being executed.

For example, the pending bits, when set, indicate that all of the read data for a particular block has not been received. In correspondence, during a read operation, when the address directory signals a correspondence and when setting the pending bit, the cache memory 750 stops the operation of the processor 700. Consequently, no new request is made. is sent to the main memory.

The network used to set and reset the current operation bits to 0 includes a 4-bit buffer register 750520, a block decoding register 750-524 and a decoder 750-.

112 2425110

512. The registers 750-520 are addressed during a write cycle by the signals PRZACTO-1 via an address register 750-522 and, during a read cycle, by the signals MIFS-2-3. The block decoding register 750-524 ensures the setting to 1 of different output signals BKDCODO-3 under the following conditions: (1) at least one full / empty bit is in state 0, it occurs, during from setting this bit to 1, setting the corresponding waiting bit to 1 via the decoder 750-512. When all the full / empty bits are set to 1, the next value kO of the permutation account is coded and this bit position included in the set of four pending bits is set to 1.

A pending bit is reset to 0 via the decoder 750-512 only when the cache memory 750 has received all the information (ie 4 words) from SIU 100. The contents of registers 750 -520 indicate the position of the waiting bit to reset to 0. The waiting bits extracted from the 750-500 command directory are transmitted to the decoder 750-514 for the necessary update.

The current bits are set to 1 and reset to 0 under the following conditions:

UPDATE: INSTF2 (BYPCAC + CACMISS) / LDQUAD (BYPCAC + CACHEMISS) + PREREAD (BYPCAC + CACMISS) + READSINGLE.CACMISS + READDBL. bypcac-cacmiss.

RESET: INSTF2 + LDQUAD + PREREAD + RDSNG + RDDBL.BŸPCÂC.

The actual control signals have been indicated previously.

The address directory 750-502 contains, as mentioned above, 128 sets of 4 words each having a length of 15 bits. Each 15-bit word corresponds to the address of a 4-word block in the cache memory 750-7. Each time a ZAC command is processed and involves writing or reading in cache 750, the 15 bits of the block address contained in the buffers ZAC 750-100 or 750-102 are compared on the basis of combination with the address contents of the 750-502 directory so as to determine the existence of a condition of correspondence or absence of correspondence. More particularly, the directory 750-502 performs its associations on bits 0-14 of the address ZA.C in order to detect a condition

113 or no correspondence. These bits correspond to the address signals applied to lines 11-18, 2026 of ZAC, or else lines 20-24 of ZADO / RADO and chosen via a two-position input switch ZACSW 750-530 .

The address of the distributor combination is defined by a cache memory (CADDLO-6) applied via a three-position input switch 750-702. This allows an indication of 4 block addresses which are extracted and applied to the input of each of the 4 comparator circuits 750-536 to 750-542 of a group. Each comparator circuit compares its block address with bits 0-14 of the ZAC address. The results established by circuits 750-536 to 750-542 are · applied to the corresponding inputs of a first group of AND gates 750-550 together with corresponding full / empty bit signals from the register 750 * 506. A second group of ET gates 750-552 to 750558 combine the outputs of AND gates 750-544 to 750-550 with ZEXTBKO-3 signals indicating the block selected and applied via the 750-518 register.

ET gates 750-552 through 750-558 provide a group of block selection signals (i.e., CBSELO-5 signals), which are applied to the cache memory 750-700 as well as a group of memory circuits. directory match detection part of block 750-560. The circuits in block 750-560 include a group of AND gates 750-562 which provide the logical combination of signals representing pending operation bits with the block selection signals, the results being logically combined using an OR gate 750-564 in order to supply a directory correspondence signal transmitted via the BPSD line. The circuits of block 750-560 put the BPSD line in binary state 1 when the address bits 0-14 correspond to the contents of the directory, when the corresponding full / empty bit is in binary state 1 and when the corresponding waiting bit is in binary state 0. We will assume that there are error conditions.

114

750-7 cache memory set

The 750-7 set includes a memory unit

750-500 containing 2048 (2K) 40-bit word locations which are divided into 128 groups of 4 blocks. The unit consists of bipolar pads of classic design. The 750-700 cache memory set is addressed by the address to 7 CADDL0-6 applied via the 750-702 switch. The address is stored in a register 750-704. This results in the application of 4 blocks of 4 words to a group of 1 to 4 selector switches (not shown). The appropriate block (level) is determined by the states of the block selection signals transmitted by the CBSELO-3 lines. The signals applied to the CBYSELO-7 lines via the 750-708 switch ensure the proper selection of even word and odd word bytes. Between the words 0, 2 and 1, 3 the selection of byte is independent and takes place as follows;

OBYSELO (byte selection 0) for words 0, 2

CBYSEL3 (byte selection 3) for words 0.2

CBYSEL4 (Selection of byte 0) for words 1,3

CBYSEL 7 (selection of byte 3) for the words 1.3.

115 2425110

The signals applied via the CWSEL0-3 lines via a 750-706 decoder are used to designate the words. We make sure that the contents of the appropriate bi1s positions are defined in the group of memory pads which constitute the set 750-700.

The words of a selected block are applied to the inputs of a number of OR (NAND) door groups 750712 to 750-716. Each group of doors selects the word of the selected block. Words exiting the OR gates are applied to the inputs of an instruction buffer 750-900 via a second position of a two-position switch 750-902 and to the first four positions of an output switch ZDI 750-720 for application to the 700 processor. The fifth position of the switch ensures the application of the word contents of registers 750-180 to processor 700 via a ZBP switch 750-902. Finally, the sixth position of the ZDI switch 750-720 transmits the output of the instruction buffer 750-900 via the lines ZIB 0-39.

As shown in the figure, during a write cycle, the contents of ^ notes from register 750-180 are applied to the inputs of unit 750-700.

750-9 Instruction Buffer Set

This set includes a 16-word instruction buffer 750-700 which receives incoming data from registers 750-180 through the switch 750-902. As mentioned earlier, the outputs of the cache memory set 750-700 are also written to the buffer 750700 through the switch 750-902. Control signals and address signals transmitted through a switch 750-904 are decoded by a decoder 750-906 and are used to switch a read address counter 750-908 and a counter d write address 750-910 in appropriate states. The addresses leaving the counters are transmitted via switches 750-9C2 and 750-914 to the buffer 750900 and are used to constitute the appropriate addresses during read / write and write cycles.

116

750-10 diagnostic block.

As can be seen in Figure 4, the cache unit 750 further includes a diagnostic block 750-10. This block is used in conjunction with a PI interface for diagnostic and maintenance operations. In FIG. 4, the block 750-10 comprises a 7-bit counter 750-1000, two multiplexer detector circuits 750-1004 and 750-1006 and a decoder circuit 7501002.

The 750-1000 counter can be loaded via the ZPIDT29-35 signal lines corresponding to an access address to the locations of a 750-500 command directory and of a 750-502 directory via d 'a switch 750-702. The decoder circuit 750-1002, in response to signals sent via lines ZPIB9-10, generates (

output signals which are sent via PIBKO-3 lines to an input of switches 750-532 and 750-534 to select a particular block.

750-1004

The ^ 750-1006 switches receive the address and status signal sets from the 750-500 control directory and the 750-502 directory. In particular, the switch 750-1004 comprises 4 blocks each having 4 inputs for receiving a particular combination of the signals RSPENO-3, RDR F / EO-3, ADDRRO-1 and RDRRRO-1. Depending on the coding of the signals sent to lines ZPIB9-1O, the combination of 4 signals from one of the four blocks is selected to be sent to lines ZDIR16A to ZDIR15D.

Similarly, the switch 750-1006 comprises 4 blocks each having 15 inputs for receiving one of the 4 sets of address signals SP00-14 to SP30-14. This switch, once enabled by an ENZDIRI10 signal, sends a set of most significant address signals read from the 750-502 directory. Parity bit signals, not shown, are also sent to inputs of switch 750-1006. The ZDIRO-15 line output signals from switch 750-1006 as well as the ZDIR16A to 16D line signals from switch 750-1004 are sent to additional inputs constituting parts of OR circuits 750-712. These signals are in turn transferred via the circuits of the central processing unit 700 through position 1 of a ZDÎ 750-720 switch to the unit - triggering the PI command. As we will explain below, the trigger, the trans2425110

117 fert and the processing of PI commands via the PI interface are carried out as described in US Patent No. 4,006,466 and Patent 4,017,839, as well as in US Patent Application 755,907, assigned to the same assignee as the this request.

OPERATING DESCRIPTION

The operation of the preferred embodiment, according to the present invention, will now be described, with reference to FIGS. 1-10, with respect to the processing of a shaping instruction which has a format and a code which will be defined in the following.

This instruction is contained in an instruction repertoire having the processing capacities of byte, character and bit strings called extended instruction set (EIS). The instruction has a multi-word instruction structure. The first word is a basic instruction word containing the operation code which is followed by first, second and third descriptor words. Bits 0-17 contain additional information regarding the operation. In particular, the bits include two 7-bit modification zones coded to specify any address modification to be made on operand descriptors. In this case, the zones can be considered as formed by ZEROS.

Bits 18-27 include the operation code value encoded to specify a formatting operation while bit 28 is an interrupt service bit considered to be 0. Bits 29-35 correspond to another modification zone. 7 bits coded to specify the address modification to be performed on a descriptor 1. We consider that this zone contains only ZEROS.

The second word contains an 18-bit address for descriptor 1, a 3-bit CN1 area coded to specify the number of original characters inside the word considered, a 2-bit TA area coded to specify what type of alphanumeric characters are in data and a 6-bit NI field encoded to specify the number of characters or bits in the data string or a register that contains the number of characters or bits. The maximum length allowed is 63. The TA zone is coded as follows:

118

DATA TYPE CODE

9-bit OO

6 bits

4 bits

The CN area for 9-bit characters is coded as follows:

NUMBER OF CHARACTERS CODE

000 0

110 3

The third and fourth maxima words contain similar information for descriptors 2 and 3 respectively.

The shaping instruction requires micro operations (MOP operations) to perform the shaping functions effectively. The micro-operation sequence to be executed is contained in memory and is indicated by the second operand descriptor word. Some of the micro-operations require the insertion of special characters in the manipulated character string. These special characters are contained in a shaping insertion table stored in the interpreter memory of a unit 714. This table is made up of 8 characters of 9 bits and at the beginning of each shaping instruction, the unit central processing unit 700 initializes the table to the following values:

TABLE ENTRY 12345678

VALUE b + - g, .0.

The operand descriptor for deniero-operations (0P2) indicates a 9-bit character string that specifies the micro-operation to be performed during the formatting instruction. Each of the 9-bit characters has a format that includes, a 5-bit MOP area encoded to specify the micro-operation to be performed and a 4-bit IF area encoded to specify the number of basic binary digits to handle (1-16) , or the number of the particular entry in the formatting insertion table to be used according to the coding of the MOP area. The micro-opera^- are

119 normally terminated when the received chain length is used up (L3).

The different areas of the EDIT formatting instruction are coded as shown in Figure 8. For more information on the instruction in question, reference may be made to the publication Series 60 (Level 66) / 6000 Macro Assembler Program (GMAP) ”from Honeywell Information Systems Inc., copyright 1977 order number DD08B, Rev.O.

For this example, it is considered that the aforementioned shaping instruction is stored in the instruction buffer 750-700. It is also considered that the operand data specified by the descriptors 1,2 and 3 are not stored in the cache unit 750 but are located in the main memory 800.

Referring to FIG. 10, it can be seen that the first cycle relating to the processing of the shaping instruction (MVE) is a cycle ^ END, which corresponds to a last cycle of the previous instruction . This cycle is established by forcing a control signal from Γ END to ONE binary in accordance with a following Boolean expression: J_END = FESC100. DPIPE 1-4 + ...

The FESC state flip-flop is ONE binary when the processing unit 700 operates under microprogrammed control as during the execution of a program instruction. A DPIPE1-4 signal is at binary ONE when bits 38-40 are coded to specify or restart the recovery / of the pipeline mode by which a new instruction is loaded in the registers of the processing unit. i.e., type 1. When both FESC100 and DPIPE1-4 are binary UNS, the j_END cycle is started via the circuits of a block 704-102.

During the JEND cycle, the central processing unit 700 transfers, under microprogrammed command, signals corresponding to the first word of the shaping instruction in the registers RBIR, RSIR, RBSA, RRDXA and R29 of a block 704-150 from buffer 750-900 via lines ZIB 0-39.

In this example, the registers RBASA, RRDXA and R 29 are positioned at ZEROS (that is, the zones corresponding to bits 0-2, 32-35 and 29 of the EDIT instruction are ZEROS) .

If we consider that the previous instruction was not a transfer instruction, the processing unit 700 sends

120 a signal on line ^ RDIBUF / ZIB to advance the read counter 750-910 of the buffer 750-900 by one to read the next word in the EDIT formatting instruction (descriptor l). the content of the lines ZIB is loaded into the registers RBIR andRSIR in response to the signals SRBIR and f ^ SRSIR generated by a decoder 704-106 via switches 704-172, 704-170 and 704-173. Bi.ts 0-2 are loaded into the RBASA register 704-144 and bits 32-35 are loaded into the RRDXA register 704-158 in response to i signals. SRBASA and £ SRRDXA via switches ZBASA, 704-175, 704-176 and 704-177. A bit 29 is loaded into the register R 29 in response to a signal SR29 via a switch 704-183.

If we consider that the previous instruction was not a transfer instruction or an EIS instruction, the content of the instruction counter 704-310 progresses by one by an adder 704-312, via a position 3 of switch ZÏC-N 704-314 (i.e. the value 001).

The FPOA cycle is then launched in response to the switching of the FPOA state flip-flop of a block 704-102 in FIG. 3.

The FPOA flip-flop is set to ONE binary under hardware control in accordance with the following Boolean expression:

UPDATE = JhOLDI. (DIBFRDY.DIBFEMTY. / STRCPR.

DXEDRPTS. DPIPE1-4).

This is how the FPOA cycle is triggered following a £ END cycle when there is no HOLD holding condition relative to the pipeline (i.e., a HOLDIOO signal = 1), that the instruction buffer 750-900 is not empty (that is, DÏBFEMTYOO = 1), that there is at least one instruction. Ready for a transfer to the unit of processing 700 (i.e., DIBFRDY100 = 1), that the previous instruction was not a memory comparison instruction (i.e., £ STRCPROO = 1) or an execute / repeat instruction (i.e. DXEDRPTSOO = 1) and the pipeline has been restarted (i.e. DPÎPE1-4 = 1) .

At this time, the register RBIR 704-152 memorizes the zone of code-operation of instruction of formatting as well as the zones of modification of address MF1, MF2 and MF3 for the des2425110

121 scribers 1,2 and 3, respectively. During this cycle, the flag or indication flip-flops FID and FRL are set to one by signals corresponding to bits 30 and 31 of the register RBIR 704152 sent via the switch ZIDD 704-180 in response to a signal pZlDD generated by the circuits of a block 704-124. Similarly, registers R29 and RRDXA 704-162 and 704-158 are set one by signals corresponding to bit 29 and bits 32-35 of the RBIR register 704-152 sent via a ZIDD switch 704 -180. Similarly, the flip-flop RDESC1 is reset to zero by setting the binary state flip-flop FPOA to ONE. The values ​​loaded in these registers are ZEROS.

Under hardware order, the value 00 is forced into the RDESC register 704-170. This is how the RDESCO flip-flop in register 704-140 is set to one and reset to zero in accordance with the following Boolean expression:

UPDATE: RDESCO = area of ​​large CU of reg. + small CU FMTD area +

DESC1. (DNUM3EDIT) .FPOP.

RESET: RDESCO = FPOA + large CU area + small CU area.

In this case, the RDESCO flip-flop is reset to zero by setting the binary FPOA state flip-flop of block 704-102 to ONE binary.

The RDESC1 flip-flop is set to zero and reset to zero in accordance with the following Boolean expressions:

UPDATE: RDESC1 = area of ​​large CU + area of ​​small CU +

DESCO.FPOP.MTM MTR.

RESET: FPOA + (DESC1. (DNUM3EDIT)

FPOP) + large CU area + small CU area.

In addition, the content of the next word (descriptor 1) of the formatting instruction sent to lines ZIB 0-39 is loaded into the RSIR register 704-154 in response to a control signal (SRSIR. Bits 0- 2 are loaded in the RBASA register

704-156 from ZIB lines while bits 21-22 corresponding to area TA1 are loaded into the RTYP register 704-160 via ZIB lines in response to signals

122

SRBÂSA and ^ SRTYP generated by the circuits of a block 704-106.

The TA1 field value "00" which specifies a 9-bit character is loaded into the RTYP register 704-160 via switches 704-178 and 704-179. ZEROS are also loaded into the RBASA register 704-156 via switches 704-174 and 704-175. In addition, block circuits 704-108 and 704-128 force a line RDÏBUF / ZÎB to ONE binary. This advances the read counter 750-910 by one to read the third word of the formatting instruction (descriptor 2).

Operation code signals sent via the RBIR register 704-152 to the CSS memory 704-200 allow an output register 704-202 to read the contents of the designated memory location * when a clock signal.

As can be seen in Figure 3, the content is coded to contain the following control information:

CCSO = 000,

CCSR = 0100; CCSS = 11101 and

CCSI = any.

When the CCSO zone contains ZEROS, the FNUM flip-flop of a block 704-104 remains at binary ZERO. The CCSR area is coded to designate a 4-word area and is used to advance the instruction counter to a value appropriate to the completion of the shaping instruction.

The 10-bit operation code (bits 18-27) in the RBIR register 704-152 is transformed by the CCS memory 704-200 into a suitable 6-bit code for controlling and selecting the appropriate command sequences. The CCSS area is decoded by the circuits of a block 704-100 and then establishes the particular sequence while switching the FPOP flip-flop to ONE binary. Therefore, the CCSS area once decoded indicates that the type of instruction is that of an EIS DEDIT instruction.

The FPOP flip-flop is set to zero and reset to zero in accordance with the following Boolean expressions;

UPDATE: FPOP + f HOLDI. ([NEEDDESC.

FPOA.DEIS. DBIT. + DESCO. FPOP. DEDIT + DPIPE-6) + _____ DIBFRDY

123 _____

RESET: FPOP = RESET.

In this case, the FPOP state flip-flop is set to a descriptor is not necessary (i.e.,

NEEDDESCOOO = 1), the FPOA flip-flop is set to one (FPOA = 1), the CCS area specifies an EIS instruction (DEIS = 1), the CCS DBIT bit =

O and the instruction buffer 750-900 is in the ready state (i.e., DIBFRDY = 1).

During the first FPOP cycle, the address preparation unit 704-3 generates the address specified by the first descriptor word. Bits 0-20 (y) of the RSIR register 704-154 are thus sent to an input of an adder 704-322 (i.e. descriptor address) via a switch 704326 and AND gates in response to register R 29 704-162. This value is added to the content of the address register selected by the content of the RBASA register sent via a switch 704-328 when the bit R 29 is at ÜN. If bit R29 is at binary ZERO, the effective address corresponds to the descriptor address. The output of switch 704-328 sends ZEROS while being invalidated by the state of bit R 29. The effective address value is added to an address modification zone (X or AR) selected via a ZX switch according to the content of the register RRDXA 704-158, of the register RTYP 704-160 and from the FNÜM scale of bloe704-104. When these values ​​are ZEROS, the address modification zone consists of ZEROS.

The resulting value is then stored in the TEAO location as designated by the contents of the RDESL704-144 register via a switch 704-334. The adder 704-320 adds to this resulting value a base value stored in a temporary base register specified by the content of the RBASB register 704-144. We consider the base value equal to ZERO. The resulting address therefore corresponds to the descriptor address. The ZBASE value is also stored in the TBASEO register via a switch 704-332.

According to the present invention, under hardware control, the central processing unit 700 issues a cache pre-read command to the cache unit 750. This ensures its immediate loading with the necessary data while the unit

124 processing 700 continues processing a shaping instruction. As can be seen in FIG. 9, this command causes the reading in main memory 800 of a first block of 4 words of descriptor data 1 stored at locations 1000-1003, in parallel with the processing of an instruction, so when the processing unit 700 is ready to use this data, it is in the cache memory 750. The pre-read command thus makes it possible to extract data necessary for carrying out an instruction in advance with respect to the processing of the following descriptor of the instruction. This operating order advances the execution of the operation specified by the instruction during the initial phases of the operation (that is, the extract operands). The arrangement of the present invention therefore has the effect of speeding up the execution of the instruction considered by the central processing unit.

The pre-read command is generated as follows. The absolute descriptor address is loaded into the RADO register through the ZADGB switch in response to the ^ RADO signal generated by the decoder circuits 704-124. In addition, control bits 1-4 and area bits 5-8 are sent by a switch 704-40 instead of bits 1-8 from a switch 704-46 while bits 0 and 9 are forced to ZEROS. Bits 1-4 from the RMEM register 704-130 are converted into a control mode of 0111 by the decoder circuits of a block 704-118. This command code specifies a QUAD memory read operation. Field bits 5-8 are set to binary UNS through the input switch 704-40 and are not used for reading. At the same time, the circuits of a block 704-108 generate the pre-read code of YES '' which corresponds to the signals MEMOTB to MEM3TB. These signals are generated according to the following Boolean expressions:

MEMOTB = 0 ~ MEM1TB1 £ mEM2TB? = EPOP.EDIT.DLNNZ (DESCO.FËII + DESC1.FÉ2).

ΓMEM3TBj

125

When the FPOP flip-flop is set to one, the instruction is a formatting instruction, the length is not zero (DLNNZ = 1 established by the flag or FIGNLEN control indicator) for the descriptor, these signals are UNS binary when the first flip descriptor area (DESCO = 1);

(FEIIN = 1) or the second descriptor area (DESC1) being processed has not been exhausted (FEU or FE2 = 1). These values ​​can all be considered as binary UNS at the start of an instruction processing.

These signals are then loaded into the register

RMEMO-3 704-130 via a 704-116 decoder. The content of the RMEMO-3 704-130 register is sent in turn on the lines DMEM0-3. In addition, the circuits of block 704-108 generate signals which force the RSZ register 704-132 to the value

00. The content of this register is sent on the DSZ lines to specify a complete word writing (not used to generate prefetch commands). The decoder 704-120 forces the DREQCAC line to ONE binary when the DMEM command stored in the register 704-130 is decoded. The BYPCAC line can be considered as binary ZERO in the example.

During the FPOP cycle, signals corresponding to the TAl zone are transferred from the RTYP register 704-160 via a switch 720-42 of the unit 720 in accordance with the state of the RDESC register 704-140 . The signals have a value of 00 which means that the descriptor data area 1 is made up of 9-bit characters. Signals corresponding to the area NI which represents the length are also transferred from the RSIR register 704-154 via the switch ZLN 722-82 into the register RLN1 of a block 722-80. These signals have a value indicating that the descriptor data area. has 16 characters.

The register RCN1 720-28 represented in FIG. 3h, contained in the character unit 720 is loaded with the value 10₂corresponding to the CNI zone of descriptor 1 transmitted by lines ASFA 34-36 and a RAD register 720-24 from a TEAO register of block 704-302 having stored descriptor 1. This value points to character number 2 of the first descriptor 1 data word as the starting character for begin

126 for treatment. The RPO register of a block 722-20 of a unit 722 is loaded with the character pointer value 01 ”by the lines ASFA 33-35 and the ZRPA switch 722-23 for temporary storage of this value.

Signals corresponding to zone MF2 are then transferred to register S§9 704-162, to register RRDXA 704-158 and to flip-flops FID and FRL of a block 704-110. The signals are also sent by the ZIDD switch 704-185 from bit positions S-17 of the RBIR register 704-152. As can be seen in FIG. 10, these values ​​are all ZEROS indicating that there is no modification of the data of descriptor 1. The RDESC register 704-140 is loaded, under control of the material of the value 'Olg can designate an operation of the descriptor 2. The flip-flop RDESCO then remains at zero while the flip-flop RDESC1 is set to binary ONE since the descriptor 1 is processed ( DESCO = 1); the cycle is an FPOP cycle (FPOP :: 1) and the instruction is not a memory type instruction (MEM to MEM or MEM to REG MTMMTR = 1).

The central processing unit 700 sends a new control signal on the line ^ RDIBUF / ZIB to advance the read counter 750-110 of the buffer 750-900 in order to read the next word of the shaping instruction ( descriptor 3). The content of descriptor buffer 2 sent on the ZIB lines is loaded into the RSIR register 704-154 while bits 0-2 and 21-22 from the ZIB lines are loaded respectively into the RBASA register 704-156 and the TYP register 704-160.

At this time, the RSIR register 704-154 contains descriptor 2, the R29 register 704-156 contains ZEROS indicating that there is no modification of address register and the RTYP register 704-160 contains ZEROS indicating that descriptor data area 2 is made up of 9-bit characters.

With regard to cache 750, the memory prefetch command sent by lines ZPSWA0-39 is written in an empty location of the buffer RZAC 750-102 specified by the content of a counter 750-106. As mentioned

127 the address of the empty slot is determined by the state of the activity bits. This entry is made regardless of a match condition or no match condition (i.e., BPSD status). The content of the ZAC read buffer is used in a subsequent cycle to store the address to be entered in the '750-500 · order directory.

The cache control is then decoded by the cache decoder 750-166 to establish which control state flip-flop of a block 750-3 should be set. In the case of a pre-read command, it results from a lack of correspondence for the cache memory a directory assignment cycle in which the address is entered in the command directory 750-500, the bit full / empty is set to one if it is not and the appropriate wait bit is set to one to indicate that the operation is now on hold. As explained, the directory assignment cycle is triggered when the state flip-flop UGCOGTH is switched to binary ONE. It will be noted that it is the cache unit 750 which determines whether the central processing unit 700 continues its processing in accordance with the state of the line CPSTOPOO. In the case of a pre-read command, the two set-to-1 and turn-off signals are binary ZEROS maintaining the line CPSTOPOO at binary ONE. The state of the line CPSTOPOO validates the continuous application of clock signals to the circuits of the processing unit, which allows the central processing unit 700 to continue processing. cache memory 750 stops the operation of processing unit 700 in the case of a cache read command occurring in the absence of a match.

At the same time as it decodes a command, the cache unit 750 has access to the directories 750-500 and 750-502 and to the memory 750-700 of the cache memory. The 750-500 and 750-502 directories and the 750-700 memory are addressed by address signals from the RADO 25-33 lines sent by a 750-702 switch. Comparison circuits 750-136 to 750-542 compare the address sent from the RADO-ZADO lines to the directory address. If the data of the first descriptor is not in the cache memory, circuits 750-560 maintain the correspondence signal - absence of BSPD correspondence at zero. The seesaw

128

UGCOGTH is thus switched to binary ONE by a SETCQGTH signal due to the BPSD and CPRRD signals which immediately follow the request from the processing unit when the command directory 750-500 must be updated.

During the directory assignment cycle, the address entered in the buffer RZÂC 750-102 passes through the ZAC switch 750-530 and it is sampled in the directory 750-502 instead of being compared as in the previous cycle. When the command is deferred because data is received from the main memory, an alternate state flip-flop TLTHM is set. The directory assignment cycle is eliminated, data from memory is stored in the cache memory, and the search and directory assignment cycle is re-executed. Set differently, the control operation is interrupted and restarted via the alternate TLTHM toggle.

During the directory search cycle and before a match or no match condition is determined, the ZAC command is loaded into the output register of SÏU 750-174 via the switch ZPSWA 750-110 and the ZPSW 750-178 switch (the cache unit assumes a no match condition).

During the directory assignment cycle, the cache unit 750 makes the SÏU 100 request a memory operation under the control of a state flip-flop CÂOPR. Thus the flip-flop CAOPR forces the line AOPR to ONE binary to signal the SIU 100 unit the memory request. At this time, the ZAC command is sent on the DTS lines together with the appropriate memory identifier signals and the maneuver signals sent on the MITS and SDTS lines. The memory identifier signals are sent by a register 750-138 previously loaded from a register 750-106 via a switch 750-139. The operating signals are generated conventionally by means not shown to designate the central processing unit 700 as being at the origin of the request. For more information regarding the use of maneuvering signals, reference may be made to US Patent 4,006,466.

129

The SIU1OO unit signals the acceptance of the cache memory request by forcing the ARA line to ONE binary.

It then transmits the request to the main memory which extracts the block of 4 words from the descriptor data 1. During the transfer of a first pair of data words, the SIU 100 forces the ARDA line to ONE binary, which which indicates that the even word of the pair is available on the lines IF, S. The SIU 100 also forces the DPES line to ONE binary to indicate a double word transfer. This switches the OATB flip-flop to ONE binary, which indicates that the odd data word is available on the DFS lines. The THCFD flip-flop is then switched to ONE binary.

The first data word is loaded into register RP 750-179. The memory identifier signals sent on the MIFS lines by the SIU 100 unit are also loaded into the RSPB register 750-124. Bits 2 and 3 are used to access the ZAC read command in the RZAC 750-102 buffer . The address is again sent to the cache memory 750-700 and to the directories 750-500 and 750-502.

In addition to accessing the 750-700 directories and cache memory, the first data word is loaded into the RDO 750-180 register. The second word is transferred to the RP 750-179 register and loaded into the RDI 750-180 register. The two words are then written to the cache memory 75025 700 at the location specified by the ZAC command. In addition, the first activity bit is reset according to the coding of the MIFS1-3 signals.

The SIU 100 performs the transfer of the next two data words to the cache unit 750 by forcing the ARDA and DPFS lines again to binary UNS. This again switches the OATB flip-flop to ONE binary, which in turn switches the THCFD flip-flop to ONE binary. Once again, the signals stored in the MIFS register 750-124 give access to the ZAC command originating from the buffer ZAC 750-102 to address the directories and the cache memory 750-700.

At the same time as the addressing, the following two data words are transferred via the register RP 750-179 to the registers RDO and RDI 750-180. The words are

130 then entered in the cache memory 750-700 to complete the storage of a first descriptor data block 1 in order to make it available for the processing unit 700. When the command is a pre-read command, the cache 750 does not allow the switch 750-720 to validate the transfer of the data words to the central processing unit 700. During the write operation, cache 750 resets the second activity bit to zero according to the MIPS signals and the wait bit indicating the completion of the prefetch operation.

As FIG. 9 indicates, as well as the flow diagram of FIG. 10, the central processing unit 700 executes a second FPOP cycle. Thus the flip-flop FPOP remains at a binary because the descriptor 1 is treated (DESCO = 1), that the previous cycle was an FPOP cycle (FPOP = 1) and that the instruction is a shaping instruction ( DEDIT = 1). Signals corresponding to a value of address Y of descriptor 2 (RSIRO20) loaded into the RSIR register 704-154 during the first FPOP cyscle are transferred via the switch ZY 704-32S in association with index values ​​( X) or address register (AR) from a ZX switch 704-58 and a group of registers 704-304, respectively, by an adder 704-322. When there is no modification of index or address register (MF2 = 0), the values ​​sent on lines ZARO23 and lines ZX0-20 are ZEROS. The descriptor address value 2 is thus transferred to the TEA1 location of a group 704-302 selected by the content of the RDESC register 704-144 and to the RADO register 704-46 via the ASFA lines and a adder 704-320. It will be noted that the appropriate base value is added to the address of descriptor 2 in the same way as what has been described previously for descriptor 1.

As can be seen in FIGS. 9 and 10, the central processing unit 700 generates another prefetch command in which the command word ZAC sent on the RADO / ZADO lines comprises the address value 3000 of descriptor 2 and a QUAD memory read operation. This command is passed to cache 750 and is treated the same as the other command. Since we consider that the data

131 of descriptor 2 are not in the cache memory, the pre-read command causes the loading in the cache memory of the first block of descriptor data 2. In FIG. 7 it can be seen that this block includes the data characters of the words at addresses 3000-3003.

During the processing of the pre-read command in the cache memory, the central processing unit 700 continues its processing. During the second FPOP cycle, the RTF2 register 720-46 is loaded with signals corresponding to the TA2 zone via the RTYP register 704-160. The value also indicates that the descriptor data 2 consists of 9-bit data characters. The register RLN2 of a block 722-80 is loaded with signals corresponding to the area N2 by means of the switch ZLN 722-02 in from RSIR lines. The value indicates that the length of descriptor data area 2 is 6 characters, as shown in Figure 7.

In addition, the register RCN2 720-30 is responsible for the value llg ”via the lines ASFA 34-36 and the register RAD 720-24. This indicates that the third character of the first descriptor data word 2 is the first character in the area to be processed. The register RP1 of a block 722-20 is also responsible for the value of character pointer llg to temporarily store it.

Signals corresponding to bits 0-8 of the zone

MF3 are transferred from register RB1R 704-152 to register R29 704-162, register RRDXA 704-158, flip-flops FID and FRL via the switch ZIDD 704-180. The vaqu'une their constituted of ZEROS indicate / modification of address is necessary for descriptor 2. The register RDESC 704140 is forced to memorize a value lOg ”designating a descriptor operation 3 (see the Boolean expression).

The i RDIBUF / ZIB line is forced to ONE binary to advance the read address counter in order to point the next instruction. The signals corresponding to a descriptor 3 sent on the ZIB lines are loaded into the RSIR register and the R29 register 704-162. Signals from ZIB 0-2 lines are also loaded into the RBASA 704-156 register. Likewise, ZEROS are loaded into the RTYP register 704-160

132 via the ZIB lines, which indicates that the descriptor data area 3 is made up of 9-bit characters.

During the FPOP cycle, the first 4 ASCII characters are transferred, under microprogrammed command, from a location 14 (8) of an interpreter memory 714-30 to the register RTRH4 (TR4) of a block 714 ^ .10. Signals are also generated to control the FINDA and FINDC command flag indicators and a conditional vector branching operation RB2, established by the area TA1 deduced from bits 21-23 of the RSIR register 704-754, is performed by the circuits d 'a block 701-1. The flag control is not appropriate for this instruction and can therefore be ignored.

As the flow diagram of FIG. 10 indicates, a cycle FESÇ is triggered by switching to binary ONE of the control state flip-flop FESC. The FESC flip-flop is set to zero and reset to zero in accordance with the following Boolean expressions:

SETTING A FESC = [HOLDI (FPOP.

SETFPOP).

RESET FESC = DPIPEO-5.

In this case, the FESC flip-flop is set to one since the FPOP flip-flop is set to one (FPOP = 1) and the flip-flop must not be reset to one (SETFPOP = 1), as it is considered that there is n There is no start of operation specified by microprogrammed command (see the Boolean expression - DPIPE area).

This cycle is under microprogrammed control in which the micro-instruction word cycle zone A = 1 is used. During this cycle, the 4 second ASCII characters are transferred from a location 158 of the interpreter memory 714-30 to the register RTRH5. (TR5) of a block 714-10. The descriptor character pointer value 1 stored in the register RPO of block 722-20 is transferred via the switch ZPA .722-27 and an adder Al 722-S2 in the operating register RLN3 of block 722 -80. The descriptor character pointer value 2 stored in register RP1 is also transferred via the ZPB switch 722-28 and a ZRPB switch 722-24 in register RP5 of block 722-22.

133

Memory registers (historical) of indicators, not shown, which are contained in the block circuits 701-1 are also given to ZEROS. These registers are used to memorize the states of input group 1 indicators selected by bits 136-139 of a micro-instruction word to carry out a test during a following operating cycle.

From FIG. 10, it can be seen that when the value “00 specifying 9-bit data characters is stored in the area TA1 controlled by the vector connection circuits of block 701-1, the processing unit 700 launches an operating cycle B1. During this cycle, the number of characters of a word from descriptor data area 1 is loaded into the RXPB register of a block 722-60, under the command of a microinstruction word comprising a type A area = 4. Figure 10 also shows that this value is 4 for 9-bit characters and that it is generated by the adder 722-72 in response to a constant sent by the ZXPB switch 722-70.

The length of descriptor data area 1 stored in the register RLN1 is transferred to the register RLN4 by the adder 722-92. Signals corresponding to the first 4 characters of the shaping insertion table stored in the register TR4 of a block 714-10 are also loaded into the table input register 1 of a block 720-10 by the switch ZRESA 714-36.

The central processing unit 700 then launches the cycle B3 and executes the operations specified by a micro-instruction word having a second format. During this cycle..Signals corresponding to the length of descriptor data area 2 stored in the register RLN2 of block 722-80 are sent to adder 722-92 and checked against zeros. The resulting indication is transmitted to certain flip-flops of an auxiliary flip-flop block 701-42 and if it is NULL it causes the switching of one of the end or exhaustion flip-flops (EXH2) to ONE binary. This prevents the processing unit 700 from reading the descriptor 2 during a cycle B7.

Signals corresponding to the next 4 characters of the shaping insertion table stored in the register TR5 of block 7.14-10 are loaded into the table input register 2 of block 720-10 via the switch ZRESA

134

Bits 44-46 (PIPE area) are also coded to specify a type 6 stimulus in which the FPOP flip-flop is switched to binary ONE during the next operating cycle. A command transfer is made to a hardware order, under which the processing unit 700 begins a third FPOP operation cycle to process a descriptor 3.

During the FPOP cycle (3), the address bits 0-20 (Y) of descriptor 3, read in the RSIR register 750-154 during the second FPOP cycle, are transferred to the ICBA register of a block 704-302 via the ZY switch 704-326, an adder 704-322 and a ZRESB switch 704-334. When there is no modification of index or register of specified address (that is to say an area MF3 = ZEROS), the address value corresponds to the descriptor value 3 of 5000. The same value (Base Z = ZEROS) is also loaded into the RADO register 704-46 by the ASFA lines.

As shown in Figure 10, the flip-flop PTF3 720-52 is set to binary ONE by the detector 720-50, indicating that the descriptor data area 3 is made up of 9-bit characters. Thus the value ”00 corresponding to the zone TA3 transmitted by the register RTYP 704-160 is decoded by the detector 720-50 which causes the flip-flop 720-52 to switch to binary ONE. In addition, signals corresponding to area N3 are transferred from bit locations 30-35 of the RSIR register 750-154 to the register RLN1 of bloe 722-80 via the switch ZLN 722-82. The RPG register of a block 722-70 is loaded with the descriptor character pointer value 3 consisting only of ZEROS by the ASFA lines, indicating that the descriptor 3 data zone begins at the character of number ZERO (address 5000) .

It can be seen in FIG. 10 that the processing unit 700 tests the value of descriptor length 1 stored in the register RLN4 with respect to ZEROS, under microprogrammed command. This is achieved by controlling one of the state indication flip-flops of a block 701-1 which indicates whether the output of the adder 722-92 is at ZERO or if no carry-over has been generated.

The conditions mentioned set one of the flip-flops (EXH11) to ONE binary for a next check.

135

The processing unit 700 then begins a cycle B5 in which it transfers the difference between the value of 4 of the register RXPB corresponding to the number of characters in a descriptor data word 1 and the value (10)₂ from the RLNg register, to point the character number 2 as the start character of the data area under the command of a micro-instruction word using the format TYPEA = 4. The difference in values ​​of 2 generated by an adder 722-72 is stored in the register RXP2 and indicates the number of data characters to be read or processed in the first data word of descriptor 1.

The length of the data area of ​​descriptor 3 is read from the register RLN1 and it is stored in the register RLN3 via the adder 722-92 and the switch ZLN 722-82 by a write command ZONEO. The adder flag AL = O is then selected ^ for a check. Then, the RDESC register 704-140 and the RBASB register 704-144 are set to ZEROS by reading descriptor 1 data.

Cycle B5 is followed by an operating cycle B6 during which the processing unit 700 transfers, under microprogrammed command, signals (value 1000), corresponding to the sum of an address of the first descriptor data word 1 coming from the TEAO register and a basic value from the TBASEO register generated by an adder 740-320, in the RADO register by the ASEA lines. The control unit 704-1 sets bits 1-4 of the ZAC control code to a code of 0000 to specify a simple read command and forces the DMEM lines to a code of 1000 to specify a simple cache read operation.

As previously described, the processing unit 700 transmits the read command to the cache unit 750. As can be seen in Figures 7 and 9, this data was first extracted from the main memory 800 and stored in the cache memory. Therefore, when cache 750 decodes the single read command, it accesses directories and cache memory 750-700, match detection circuits - no match 750-560 which force the BPSD line to ÜN binary indicating a match or presence of cache memory. None of the command status flip-flops are set to one in this case. Cache unit 750 con2425110

136 adds signals OPSWQ-2 to validate the transfer of the data word to an address 1000 in the processing unit 700 via the switch ZDO 750-9 during a following cycle. The previous processing of the pre-read command by the cache unit 750 therefore eliminates the stop of operation of the processing unit 700 while waiting for the requested data word. This would happen in the case of a single read command where an absence of correspondence was detected.

The processing unit 700 also subtracts from the descriptor length value 1 (16) the number of characters in the data word (2) by means of the adder AL 72292 and stores the value indicating the number of characters descriptor 1 remaining in the RXPD register of a block 722-60 via the ZXP switch 722-62. During this operation, one of the indication flip-flops of block 701-1 (EXH11) is set to binary ONE, if the value RLN4 is NULL (ALZ = 1 or carry).

In addition, the processing unit 700 sets the RDESC register 704-140 and the RBASB register 704-144 of the control unit 704-1 to the value Ol (that is to say, the area NXTD). This specifies reading of descriptor 2 information.

Cycle B6 is followed by cycle B7 during the control of the length of descriptor area 3 by an indicator (ALZ) which would have been set to one during cycle B5. When the ALZ indicator is not set to one, the processing unit 700 starts the cycle B7. The first descriptor data word 1 (operand 1) previously extracted from an address 1000 is sent on the lines ZDI 0-35 is loaded into the RDI register 704-164 via a switch 704-182. The length of descriptor 1 is also read in the register RLN4 and it is memorized in the register RXPA via the switch ZXPB 722-70 and an adder 722-72. Likewise, a copy of the descriptor length 3 is read from the register RLN1 and it is stored in the register RLN4 via the adder 72292.

The resulting descriptor address 2 generated by adding the contents of the TEA1 and TBASE1 registers, generated by the adder 704-320, is transferred to the RADO register 704-46. The processing unit 700 works for

137 generate another simple cache read command to be transmitted to the cache unit 750. The command is generated as described above. However, in this case, the ZAC command specifies the address of the descriptor data

2 (operand 2), (that is, address 3002), to be entered into the operand data 2. This data corresponds to the string command word characters in FIG. 8. As can be see in Figure 9 and as previously described, the cache unit 750 first extracted an operand data block 2 / descriptor 2 in response to a pre-read command issued previously. When the cache unit 750 decodes the simple read command, it therefore has access to the directories and the cache memory 750-700, and the circuits 750-560 again force the BPSD line to ONE binary signaling a cor15 correspondence. It then reads the first data word from operand 2 which is sent over the ZDI lines in the manner described above. Once again, the processing unit 700 loads, under microprogrammed command, the registers RDESC and RBASB with the value 00 to select temporary or descriptor maneuver registers 1.

As FIG. 10 indicates, the processing unit 700 initiates a cycle B8 during which a micro-instruction word having a format TYPEA = 2 is executed. During this cycle, the first descriptor data word 1 (operand .1) is transferred from register RDI 704-164 to register 0P1 of the character unit register block 720-10, in unit d 'execution ALU 714-20, in switch ZRESA 714-36 and on lines ZRESA 0-35.

The value 4 is then subtracted from the character pointer value read in the register RP5 and added to the value read in the register RLN2. This operation is carried out by the adder AL 722-92 which receives the appropriate values ​​by the ZLNA location of the ZÂLA 722-88 switch and the last location of the ZALB 722-90 switch. The result, provided by the state of ALZ or of the signal of absence of carryover indicating the remaining name 35 short of descriptor characters 2 to be extracted, is used to put one of the flip-flops of indication (EXH2) for a next control an end or exhaustion condition.

138

The first word of descriptor 2 (operand 2) sent on the ZDI lines by the cache unit 750 is loaded into the RDI register 704-164, the constant value of Ι20θ is generated by the adder AP 722 = 34 and entered in the RP3 register of block 722-20. This value corresponds to the interpreter memory address designating the location in interpreter memory 714-30 in which the second descriptor data word 1 (operand 1) is to be stored.

The first operand data word 2 sent over the ZDI lines from the cache unit 750 is loaded into the RDI register 704-164. A CSO 704-322 counter advances the descriptor address 1 read in the TEAO register by 1 (1 word) and the sum is again loaded into the TEAO register.

An adder 704-320 also adds the increased value to the base value read from the TBASO register and the resulting address (1001) is loaded into the RADO register 704-46. As can be seen in Figures 7 and 8, this address specifies the second operand word 1 comprising the 4 9-bit data characters of Figure 8.

The central processing unit 700 operates again to generate another simple cache read command sent to the cache 750. In this case, the ZAC command specifies the address 1001 to extract the second operand word 1 ( descriptor 1) As a consequence of the transmission of the prefetch command in the cache unit, this second word is also found in the cache memory

As FIG. 10 indicates, the processing unit 700, via its test and connection circuits, checks the state of the selected end indication flip-flop EXE11 via a register vector branching operation (i.e., RIDW) 722-106. If this indication rocker is not set to one, the processing unit 700 launches an operating cycle B13. During the cycle, the first operand word 2 is transferred from the RDI register 704-164 to the register 0P2 of a block of character unit 720-10 via the execution unit 714. '

139

The AXP 722-72 adder then subtracts the value stored in the RXPB register indicating the number of characters per word from the current descriptor length value 1 (14) which is stored in the RXPD register and stores the result (10) in the RXPD register via the ZXP 722-62 switch. If the output signal from the AXP722-72 adder is not ZERO (that is, the AXPZ indicator or the carry signal is not ZERO), the EXH11 end switch remains to zero. During this cycle, the second word of operand 1 (address 1001) read from the cache unit 750 and sent over the ZDI lines is loaded into the RDI register 704-164.

The constant value 117g is generated by the adder AP 722-34 and it is loaded into the register RP5 via the switch ZRPB 722-24. This value serves as the start address of the interpreter memory for transferring operand data 2 into the character unit 720. Finally, the processing unit 700 loads the registers RDESC and RBASB, 704-140 and 704-144 , with the value ”00”, under microprogrammed command, to select descriptor operation registers 1.

As shown in FIG. 10, the processing unit initiates a sequence of two micro-instructions which includes cycles B14 and B15. This sequence is used to load the interpreter memory 714-30 of the remaining operand data descriptor 1 characters. The interpreter memory 714-30 can store up to 63 characters. If the length of the string is 16 characters of data or 4 words, the sequence is repeated several times.

During the first passage in the cycle B14, the processing unit 700 transfers, under the command of a microinstruction word having a format in which AACU = O, the second operand word 1 of the register RDI 750-164 in the RSPB memory input register interprets via ZRESB switch 714-38. Once again, the adder 704-322 advances the content read in the TEAO register by one and the result is returned in this register. The adder 704-320 also adds the increased value to the content of the TBASEO register and the resulting address is stored in the RADO register 704-46 by the lines ASFA.

140

The address (1002) which points to the third operand data word 1 is included in another simple read command which is generated and transmitted to the cache unit 750.

This data word is also found in cache memory 750-700.

The adder AP 722-34, figure 10, advances by one the contents of register RP5 and the resulting address by 120_Q

Descriptor Q is re-entered in the register RP5 by the intermediary of the switch ZRPS 722-24 and in the address register 10 is RSPA of the interpreter memory 722-102, via the switch ZSPA 722-100. The processing unit 700 loads, under microprogrammed control (NXTD area), the value 102 ”ⁱⁿ RDESC and RBASB registers, 704-140 and 704-144. This value specifies the selection of descriptor 3 maneuver registers (i.e., TBASEA, ICBA) and remains unused until the data words are loaded into interpreter memory 714-30. This value in cycle B15 is used to select the descriptor 1 operating registers (value OO ”) to generate other descriptor 1 addresses.

In FIG. 10, the processing unit 700 searches for the end or exhaustion of the operand data chain 1 in a previous cycle by examining the states of the adder indicators AP to detect whether the adder output signal was to ZERO or if there was no carryover. If the operand data string 1 is not finished or exhausted, the central processing unit 700 begins the cycle B15. During cycle B15, the adder ÂXP 722-72 subtracts the number of characters per word value stored in the RXPB register from the current value of descriptor length 1 (10) stored in the register, and stores the result ( 6) in the RXPD register via the ZXP 722-62 switch. The resulting length value_Λ if te is checked ei / ell® is still not at ZERO, the rocker at ^ end EXH11 remains at zero.

The third operand word 1 sent by the an35 unit memory 750 on the ZDO lines is then loaded into the EDI register 750-164 and it is then stored in the RSPB interpreter memory buffer 714-32 to be recorded in the location specified by a 120g address stored in the RSPA register 722-102

141

The adder indicators AP are still selected for a next test and the registers RDESC and RBASB are set to 00 to select the descriptor operation registers 1.

The processing unit 700 returns to cycle B14 and repeats the indicated operations which result from the generation of the second group of values. The processing unit 700 then repeats the operations in the cycle B15 to produce the second group of represented values. This is followed by another passage in cycles B 14 and B15 to produce the third group of values.

During the third passage in the cycle B14, the processing unit 700 emits, under microprogrammed command, a simple read command in the direction of the cache memory unit 750 to extract the fifth word of operand data 1. As the Figure 8 indicates, this word is in the main memory 800 and not in the cache memory.

In response to the simple read command, the cache unit 750 operates to extract from the main memory 800 another block of data words corresponding to addresses 1004-1007 t ^ in a manner comparable to that which has been described. about the pre-read command. However, in this case, if the command is a simple read command, the cache unit 750 forces the line CPSTOPOO. to ZERO binary. This25 forces the signals IH0LD00 and EH0LD00 to binary ZEROS to stop the operation of the central processing unit 700.

Thus, if the contents of all the registers of the processing unit cannot be modified, the processing unit 700 remains in the same state until the cache memory unit 750 has extracted the data words requested. When the cache unit 750 thus receives the data words which include the addressed words, it forces a DATA RECOV control signal to a binary ONE which in turn resets the state flip-flop RBPSD setting the processing unit 700 off-circuit. As a result, the cache unit 750 forces the line

CPSTOPOO has ONE binary to allow the processing unit 700 to continue operating.

142

The efficiency with which the instructions are executed is not modified if the processing unit stops operating until the unit 700 is at a processing point of the EDIT instruction where it needs the data. requested without being able to perform another operation. In cases where the processing unit 700 can start another operation, it may be advantageous to allow the generation of other pre-read commands during the execution of cycles B14 and B15.

Of course, when the operand data string 1 is made up of 16 characters or less, the generation of the simple prefetch command under hardware command is sufficient.

During the third passage in cycle B15, if the AXP 722-72 adder subtracts the number of characters per word value stored in the RXPB register from the current descriptor length value 1 (2) stored in the RXPD register, the result is negative and there is therefore no carryover. As a result, the end flip-flop EXH11 switches to ONE binary, just as a connection to cycle B16 follows the completion of a fourth cycle B14.

It can be seen in FIG. 10 that, during the third pass in the cycle B15, the fifth data word obtained from the main memory 800 by the cache unit 750 is loaded into the register RDI 704-164. Similarly, the negative result generated by the adder AXP 722-72 causes the binary of the end flip EXH11 to be set to ONE. The fourth data word previously stored in the RSPB buffer register 714-32 is written in the location of the interpreter memory 714-30 having the address 1003. Following the selection of the adder indicators AXP, and the loading of the registers 704-140 and 704144, the processing unit 700 begins its last passage in the cycle B14. .

During the last cycle B14, the processing unit 700 repeats the operations indicated to produce the fourth group of values ​​indicated in FIG. 10. In a few words, the unit loads the fifth data word (1004) into the buffer register RSPB 714-32, advances by one and stores the interpreter memory address in the RP5 and RSPA registers. However, if the EXH11 end scale is previously set to one,

143 the processing unit 700 prevents the generation of another simple read command specified by the small CU area of ​​the micro-instruction word. This is how the end or exhaustion condition leads to the application on the DMEM lines of a code consisting of ZEROS. The processing unit 700 then sets the value 10g in the RDESC and RBASB registers to perform the reading. descriptor maneuver registers 3.

At the end of cycle B14, the processing unit 700 connects to cycle B16 in which it writes the last word of the operand data chain 1 at the location designated by an address of memory interpreter 123g. This cycle is followed by a cycle W8 during which the lengths of the two operands 1 and 2 are controlled by the intermediary of the adders AL and AXP, 722-92 and 722-72, to verify that neither the operand 1 nor the opé15 rande 2 does not have a null number of characters indicating a fault condition. If this is not the case, no indication of fault is generated.

The processing unit 700 reads the descriptor start address content 3 from the ICBA register. The adder 70420 322 reduces the ICBA address value by one and the resulting address is loaded back into the ICBA register. Before being used, the same address is increased by one during the execution by the cycle processing unit of a common fitness program. The resulting address is transferred through the middle of the ZZ switch 704-328 and the ZDO switch 704-340 to the register RTRH7 of the execution unit register block 714-10 for storage there. At the end of this cycle, the processing unit 700 performs a vector connection of the content of the register R1DW 722-106 which corresponds to the value TA3 stored in the locations 21-23 of the register RSIR 704-154 where it was transferred for the FP0P3 cycle.

The processing unit 700 then begins an operation cycle 02. During this cycle, the unit 700 subtracts, using the adder AP 722-34, the descriptor start character pointer value 3 ”0” read from the RPO register, from the constant value of 4 which specifies the number of characters per word of operand data 3. The result of 4 is then stored in the register RP2. In addition, the pointer value of carac2425110

144 tère read in the RPO register is registered in the RP6 register. The AXPZ indicator of the AXP adder is selected to control the length of operand 1 during subsequent cycles. The state of this indicator, as established in the W8 cycle, is stored in a historical register HR4, not shown, to allow another control thereof.

As can be seen in FIG. 10, the processing unit 700 executes another vector branching operation using the content TA3 of the register R1DW 722-106 and initiates a cycle DI (9-bit characters) to start the execution a MOP preparation operation. During this cycle, a constant value OllOg ”or 6 is loaded into the register RRDXB via the switch 704-188 to select the register RAAÜ by the bloe704-5 in order to use it in the execution unit 714 during subsequent cycles.

The content of register 0P2 is read from block 72010 and the first character MOP selected by the content of register RCN2 720-30 is loaded into register RMOP 720-70 and into register RIF 720-63 via the switch ZCV 720-18. In this example, the EDIT statement is to replace zeros with asterisk characters. The RMOP register 720-70 therefore stores the micro-operation code specifying the replacement of characters 0 on the left with asterisks. The RIF register 720-63 stores information defining the length of. the operand zone 1 on which this microoperation code operation will relate. In this example, this character is used to process 3 operand 1 characters.

The value memorized in the register RCN2 720-30 is then checked against an overflow of capacity by conditioning an adder 720-34 so that it adds to this value the value of oC- = 2. The result is reloaded in the register RCN2 720-30. When the register RCN2 720-30 points to a character number 3 of a word 3002 of operand 2, the detector 720-38 forces the output signal CN20VF to binary DR. This means that at this time another operand word 2 is necessary to have a minimum of 4 words memorized and ready to be processed. We can see this in Figure 7.

145

Input bits 0-4 8 of the shaping insertion table previously stored in a table input register 1 of a unit register block 720-10 are then read during the cycle of next operation and are loaded into register RTE 8 720-68. An indication of the CN20VF condition detected during this cycle is also stored in a history register, not shown, for control during a following operation cycle. The CN20VF indicator is also selected for control, under microprogrammed command, during a next connection operation.

At the end of the DI cycle, the operand length 1 is checked via the AXP adder indicator (AXPZ). If the length is not zero, the processing unit 700 begins a cycle D2. During this cycle, the adder AL 722-92 causes the value of operand length 2 read in the register RLN2 to be reduced by one and reloads the resulting value of 5 in the register RLN2. A constant value of 27 is then generated via the adder AP 722-34 and loaded as an offset account in the register RSC 722-40 just as it is entered in the register RP7 via the ZRPB 722-24 switch. This is prepared to perform an offset operation by an execution unit offset circuit 714-24. The shift circuit 714-24 comprises two registers whose contents are offset from one another. By shifting 27 bit positions, you can select a value equal to one data character corresponding to the 9 most significant bits.

The processing unit 700 then puts, under microprogrammed command, the registers RDESC and RBASB, 704-140 and 704-144, at the value ”0l '' to select the operating commands of descriptor 2. At the end of this cycle , the processing unit 700 performs a conditional vector branching operation based on the state of the capacity overflow indicator CN2.

If this indicator being previously set to one, the processing unit 700 begins an operation cycle D3.

As can be seen in Figure 10, during cycle D3, the adder 704-322 advances by one (1 word) the descriptor address 2 read in the register TEA1 and reloads the resulting address in the register TEA1 . The word address resul2425110

146 aunt 3003 is added to the base value read in the TBASE1 register by an adder 704-320 and the result is then loaded into the RADO register 704-46. The processing unit 700 then generates a simple cache read command to extract the second word from operand 2 since this word is immediately necessary for processing. As FIG. 7 indicates, this word which includes characters 1 to 4 was previously read in the cache memory 750-700 in response to the pre-read command generated by the hardware. From now on, the processing unit 700 can continue to operate and the cache unit 750 ensures the extraction of the requested word and its transmission by the ZDO lines.

During cycle D3, the current value of the operand length 2 is read in the register RLN2 and it is checked with respect to zero by the adder AL 722-92. If the value is 5, the adder ALZ flag AL is not set to ONE binary. In this case, the indicator is selected for control during a following cycle.

The next cycle is a cycle D10 during which the adder AL 722-92 causes the value 5 of operand length 2 read in the register RLN2 to regress by 4 to verify whether operand 2 is exhausted. If the value is not zero, the output indicators ALZ of adder A1 or the absence of carryover prevent the flip-flop EXH2 from being set to ONE binary. The second operand word (3003) 2 read from cache memory 750-700 is loaded into the RDI register 704-164.

The adder 704-322 then advances the descriptor address 2 read from the TEA1 register by 4 words. The adder 704-320 adds the value read from the TBASE1 register to the incremented address and the resulting address is loaded into the RADO register 704-46. However, the address value remains unchanged in the TEA1 register. The processing unit 700 generates, under micro-programmed command, a pre-read command (0110) in accordance with the coding of the zone MEM of the zone of small CU of a micro-instruction word having a format 1. The format 1 is used because it lends itself to a more complete control of the auxiliary unit 722. However, it will be noted that the pre-read command could also have been generated by a micro2425110

147 instruction, having the alternate format shown in Figure 6b.

The pre-read command extracts the next block of 4 words (addresses 3004-3007). If the ZAC command specifies the address 3007, the cache unit 750 allows the memory, by transmitting this ZAC command to the main memory 800, to read the data block which includes the specified word.

As already explained, while the cache unit 750 processes the pre-read command generated under microprogrammed command, the processing unit 700 is authorized to continue the execution of the shaping instruction . This is how cache 750 maintains the CPSTOPOO line at ONE binary. This in turn accelerates the execution of the shaping instruction.

It can be seen in FIG. 10 that the processing unit 700 performs a conditional vector connection based on the state of the indicator ALZ of adder AL. If the operand length 2 is not zero, the processing unit 700 begins an operation cycle DU. In this cycle, the second operand word 2 (at address 3003 in FIG. 7), stored in the RDI register 704-164, is loaded into the 0P2 register of block 720-10 via the ALU 714-20 execution unit on ZRESA lines.

At the end of the cycle DU, the processing unit 700 executes a conditional vector branching operation based on the value TA3 stored in the register RIDW 722-106. The result is that the processing unit 700 begins an operation cycle E1 in which the character unit 720 performs the execution of the type of shaping operation specified by the coding of the first control character MOP.

During the cycle El, the adder AXP 722-72 causes the value of operand length 1 read in the register RXPA to decrease by one, under the command of a micro-instruction word having a format AACU = 3, the resulting value (15) being reloaded again in the RXPÂ register. Likewise, the adder AL 72292 causes the operand length value 3 read in the register RLN1 to regress by one, the resulting value (P6) being again reloaded in the register RLN1. In addition, the adder

148

AP 722-34 causes the complement of the value CN3 read in the register RP2 to be reduced by 1 and the resulting value is again reloaded in the register RP2 „

The content of the register RCN1 720-38 is updated, under hardware control, to the value &lt;= 2 (010) via the adder 720-34 indicating the selection of the next 9-bit character. The remaining bit will be ignored only if the two most significant bits are used, so that the progress value = 1 will appear ^^. The contents of the RCN2-30 register are kept at ZERO until the value stored in the RIF register 720-03 has decreased to ZERO.

As can be seen in FIG. 10, the number (3) indicating the remaining characters to be processed by the first control character MOP stored in the RIF register 720-63 regresses by 1 through the circuit 720-60 and the result is reloaded in the register.

The decoder 720-74 works to decode the command character MOP and generate signals to control the operation of the character unit 720. During operation, the first character is read in the register 0P1 and when it is NULL like the detector 720-82 indicates this, it is replaced by the asterisk character read in the second character location of the input register 1 of table of block 720-20. If the first data character is NULL as shown in Figure 8, the asterisk character is selected via the ZOC switch 720-20 and loaded into the RAAU register 722-46 via a switch 722-44.

The processing unit 700 also sets up, under microprogrammed control, the registers RVBO and RVBZ according to the states of the indicators of MOP, ΜΟΡΙΑ and MOPIB, for subsequently carrying out connection operations. The indicator ΜΟΡΙΑ signals to the processing unit 700 that it can continue the execution of MOP execution cycles, to process the next MOP command character and to determine if processing should be continued using the same character MOP., The MOPIB indicator signals to the processing unit 700 that it must complete the operations. In addition, several historical registers, not shown, HRO.l and 3 are set to one depending on the states of the indica2425110

149 CNIOVF, CN2OVF and END order teurs for a following test.

The values ​​are then ZEROS.

As can be seen in FIG. 10, the processing unit 700 begins an operation cycle E2 during which the asterisks of the content of the RAAU register 722-46 are sent on the lines ZEB via the switch ZXB2 70459 d 'a block 704-5. From there, the asterisk character is sent to the shift circuit 714-24 via the ZOPB switch 714-17 while the contents of the TRO register are trans10 set by the ZOPA switch 714-15 and by the switch 714- 28.

The shift circuit 714-24 shifts these signals by 27 bit positions Under the control of the shift count of the unit 722.

The shifted result which corresponds to the first character of operand 3 of FIG. 8 is then loaded into the register TRO via the switch ZRESBO 714-38.

At the end of the cycle E2, the processing unit 700 checks the state of the control indicator ΜΟΡΙΑ by a vector connection operation. If the value ΜΟΡΙΑ is 00, the processing unit 700 begins a cycle F1 followed by an operation cycle F2. During the cycle F1, the processing unit 700 performs operations similar to those performed during the previous operation cycle El. This results in the group of values ​​indicated. That is, the registers RXPA, RLN1 and RP2 store the values ​​14, 14 and 2 respectively.

Likewise, during the cycle F1, the character unit adder advances the register RCN1 720-28 by one, under hardware control, which results in the storage of a condition C'NLOVF in a historical register HRO, not shown, for further testing. This indicates that the second word of o30 perande 1 is necessary to be extracted from the interpreter memory 714-30 and stored in the register 0P1. The RCN2 720-30 register remains at ZERO and the RIF register, after having regressed its content, stores the value 1 ”. An asterisk character is once again selected using the ZOC 720-20 switch to place the second NUL data character of operand 1. The vector branch registers RVBO and RVB2 are set to one according to the indicators ΜΟΡΙΑ and

242511©

150

MOPIB, respectively. The RVBO register is set to 010 to signal the verification of a CN10VF condition. The RGB2 register is set to 10 to indicate that the indicators must be checked during a next operating cycle.

During the F2 cycle, the second asterisk character is sent on the ZEB lines via the ZXB2 switch 704-59 from the RAAU register 722-46. The contents of the TRO register and the asterisk character are sent again to the inputs of the shift circuit 714-24, in which they are shifted by 27 bit positions, the result being stored in the TRO register. The result corresponds to the first two operand characters 3, indicated in FIG. 8. At the end of the cycle F2, the indicator ΜΟΡΙΑ is checked by a conditional branching operation and the processing unit 700 begins a cycle F4.

During the cycle F4, the processing unit 700 prepares, under microprogrammed command, the states of the various indicators for a next connection operation. Indications such as: • a negative overflow L1, a negative overflow L3 and a positive overflow CN3 are established by reading the contents of the registers RXPA, RLN1 and RP2 by the adders AXP, AL and AP and by memorizing the 'state of the output indicators to ZERO of adder (AXPZ, ALZ and APZ) in historical registers HR4, 5 and 7, not shown. The AXPZ and ALZ indicators are selected and the RGB2 register is set to one by the TA3 content of the R1DW 722-106 register.

At the end of the cycle F4, the processing unit 700 performs a vector connection operation based on the state of the MOPIB indicator and launches a cycle J1. During this cycle, the memory register CN10VF (HRO) is selected for control. At the end of this cycle, the processing unit 700 performs a connection based on the state of the previously selected adder indicators AXPZ and ALZ. If none of the lengths of operands 1 and 3 were at zero, the processing unit 700 starts a cycle J7.

During cycle J7, the processing unit loaded, under microprogrammed command, the memory address interpreter

151 for operand 1, read in the register RP3, in the register RSPA 722-102 via the adder AP 722-34. The processing unit 700 also selects the end indicator memory register, HR3, not shown, for later checking. At the end of the cycle J7, the processing unit 700 performs a connection based on the memorized state of the indicator CNIOVF. If the indicator is not previously set to one, the processing unit | launches a cycle PI.

During the PI cycle, the second operand word 1, previously stored at address 1001, is read at address 120θ of the interpreter memory 714-30 and it is loaded into register 0P1 of block 720-10 with l through the ZRESA lines. As FIG. 8 indicates, this word comprises the data characters 4060 in which the formatting of the first character is carried out under the control of the first control character MOP while the formatting of the three following characters is carried out under the command of the following MOP command character of FIG. 8.

During the PI cycle, the operand interpreter memory address value 1 is also read in the register RP3, the adder AP 722-34 advances it by one and the resulting address 121g is reloaded in the register RP3 by Via the ZRPC 722-32 switch. The processing unit 700 also selects, for a subsequent control, the historical register HR7 which stores the state CN30VF.

At the end of the PI cycle, the processing unit 700 performs a branching operation based on the result of checking the state of the end indicator. If this indicator is not set to one, the processing unit 700 initiates a cycle P2. During this cycle, the operand length 1 stored in the RXPA register is checked with respect to zero by the AXP 722-72 adder to detect a fault condition. The offset constant 27, stored in the register RP7, is loaded into the register RSC 722-40 to control the shift circuit 71424 during subsequent operating cycles.

At the end of the cycle P2, the processing unit 700 performs a conditional vector branching operation based on the state of the condition CN30VF previously selected for

152 a control. If a positive capacity overflow condition CN3 has not been detected, the processing unit 700 begins another MOP sequence starting with the cycle F1 which is followed by another cycle E2.

During the cycle E1, the processing unit 700 sets the registers EXPA, RLN1 and RP2 to the values ​​13, 13 and 1 respectively, according to the representation in FIG. 10. Under control of the hardware, the register RCN1 720-28 progresses again with a value 01, the. register RCN2 720-34 remains at the same value and a value stored in the register RIF 720-63 decreases to ZERO. The regression of the content of the RIF register to ZERO results in the loading in the RGB2 register of a value of 01 of ΜΟΡΙΑ. The processing unit 700 can thus read the following control character MOP which corresponds to the operand character 2 at an address 3003 previously entered in the register 0P2 during the cycle DU.

Since there is no null character detected, the data character having the value 4 ”is selected by means of the ZOC switch 720-20 for loading into the RAAU register 722-46. The result of the micro-operation specified by the content of the register RMOP 720-70, indicated by the states of the indicators ΜΟΡΙΑ, MOPIB and END, is stored in historical registers HRO, 1 and 3 for later control during an operating cycle following.

During the second cycle E2, the data character 4 is sent on the ZEB lines via the switch ZXBZ 704-58. The data character and the contents of the TRO register transmitted to the shift circuit 714-24 are shifted by 27 bit locations to the left and the result is rewritten in the TRO register. At this time, the register contains the values ​​4 and the register RP2 contains the value ”1”. These indicate that one more operand data character 1 can be processed and stored in the TRO register.

At the end of the cycle E2, the processing unit 700 performs another vector connection operation based on the states of the indicators ΜΟΡΙΑ. Since the value is ”01”, unit 700 now begins an F3 cycle. During this cycle, the ad2425110¹⁵³ Alder 722-92 controls the value 5 stored in the register RLN2 which indicates the number of operand characters 2 remaining (L2) to detect a fault condition. The AXP 722-22 adder also controls the value 13 stored in the RXPA register which indicates the number of characters remaining in operand 1 or descriptor data area 1 (L1). The result of this check is signified by the state of the indicator AXPZ which the processing unit 700 selects for a check during a following cycle.

After the loading of the value TA3, memorized in the register RlDW 722-106, in the register RGB2, the unit 700 performs another vector connection operation and begins another operating cycle DI. Since the unit 700 performs the same operations as those previously described, only the appropriate results will be explained with respect to the cycles described above.

During this cycle, the character of number O of the descriptor word 2 stored at address 3003 is selected by a switch ZCV 720-18 and loaded into the register RMOP 720-70 ^the register RIF 720-63 when the word is read in the register DP2. In addition, the value stored in the register RCN2 720-30 progresses from OOg to 01₂ to designate the character of number 1 as the next MOP command character to be read in the 0P2 register.

During the cycle D2, the unit 700 causes the content of the register RLN2 to regress in a solid fashion so that it indicates that there are 4 additional MOP command operand 2 characters to be processed. As can be seen in FIG. 10, if there is no overshoot of positive capacity CN2, the unit 700 starts another cycle El. During this cycle, the values ​​of L1 and L3 stored in the registers RXPA and RLN1 regress to 12. The value stored in the RP2 register also decreases to ZERO, which indicates that the TRO register now stores a complete word of 4 characters which could be written to the first location of the operand data area.

3.

Under material control, the value stored in the RCN1 register is raised to the value "102" indicates that

154 the data character ”6 is the next character to be selected from register 0P1. The register SCN2 720-30 remains at ”01” indicating the next MOP command character while the content of the RIF register decreases from a value 3 to the value 2. This indicates that 2 characters of operand data 1 must be processed by the MOP command character currently stored.

Since the selected data character is a ZERO, the ZOC switch 720-20 is conditioned by the logic control circuits 720-76 to select another asterisk character to be loaded into the RAAU register 722-46. This results in a replacement of character number 1 at an address 1001, in FIG. 8, with an asterisk.

Since the value memorized in the register RP2 is ZERO, the processing unit 700 sets the indicators ΜΟΡΙΑ and MOPIB to the value ”01₂”. During the following E2 cycle, the asterisk character is loaded into the TRO register. At this time, the TRO register stores the values ​​4. As described above, the unit 700 begins a second cycle F4 which depends on the state of the indicators ΜΟΡΙΑ and MOPIB. During this cycle, the content of register RP2 is checked with respect to zero and the historical register HR7 is set to one to indicate the production of a CN30VF condition (RP2 = 0). The unit 700 then begins a second cycle J1 during which the memorized state of the ŒIOVF (HRO) indicator is selected for control during a subsequent cycle. The processing unit 700 begins a second cycle J7 during which the registers RDESC and RBASA, 704-140 and 704-144, are reset to the value 10g for the selection of descriptor operation registers 3.

Since there was no condition of capacity overflow CN1, the unit 700 begins a first cycle J8. During this cycle, the descriptor address 3 (4777) read in the ICBA register increases by 1 (word) under the effect of an adder 704-322 and the result (5000) is re-entered in the ICBA register. The base value stored at address 5000 of IBASE A register is added to address 5000 by an adder 704320 and the resulting address 5000 is loaded into RADO register 704-46. Unit 700 generates a simple write command

155 zone under firmware control. In particular, the unit 700 forces bits 5-8 to a value 1111 specifying the bytes of the word to be written to an address 5000 in response to the write command. In addition, the processing unit 700 forces, under microprogrammed command, command bits 1-4 to a code.

1000 specifying that the ZAC command is a zone command of a simple write type. The ZAC command is transmitted to the cache unit 750 for processing.

In addition, the processing unit 700 forces, under the command of the MEMADR area, the DMEM lines to a code 1100 which tells the cache unit 750 that a simple writing operation must be carried out. In addition, unit 700 forces the DREQCAC line to ONE binary to signal the command to the cache unit. Unit 700 causes the value of operand length 3 stored in register RLN3 to be reduced by 4 by the adder

AL 722-92 and re-writes the resulting value ”12” in the register RLN3. The processing unit 700 then performs a vector connection operation as a function of the value of the area TA3 stored in the register RIDW 722-106 and begins a first cycle Q1.

During the Ql cycle, the first data word of descriptor 3 (4) is read from the TRO register and loaded into the RADO register 704-46 by the arithmetic and logic unit ALU 714-20 and the ZRESB lines. The AP 722-34 adder then loads a value 4 into the register RP2 which is used to count the next 4 characters to be entered in the register TR4. The RP6 register is responsible for ZEROS as it was previously.

At the end of the Ql cycle, the processing unit 700 performs a branching operation which depends on the state of the status bit END 30 of indicator flag previously stored. Since the indicator is not set to one, the unit 700 returns to a cycle E1 by a vector branching operation dependent on the zone value TA3 stored in the register RIDW 722-106.

The cache unit 750 processes the simple write command in a manner similar to that used in processing a read command. In particular, cache unit 750 loads, in response to the DREQCAC line set to ONE binary, the command word ZAC transferred to the register RADO 704-46

156 by unit 700 during cycle J8, in the first location of buffer WZAC 750-100. The write address counter 750104 has its content which increases by one. The data word read in the TRO register is loaded into the RADO register 704-46 pendan? / The Ql cycle is written in the second location of the buffer WZAC 750-100.

Signals sent by RADO lines access the directories in cache memory 750-700 as described above. Assuming that the block including address 5000 is not in cache 750 the match / no match detector circuits 750-560 do not force the BPSD line to ONE binary.

The decoding of the simple write command by the decoder 750-166 makes it possible to put the flip-flops of command state UGCOGTH and CAOPR to binary states UN. Once the UGCOGTH flip-flop is set to one, the data word of the processing unit 700 can be written into the cache memory 750-700 when the block containing the word is in the cache memory. The CAOPR flip-flop forces the AOPR line to ONE binary when it is set to one. At this time, the first ZAC command word is loaded into the ZIU 750-174 output register.

In addition, the cache unit 750 sets the flip-flop UGSOGTH to a binary when it receives by the line ARA a signal to ONE binary coming from the SIU IOO unit. The cache unit 750 terminates the operation by loading the data word into the output register ZIU which remains on the lines DIS until a next clock pulse occurs.

Since the cache command was a write command, the processing unit 700 can continue to execute the formatting instruction which follows the end of transfer of the data part of the command. As can be seen in FIG. 10, the processing unit 700 begins a fourth cycle El. This results in the setting of the registers RXPA, RLN1 and RP2 at values ​​11, 11 and 3, respectively, by the unit 722 .

In addition, the register RCNI 720-28 is set to the value llg while the register RCN2 720-30 remains at the value Olg · The register RIF 720-63 according to the regression of value stores the value 1. The data character d operand 1 number 2 having the value 6

157 is selected by the ZOC switch 720-20 to be transferred to the RAAU register 722-46 on reading the content of the operand register 2 OP 2.

During the fourth cycle E2, the selected data character which is sent on the lines ZEB is shifted by the shift circuit 714-24 and the result 6 is rewritten in the register TRO. The unit 700 makes a connection to start a fourth cycle F1 followed by the cycles F4,

Jl, J7 and Pl.

During the F1 cycle, the registers are positioned as follows: RXPA = 10; RLN1 = 10; RP2 = 2; RCN1 = 00, RCN2 = 01 and RIF - 0. The status bit of the positive capacity overflow indicator CN1 produced by RCN1 = O is stored in the history register, HRO not shown. The status bit of the END indicator produced by RIF = O is stored in the historical register, HR3, not shown.

In addition, the operand data character 1 number 3 having the value ”0 is selected by the switch ZOC 72020 to be transferred to the register.RAAU 722-46 on reading the contents of the register 0P2. Since the character 0 ”appears to the right of a non-zero data character, an asterisk character is not substituted for the data character” 0,

During cycle F2, the character 0 is stored in the TRO register with the resulting content 60 ”. During cycle J7, the interpreter memory address value 121g is loaded into the RSPA register 722-102 and the third descriptor word 1 at an address 1002 is loaded into the register 0P1, during a cycle Pl, from the addressed location (121g) of the memory interpreter 714-30. During the cycle Pl, the address of the interpreter memory also progresses by one and the resulting address 122g is re-written in the register RP3.

As can be seen in FIG. 10, since the END indicator was not at one during a previous cycle, the unit 700 makes a connection to start a first cycle P4. During this cycle, the processing unit 700 controls the length of operand 2 with respect to zero to detect a fault condition. During the rest of the cycle, operations identical to those of cycle P2 are performed. The unit 700 then begins another cycle D1, followed by the cycles D2, El; E2, Fl, F2, F4, J7, J8 and Ql.

158

In summary, during the cycle D1, the next character MOP (character number 1 -3003) is loaded into the registers RMOP and RIF and the register RCN2 progresses by a value 10g. During a cycle D2, the processing unit 700 controls the end of the operand zone 2 and causes the content of the register RLN2 to regress to a value 3. During the cycle the registers are set to the following values: RXPA, RLN1 =? , / RCNl = Olgî RCN2 = 10 ^ and RIF = 2. In addition, the operand data character 1 number 0 having the value 1 is selected to be loaded into the RAAU register.

During the cycle E2, the data character is entered in the register TRO which then stores the value 601. During the cycle F1, the registers mentioned above are positioned as follows: RXPA, RLN1 = 8; RP2 = 0; RCN1 = lOgî RCN2 = lOg and RIF = 1. In addition, the operand data character 1 number I having the value 2 is selected to be loaded into the RAAU register. During the cycle F2, the data character is entered in the register TRO which then contains a complete word 6012.

Consequently, during cycle J7, the registers RDESC and RBASB are set to the value “10 to select temporary registers of descriptor 3. During cycle J8, the unit 700 loads the address 5001 in the register ICBA and in the RABQ register. Another simple write command for an area is generated and transferred to the cache unit 750.

Furthermore, the register RLN3 has its content regressing to the value 8. During the cycle Q1, the data word corresponding to the second descriptor word F3 is loaded into the RADO register to be transmitted to the cache memory unit 750. As a result, the value 6012 is entered at the location having the address 5001.

The Ql cycle is followed by the El, E2, F3, Dl and D2 cycles. In summary, during the cycle E1, the different registers are set to the following values: RXPA, RLN1 = 7; RP2 = 3;

RCN1 = II2 î RCN2 = 10₂ and RIF = 0. In addition, an operand data character 1 number 2 with a value 0 is selected to be loaded into the RAAU register. During the E2 cycle, the data character is entered in the TRO register.

159

During cycle F3, the indicators L1 and L2 are checked against the value O.

The next MOP character (character number 2 - 3003) is loaded into the RMOP and RIF registers during the Dl cycle.

In addition, the RCN2 register progresses to the value llg. During the cycle D2, the register RLN2 regresses to the value 2. The cycle D2 is followed by the cycles El, E2, F4, Jl, J7 and PI.

. During the El cycle, the registers are set to the following values: RXPA, RLN1 = 6, RP2 = 2; RCR1 = OOg (which signed a condition CN1OVF); RCN2 = 11 ^ and RIF = 2. In addition, an asterisk character is selected to be loaded into the RAAU register in place of a data character number 3 (1002) having a zero value. During the E2 cycle, the asterisk character is entered in the TRO register which then stores the value θ '.

During the PI cycle, the next data word of operand 1 containing the value 1357 is read at location 122θ of the interpreter memory 714-30 by the register 0P1. In addition, - the interpreter memory address increases by one and the result

123θ is re-entered in the register RP3.

The PI cycle is followed by the El, E2, Fl, F2, F4, Jl, J7, J8, Q1 and Q2 cycles. During the E1 cycle, the registers are positioned as follows: RXPA, RLN1 = 5; RP2 = 1; RCN1 = 01₂;

RCN2 = llg and RIF = 1. In addition, the data character number

0 (1003) of operand 1 having a value 1 is selected to be loaded into the RAAU register. During the E2 cycle, this character is entered in the TRO register which then stores the values ​​0

During cycle F3, the previous registers are set to the following values: RXPA, RLN1 = 4; RP2 = 0, RCN1 = 10₂;

RCN2 = llg and RIF = 0 (signaling the end for this MOP character).

In addition, the data character number 1 having the value 3 is selected to be loaded into the RAAU register. In addition, the flag status bit is loaded into the histori35 register as HR3. During the F2 cycle, the data character is entered in the TRO register which then contains the values ​​0 *

13.

160

2425Π0

During the J7 cycle, the RDESC and RBASB registers are set to 10 to select the temporary description registers 3. During the J8 cycle, the descriptor address 35002 is loaded into the ICBA register and into the RADO register. At this time, the unit 700 generates another simple write command of an area for the cache unit 750 to write the third descriptor word 3 in the main memory 800. In addition, the register RLN3 has its content which regresses to the memorized value 4. During the cycle Q1, the content of the register TRO is loaded into the register RADO to be transferred to the cache memory 750. In addition, the register RP2 is reloaded with the value 4. During a Q2 cycle, the operand length 2 (L2) is checked.

Cycle Q2 is followed by cycles Dl, D2, D3, D10,

DU, El, E2, Fl, F2, F4, Jl, J7 and Pl. During the Dl cycle, the next command character number 3 (3003) is loaded into the registers RMOP and RIF 720-70 and 720-63. In addition, the register RCN2 720-30 progresses to the value 00 by which the indicator CN20VF is set to binary ONE.

During the cycle D2, the register regresses to the value 1 and the registers RDESC and RBASB, 704-140 and 704-144, are set to the value 01 to select temporary registers of descriptor 2. During the cycle D3, the processing unit 700 loads the address 3004 into the TEA register 1 and into the RADO register 704-46. The unit 700 again generates, under microprogrammed command, a simple read command for the cache memory 750 in order to extract the data word at the address 3004.

Since the block of 4 words comprising said word was extracted by cache 750 in response to a cache prefetch command, cache unit 750 forces the line BPSD to ONE binary indicating a match condition, when the completion of the directory search cycle. The line CPSTOPOO therefore remains at binary ONE, which allows the unit 700 to continue processing the shaping instruction.

161

During cycle D10, the value stored in the register RLN2 decreases by 4, which gives the value -2. This forces the non-carry flag to ONE binary which changes the EXH2 flag to ONE binary. The data word at the address

3004, including the value ”90 sent on the ZDI lines by the cache unit 750, is loaded into the RDI register 704164. The unit 700 advances the descriptor address 2 by 4 (words) and loads the resulting address 3008 in the RADO register 704-46. Another cache pre-read command specifying the reading of the next block of 4 words (addresses 30083011) is generated by the unit 700 under microprogrammed command.

It can be seen from the above that, by the use of pre-read commands, the processing unit 700 is able to carry out the shaping operation more quickly because the data of operand 2 necessary will always be put in advance in the cache memory 750-700 to make them available as soon as it is necessary for the unit 700. The unit 700 can thus continue processing without interruption.

During the DU cycle, the data word extracted by cache memory 750 is transferred from register RDI 704-164 into register 0P2 of the character unit 720. During the following cycle El, the registers are positioned as follows: RXPA ,

RLN1 = 3; RP2 = 3; RCN1 = 11₂; RCN2 = 00g and RIF - 2. In addition, the operand data character 1 number 2 with the value 5 ”is selected to be transferred to the RAAU register 622446. During the E2 cycle, the data character is shifted and entered in the TRO register.

The execution of the cycle F1 results from the setting of the preceding registers to the following values: RXPA, R1N1 = 2;

RP2 = 2; RCN1 = 00₂ (which signals a CnlOVF condition);

RŒ2 = 00g and RIF = 1. In addition, the operand data character 1 number 3 having the value ”7 is selected to be transferred to the RAAU register 722-46. During the F2 cycle, the data character is entered in the TRO register. Subsequently, during the PI cycle, the operand data word 1 at an address 1004, in Figure 8, which includes carac2425H0

162 data points 90 is read into the interpreter memory location with address I23_g and loaded into register 0P1.

The cycle Pl is followed by other series of cycles El,

E2, E3, Dl, D2, El, E2 and F4. When the cycle E1 is finished, the registers contain the following values: RXPA, RLN1 = 1; RP2 = 1, RCN1 = Olgî RCN2 = 00 and RIF = O (which signals that a new MOP character is necessary). During the E1 cycle, the operand data character 1 number 0 (address 1004) having the value 9 is selected to be transferred to the RAAU register 722-46. During the E2 cycle, the data character is entered in the TRO register which then stores the values ​​”579.

During the cycle D1, the following control character MOP, character number 0 in FIG. 8, is loaded into the registers RMOP and RIF, 720-70 and 720-63. In addition, the register RCN2 720-30 has its content which progresses to the value Olg. During the cycle D2, the register RLN2 has its content which regresses to the value 0. This indicates that the operand chain 2 has been exhausted (L2 = 0).

During the cycle E1, the last operand character 1 (character number 1 at an address 1004 in FIG. 8) is processed by the character unit 720. Since the character is the first character to be processed under the control of the character MOP command loaded in the RMOP register 720-70 during a Dl cycle, its zero value is detected and an asterisk character is selected to be loaded in the RAAU register 722-46. At the end of an El cycle, the register values ​​are as follows: RXPA, RLN1 = 0; RP2 = 0; RCN1 = 10_g; RCN2 = 01 ^ and RIF = 0 (the MOP character was coded to specify the processing of a character).

During an E2 cycle, the asterisk character is entered in the TRO register which then contains a complete word (ie 5790). During a cycle F4, it results from the control by the adders of the values ​​of the contents of the registers RXPA, RLN1 and RP2 that the indicators AXPZ, ALZ and APZ are set to binary UNS. The status bits of these indicators are stored in historical registers HR4, HR5 and

163

HR7, not shown. Furthermore, the zero value of the content of the register RP2 is stored in the register RP5.

The processing unit 700 then executes a cycle J1 during which the status bit of the indication CN1OVF (HRO) is selected for checking during a subsequent cycle. At the end of the Jl cycle, the states of the AXPZ and AL indicators are checked. If the two are one, the unit 700 proceeds to the sequence of a cycle J2.

During the cycle J2, the unit 700 selects the indicator ALZ (HR5) for control during a subsequent cycle and begins a cycle J3. As can be seen in Figure 10, the value 10g is loaded into RDESC and RBASB registers, 704-140 and 704-144, to select temporary operand registers 3. In addition, the END flag is selected for a check during a subsequent cycle.

At the end of the J3 cycle, the unit 700 performs a conditional vector connection operation depending on the state of the indicator ALZ. Since the indicator was at one, the unit 700 makes a connection to a cycle Q7 which depends on the content TA3 of the register R1DW 722-106. During the Q7 cycle, the unit 700 advances the descriptor address 3 read in the register 1CBA by one (word). The resulting address 5003 is re-entered in the ICBA register. In addition, this address is added to the TBASEA address by an adder 704-320 and the resulting address (5003) is loaded into the RADO register 704-46).

As can be seen in FIG. 10, the processing unit 700 generates a last simple write command for an area which is transmitted to the cache unit 750. At this time, the unit 700 sets the indicator EXH3 to ONE binary. In addition, the adder AP 722-34 generates a shifted account value by subtracting from the value (0) stored in the register RP5 from a constant value 36 the result loaded in the register RSC 722-40.

The processing unit 700 then begins a cycle Q8 during which the content of the register TRO is shifted by 36 bit positions via the shift circuit 714-24. The resulting data word with the values ​​579 = f ”is loaded into the RADO register 704-46 to be entered in the slot

425110

164 with address 5003 indicated in FIG. 8. As can be seen in FIG. 10, the unit 700 begins a cycle Q9 during which it resumes an execution of instruction in pipeline in response to a microinstruction word having the second format shown in Figure 6b.

More precisely, the PIPE area of ​​the micro-instruction word is coded to specify a type 1 recovery. By its decoding, the unit 700 sets the signal END to A binary which starts the start of the next instruction.

As can be seen from the preceding description, the system according to the present invention is capable of accelerating the execution of various instructions necessary for their execution by a data processing unit. By having a processing unit which executes sequences comprising pre-read commands for types of instructions whose execution can be facilitated, the overall performance of the data processing unit is increased.

Note that the object of the present invention does not relate to a particular way of microprogramming a given instruction. On the other hand, the microprogrammer is free to select cycles which would be coded to include a prefetch command.

According to the present invention, prefetch commands must be included in cycles in which advance calls to the cache unit for data can be made while the processing unit performs operations not requiring immediately use of data For example, as we can see, this can be achieved when the processing unit is generating addresses or executing a formatting or translation operation. Thus, according to the present invention, pre-read commands are generated under hardware command during the initial part of an instruction comprising several words, making it possible to generate the addresses of certain descriptors to be processed in parallel during the address calculation. other descriptors.

165

We will now describe the operation of the present invention with reference to Figures l-6b and ll-13d, and depending on the processing of several different types of instructions having formats shown in Figures 13a to

13d.

However, before giving an explanation of these instructions, we will first refer to the state diagram of FIG. 11. This diagram represents the sequencing of the memory circuits for command-cycle states I contained in the block

704-102 depending on the coding of the CCS sequence area sent by lines 704-210. As shown in Figure 11, the FPOA command state is a start state for processing all instructions.

The FPOA state is triggered when the FPOA control state flip-flop in block 704-102 of Figure 3 changes to Binary ONE. This rocker is put on a subcommand of the material in accordance with the following boolean expression: '_

SET TO ONE = [hOLDI. (DIBFRDY.DIBFEMTY.

£ STRCPR. DXEDRPTS.DPIPES.-4)

This is how the FPOA cycle is triggered following a ^ END cycle when there is no maintenance condition as far as pipeline operation is concerned (i.e., ui ^ signal HOLDI = 1), that the instruction buffer 750-900 is not empty (that is, DIBFEMTY = 1), that it has at least one instruction ready to be transferred to the unit 700 (i.e.,

DIBFRDY = 1), that the previous instruction did not produce a memory comparison condition (that is, STRCPR = 1), that the instruction is not a double execution instruction or repeat (i.e., DXEDRPTS = 1) and the pipeline operation has been restarted (i.e., DPIPE1-4 = 1).

In the FPOA control state, the register RBIR 704152 stores the instruction operation code as well as the rest of the instruction word having one of the formats represented in FIGS. 13a and 13b. In addition, the RSIR register 704-154 stores the same instruction word. In the case of an instruction having the format of FIG. 13a., The register RBASA 704-156 memorizes the three most significant bits of the zone y while the register RRDX-A 704-158 memorizes the part td of the zone Ins2425110 word tag

166

The flip-flop R 29 704-162 stores the value of bit AR 29 of the instruction word.

During the FPOA control status cycle, the circuits of a block 704-101 decode the CCS sequence area read from the CCS control memory 704-200 in response to the 10-bit operation code (bits 18 - 27) sent through the RBIR 704-152 register. It is the coding of the CCS sequence area which establishes the path to be followed for processing the instruction. Consequently, the coding of the CCS sequence area determines the types of operations carried out during the FPOA cycle and subsequent cycles which complete as much as possible the processing of each instruction under control of the hardware. Examples of particular operations are cited in the chapter Actions of control states by hardware included.

Considering the paths in more detail, it can be seen in FIG. 11 that the circuits of block 704-102 are sequenced from the FPOA state to the FTRF-NG control state when an FTRF-TST indication flip-flop indicates that the previous instruction was in the transfer class and that the condition for a transfer or a connection was not fulfilled ^ TRGO = 1). During the FTRF-NG control state cycle, the hardware circuits of the processing unit generate signals to reset the instruction buffer according to the content of the instruction counter. This allows the cessation of this instruction stream and a return to the present instruction stream whose address is indicated by the instruction buffer circuits. The FTRF-NG command status cycle is then followed by one of the FPI-INIT to FWF-IBUF cycles according to the coding of the buffer I status lines.

In the case of normal instruction processing, the path followed following the decoding of the CCS sequence zone is that designated FTRF-TST + ^ TRGO. This path indicates that the previous instruction was not inside the transfer class (FTRF-TST = 1.) Or that if it was in such a class, a transfer condition is about to be fulfilled (£ TRGO = 1). This path then indicates the continuation of the processing of a transfer class instruction under control of the material. Note that if the previous instruction was an instruc2425110

167 transfer class tion (FTRF-TSF = 1) and if the instruction presents a transfer class instruction (TFF), the hardware circuits of block 704-102 then remain in the FPOA command state cycle ( that is, they follow a TRF to FTRF-TSF path).

The point X in FIG. 11 indicates from the coding of the CCS sequence area whether the particular instruction is in the class EIS, in the class ESC or the class TRF.EA, in the class EIS. ESC. ^ EA. TRF or in the EIS class. ESC.QeA. In the case of the EIS class, the coding of the sequence area determines how many descriptors are required for this particular EIS instruction. Each of the EIS instructions has the multi-word format shown in Figure 13b and may require up to three descriptors. The CCS zones for all the instructions requiring one, two and three descriptors are grouped together inside the decoding circuits. Additionally, as soon as signals sent through the address lines of the instruction buffer circuits of the cache unit 750 are decoded to determine how many descriptor or word values ​​are currently stored in the buffer. instruction. These groups of signals are compared and, when there are not enough descriptors present in buffer I to complete the instruction, the circuits of block 704-102 then pass from the FPOA cycle to the control state cycle FPIM- EIS. During the FPIM-EIS control state cycle, the processing unit circuits generate signals to condition the cache unit 750 to execute an instruction retrieval operation to retrieve four more words main memory or auxiliary memory that are loaded into the instruction buffer.

Once the required numbers of descriptors have been retrieved and the cache unit 750 signals that the instruction buffer is ready (IBUFRDY = 1), the circuits of block 704102 are ^ at point C. If the buffer d the instruction is not ready (IBUF-RDY = I), the hardware circuits 704-102 pass to the command state cycle FWF-DESC in which the processing unit 700 awaits the descriptor. When the instruction buffer is ready (IBUFRDY = 1), the hardware circuits are back to point

168

Note that all EIS type instructions (CCS codes 110000-111111) follow a path to point C.

If the CCS area indicates that the instruction is a bit type EIS instruction (BIT =!), The hardware circuits 704-122 then go to the command state cycle (FESC) without performing an FPOP operating cycle. If the CCS sequence area indicates that the instruction is not in the bit type class (i.e., BIT = 1), hardware circuits 704-102 enter the FPOP control state for an operating cycle. It will be noted that the number of descriptors in the EIS instruction comprising several words determines the number of FPOP cycles.

A maximum number of descriptors are processed under hardware control before the circuits .704-102 enter the FESC control state making it possible to transfer the control to a firmware routine contained in the execution control memory 701-2. For those instructions of several EIS words which require an address preparation on three descriptors, the circuits of the hardware 704-102 remain in the FPOP command state to execute two cycles during which the circuits of the processing unit generate addresses for the first and second descriptors before entering the FESC command state.

It can be seen in Figure 11 that, depending on the type of instruction as defined by a command sequence area and the type of address preparation required, address preparation for the different descriptors occurs up to that it is determined that an address preparation can no longer continue under material order. In particular, during the FPOP cycle, an address preparation is carried out for descriptors of instruction classes which include instruction types NUM2 to MVT conditioned by the fact that the descriptor is not an indirect descriptor (FID = 1), that the descriptor does not specify an indirect length (FRL = 1) and is not a type 6 descriptor (TYP6 = 1) or that an address preparation must be completed under order of the material (FINH-ADR = 1 ) in addition to other unusual situations which ¹⁶⁹ cannot be processed under material order (i.e. FAFI = 1). When the circuits of block 704-104 force a binary ZERO FINH-ADR signal, this indicates that the address preparation has been completed under microprogrammed command and therefore should not be carried out during an FPOP cycle.

The circuits of a block 704-110 force a binary FAFX signal to ONE when address preparation can be carried out during the FPOP cycle and there are no special conditions such as the appearance of a medium interruption of instruction.

Finally, the RDES = 00 condition is defined by the flip-flop states of a block 704-142 and indicates that a first FPOP cycle occurs during which the processing unit circuits prepare the address of the first descriptor.

In the event that there are certain special type conditions presently defined by the function f, the hardware circuits of block 704-102 enter an FESC control state. This allows the transfer of commands to routines stored in the ECS 701-2 command memory to continue processing the instruction under microprogrammed command.

Furthermore, according to a preferred embodiment of the present invention, the circuits of block 704-102 include flip-flops which produce FIDESC and FWFIDESC control states for processing, under hardware control, indirect operand descriptors for instructions. EIS.

For a first indirect descriptor, it becomes necessary to stop the progress of cycle I during a cycle and to let the execution unit 714 complete its operation.

As soon as cycle E is completed, the hardware circuits extract the indirect descriptor under control of the hardware. More precisely, when the CCS zone indicates that the instruction is an EIS instruction and that bit 31 of the RSIR register is at binary ONE (see FIG. 13c), this means that the first descriptor of the EIS instruction is an indirect operand.

During the FPOA control status cycle, the hardware circuits of block 704-102 stop the flow of cycle I (i.e., HOLD-I = 1) during one cycle. This is how an FPOAID command scale included in block 704-102

2425150

170 switches to ONE binary in response to a first clock pulse which forces the HOLDIOO signal to binary ZERO. At the appearance of the next clock pulse, the flip-flop FPOAID is reset to binary ZERO which makes it possible to drill the signal to ONE binary

HOLDIOO (see expressions set out for the case of the FPOA command state in the chapter Action state of command by the hardware).

For the remaining EIS descriptors, the hardware circuits of block 704-102 no longer stop the progress of cycles I which follow the FPOA command state. It can be seen in FIG. 11 that the FPOP control state cycle is then launched. However, the circuits of block 704-1Q2 immediately pass to the FIDE3C command state upon detection of an indirect descriptor. This state is followed by a transition to the FWFIDESC command state and a return to the FPOP command state terminating the processing of a first indirect operand descriptor. These states are repeated for each descriptor word specified. by the zone MF of the instruction word having an indirect operand (see figure 13b).

Considering instructions other than EIS type instructions, it will be noted from FIG. 11 that when the CCS sequence zone indicates that the instruction falls into the change class or into the transfer class and requires an indirect address change, the hardware circuits 704-102 immediately change to the FPOA control state to the FESC control state. As mentioned, control is transferred to the appropriate firmware routines stored in the ECS control memory 70Î-2. The instruction processing is carried out subsequently under microprogrammed control. As FIG. 11 indicates, the circuits 704-102 pass to an FPOP control state when certain microinstruction codes occur.

Relative to the object of the present invention, the circuits of block 704-102 pass control to the ECS control memory 701-2 to execute certain types of instructions which cannot be executed in a pipeline operating mode .

171

The instructions mentioned above include EIS type instructions as well as the instructions which put the circuits of block 704-102 in the FESC command state during their processing. It will be noted that according to the present invention, the particular coding of the CCS sequence area allows the processing unit 700 to detect a first point in time if an instruction can be executed in the pipeline operating mode.

It can also be seen in FIG. 11 that non-EIS type instructions other than transfer class instructions (TRF = 1) requiring indirect addressing and which are not in the change class (ESC = 1) follow a path which switches to the FWF-IND control state, the hardware control circuits of block 704-102. For double or repeat execution instructions, XED or RPT, the control circuits of block 704-102 enter the FESC control state. It follows an indirect address preparation carried out under microprogrammed command.

According to a preferred embodiment of the present invention, indirect address modification operations for instructions having the format indicated in FIG. 13a ^ are carried out under hardware control. These include operations: register then indirect (RI), indirect then register (IR) and indirect then counting (IT). Other IT address modification operations which do not require indirect addressing are carried out under microprogrammed control.

As shown in Figure 11, when a change in indirect register address (that is, the tm field specifies a change in register then indirect), the circuits in block 704-102 go from state FWF-IND command to the FPOA command vise produced by the CCS area which indicates that the instruction is not a double or repeat execution instruction (ie, RI. XED.RPTS = 1).

Changing the RI address is a 2T operation (i.e., FPOA (RI) -&gt; FWF-INT-_:-&gt; FPOA). During the FPOA command status cycle, when the tm part of the

172 instruction word content from the RSIR register 704-158 indicates an RI address modification, the processing unit circuits invalidate the loading of the CCS zone address in the ECS address register 701-10 in FIG. 3b. The unit 700 also starts to extract from memory the indirect word specified by the effective address resulting from a modification of type R (that is to say, generates a simple read memory command as is has explained).

During the FO-INT control state cycle, the processing unit 700 transfers internally, under hardware control, for the indirect word having the format indicated in FIG. 13d, from the unit 750 and forces the RI flip-flop from a block 704-110 to A binary. The RI flip-flop remains at ONE binary the entire time of the next FPOA command state cycle. This flip-flop is used to force the register R29 704-162 to binary ZERO since the indirect word extracted from the memory has its bit AR 29 in the binary UN state (see FIG. 13d).

As can be seen in Figure 11, when the tm field of the instruction specifies a modification of indirect indirect address then register and the instruction is other than a double execution or repeat instruction (that is - say (IR + FIR). XED.RPTS = 1), the hardware circuits of block 70 4-102 pass from the command state FWF-IND to the command state FIRT. The IR modification is a 3T operation (i.e., FPOA (IR) -—FWF-IND -&gt; FIRT -? FPOA).

The same operations mentioned in connection with an RI modification are performed during the FPOA command status cycle.

During an FWF-IND control state cycle, the FIRT control state flip-flop and the FIR flip-flop are forced to binary UNS. This state is followed by the FIRT command state cycle during which the original content of the RRDXA 704-158 register kept in the RRDXAS 704-159 register is transferred to the RRDXA 704-158 register where the address modification specified by the indirect word is of type R or IT. At this point, the establishment of an effective address is complete (last indirect addressing).

173

In addition, the FIRL command switch is forced to ONE binary. The FIRL flip-flop (last flip-flop indirect) remains at ONE binary all the time of the next FPOA command state cycle. Since the operation is not finished, the FIR flip-flop remains at binary ONE during the FPOA command state cycle.

During the next FPOA command state cycle, the FIRL flip-flop forces the R 29 register 704-162 and the flag bits 30-31 of the RSIR register to binary ZEROS. This ends operating cycle I for this instruction. A similar sequence is followed in the case of a double non-execution or non-repeating instruction which requires an indirect address modification then counting ”. This is a 3T operation (i.e., FPOA (IT) -5&gt; FWF-IND -&gt;

FIT-I -FPOA). During the FWFIND command state cycle, in addition to loading the indirect word into the processing unit registers (i.e., ZDI -RSIR, RDI and

RRLDX-A, R29), the FIT-I command state flip-flop is forced to ONE binary and the RRDXAS 704-159 register is forced to ZEROS.

During the FIT-I command status cycle, the ZEROS content from the RRDXAS 704-159 register is loaded into the RRDXA 704-158 register. In addition, the FIRL flip-flop is forced to ONE binary. Similar to what has been described above, the register R29 704-162 and the flag bits 30-31 of the RSIR register are forced to binary ZEROS by the flip-flop FIRL. The Hardware Control State Actions chapter shows the different operations described above in more detail.

As can be seen in FIG. 11, non-EIS type instructions which are not in the change class and do not require the generation of an effective address (EIS.ESC.EA) follow a path in the direction of 'a point XX.

These instructions have the format of Figure 13 ^ and the portions tja of their TAG indicator areas are coded to specify the absence of indirect addressing (i.e., code 00). As noted, the tm portion of an instruction is checked against indirect addressing during the FPOA cycle and when indirect addressing is not specified, the control flag EA is forced to a binary state of UN.

174

FIG. 11 shows the different groups of instructions following this terminal path being those which indicate zones of CCS sequence coded to specify sequences listed in a group A, a group B, a group C₃ TRF, STR-SGL, STRHWU and STR-DBL. Instructions requiring group A sequences, as well as instructions whose processing has reached point B, following the path towards a point XX.

The point XX, in FIG. 11, indicates the point at which the processing unit 700 has completed the cycle I of processing an instruction and must then extract from the buffer I the next instruction to be processed. Before this can be done, the processing unit 700 must ensure that the instruction that has just been completed does not put it in a double or repeat execution loop (i.e., that the instruction is not an XED or RPT instruction). If the unit 700 has been looped, the hardware circuits of block 704-102 go into an FXRPT control state followed by an FESC control state. It is thus ensured that the unit 700 does not extract the following instruction but that the command is transferred to the ECS command memory 701-2 by which the following operation (s) is carried out under microprogrammed command. In particular, during the FXRPT command state cycle, the unit 700 forces, under hardware control, the ECS command memory 701-2 at the appropriate address and during the FESC command state cycle transfers the command from hardware circuits.

When the CCS sequence area indicates that the instruction is not a double execution or repatition type instruction and that the STR-CPR command flag is a binary ONE which indicates that the instruction buffer must be reloaded due to a memory operation, the hardware circuits of block 704-102 enter the FPI-INIT command state. The STR-CPR command flag is set to binary ONE during a cache write operation when the address of the cache command equals the address of the instruction block. During this state cycle, the processing unit 700 initializes the instruction buffer via the circuits of block 704-128. The hardware circuits of block 704-102 then enter the FPIM-2 control state to retrieve the next instruction. This state cycle

175 is followed by a return to the FPOA command state, as shown in Figure 11.

When the CCS sequence area indicates that the instruction is not a double execute or repeat instruction and that the instruction buffer should not be reloaded due to a memory compare operation (STR-CPR = 1), the hardware circuits of block 704-102 pass to one of the three control states FPIM-I, FPOA and FWF-IBUF indicated. In the case where the instruction buffer is empty (IBUF-EMPTY = 1), it enters the command state FPIM-I to validate the extraction of instructions to fill the instruction buffer. After the instruction buffer is filled, the hardware circuits of block 704102 enter the FPOA control state to begin processing the next instruction. If the buffer is not empty (IBUF-EMPTY = 1), but is ready for reading the next instruction (IBUFRDY = 1), the circuits of block 704-102 immediately return to FPOA order status.

As can be seen in FIG. 11, in the case where the instruction buffer is not conditionally ready (IBUFRDY = 1), the circuits of block 704-102 pass to the command state FW '-IBUF and remain in this state until the instruction buffer is ready (IBUF-RDY = 1). When this is ready, the circuits of block 704-102 go to the FPOA control state.

It will be noted that instructions which indicate CCS zones coded for s&gt;. To specify the sequences listed in group B follow the path marked group B in which the circuits of block 704-102 pass from the command state FPOA to the state FESC. Likewise, instructions which indicate coded CCS areas for specifying the sequences listed in group C pass the circuits of block 704-102 to the FDEL command state followed by the FESC command state. In each case, these instructions require operations which cannot be carried out by the processing unit 700 under control of the equipment but which require certain routines of micro-instructions to complete their processing.

As seen in Figure 11, instructions that indicate coded CCS areas to specify STR-SGL or STR-HWU sequences are processed under hardware control if these

142511Ô

176 instructions do not require character address changes (FCHAR = 1). In such cases, the circuits in block 704-102 enter the FSTR control state.

Instructions that indicate CCS area codes specifying a STR-DBL sequence cause the circuits in block 704-102 to change from the FPOA canceled state to the FSTR-DEL command state followed by the FSTR command state. In the case of each of the three types of sequences mentioned, the circuits of block 704-102 follow a path returning to point B to extract the next instruction from the instruction buffer.

According to the preferred embodiment of the present invention, the path marked TSXn is followed when the CCS zone is coded to specify the TSX instructions inside the chsse. At the start, the route is the same as that followed by instructions of the ESC-EÀ class. Similar operations are thus performed by generating an effective address by the unit 700 during the FPOA command state cycle. In addition, the instruction counter. is updated by increasing by *

The circuits of block 704-102 then go to the FTSX1 control state. During this status cycle, the content of the updated instruction counter is loaded into the RDI register 704-164. The circuits of block 704-102 switch the FTSX2 command indication flip-flop to ONE binary and then enter the FPI-INIT command state. The FTSX2 command indication flip-flop allows the unit 700 to indicate an effective address generated during the FPOA command state cycle and stored in TEAO during the FPI-INIT command state cycle.

It will be noted that normally, the unit 700 indicates the address value IC + 0 + 0 during the FPI-INIT command state cycle.

The circuits of block 704-102 then pass to the command state FPIM-2 followed by the command state FPOA.

It will be noted that FIG. 11 only relates only to hardware operations which relate to the operating cycle I. As mentioned, the processing of a given instruction is carried out as much as possible under control of the hardware. Depending on the class into which an instruction falls,

177 as specified in the CCS area, operations performed during the FPOA Compand State Cycle and during subsequent command state cycles are established. As we explained and as we can see in the chapter,

Hardware State Control Actions, the hardware circuits in block 704-102 which depend on the coding of the CCS sequence area, generate the appropriate type of cache control during the FPOA control state cycle. This action, as well as the other actions, occurs during the control state cycles in Figure 11 are as shown in the next chapter.

178

MATERIAL ORDER STATE ACTIONS

FPOA ORDER STATUS

1. If FINH-ADR = 1, then / ~ Y (29 + X (RBDX-A) + ADR (29) _7 - =&gt; ASEA;

/ “Y 29) 4- X (RRDX-A) + ADR (2 ^ _? + ZBASE -7ASFA;

If RSIR₃₀_₃₁ = OO, then 1 - ^&gt; EA;

RSIR_3O_₃₁^ OO, then O -&gt; EA; RBAS-A (29) -&gt; RSPP

If FIN3-ADR = 1, then / O + O + REA-T_7 -&gt; ASEA;

/ “O + O + REA-T_? + ZBASE - ^ ASFA;

-EA

3. ASEA REA; ASFA&gt; RADO / ~ £ CAŒE-REG = 1

4. If FTRF-TST = 1, then O ^ FINGO

5. If FMSK-29 = 1, then MASK R29 to O

If FIRL = 1, then MASK RSIR 30, 31 to OO. O -&gt; FIR

O-FRI

O - ^ IRL

6. If XFTRF-TST. / “TRGÔ). THF. EA. EIS = 1 and if EA. (LD-SGL + LD-HYÎU + RD-CLR + EFF-ADR + NO-OF), then 1 ...... ^ END; and if EA. (STR-SGL + STR-HWU + STR-DBL) = 1, then

ZREC&gt; RRDX-A; O&gt; S29; and if TSY.n. EA = 1, then IC + 1 .....&gt; IC

CCS&gt; CCS-REG; CCS-Οθ ^ Χ ^ ΤΥΡθ ^ and

S the hook sign (/ *) has been removed from the term EA to clarify expressions.

179

If EA / “DEL-STR-SGL DEL-STR-DBL + TSXn + INST -θΗ_Λ /*EA.ESC 7 = 1 (where INST- R = JJ-SGL-ESC + LD-DBL-ESC + LD-HWU- ESC + EFF-ADR-ESC / EA), then 00 —- ^ RBAS-B

7. If FTRF-TST. TRF.EA = 1, then

at. / “INIT-IBUF = 1;

b. CCS-CCS-REG;

8. If FÎRF-TST. jjRGO.EIS

If FREQ-DIR = 1, then / “HOLD 1 = 1

If FREQ-DIR = 1, then RBIR_2?_₃₅ - *&gt; ZIDD_2?_₃₅-*£29,

RRDX-A, FID, FRL;

If BIT = 1, then 01 ——ΗΤΥΡθ ^,

If MTM-MTR =? 1, then 00 -—7 * RTYP_not_₁ ;

If BIT. MTM-MTR = 1, then ZIB -&gt; RTYP_Q_₁

RIR₃₀ - *&gt; FAFI;

ZIB -X ^ RSIR, RBAS-A;

If (NEED-DESC). (IBÜF-RDY) = 1, then

FTRF-TST = 1, then / READ-IBUF / ZIB (CDR) = 1

FTRF-TST = 1, then / “READ-IBUF / ZIB (OPS) = 1 CCS - ^ CCS-REG

9. If FPCA-ID.RSIR₃₁ then HOLD-I —-&gt; 1

If FPQA-ID.RSIR ^ ·, ./ublHOLD-E, then 1- ^ POA-ID;

If FPOA-ID./ hundredHOLD-E, then 0 --FPQA-ÏD

10. If FTRF-TST = 1 and

If / “TRGO = 1, then involve FAEDF-ACTV; If XED-RPTS = 1 then 1 —-—&gt; FTRGP

If [ÊND = 1, then / RDI / ZPESB '”1

11. If ^ TRGO = 1, prevent sampling IC

1 —-—&gt; FTNG0

12. 0 -&gt; FTRF-TST.

DMEM AND VALUES ESTABLISHED DURING ORDER STATEMENT FPOA / MEM, / ~ SZ for FPOA

If FTRF-TST. / TRGO - 1, then / ~ MEM = nothing;

If (FTRF-TST + /~TRGO).ESC= 1, then / “MEM = nothing;

If (FTRF-TST + /~TRGO).EIS=1, then / ~ MEM = nothing;

If (FTRF-TST + / TRGO) .ESC.EIS, EA = 1, then / ~ MEM = simple reading £ SZ = Sgi;

180

242511Û (FTRF-TSF + [TRGO) .EA If ESC-EA + DEL-STR-SGL + TSXn + DEL-STR-DBL + NO-QP = 1, f— then ^ MEM = nothing;

If LD-SGL LD-SGL-ESC + LD — SGL — DEL ^ then FCHAR_eRRDX ~ A ⁼ DU.DL = 1 * then ^ MEM = simple reading; £ SZ = Sgi;

FCHAR.RRDX-A = DU = 1, then / ~ MEM = Direct; / ”SZ = HWU;

FCHAR.RRDX-A = DL = 1, then / ~ MEM = Direct; /^-SZ = HWL;

FCHAR = 1 then / MEM = nothing.

If LD-HWU + LD-HWÜ-ESC + LDHWU-DEL = 1_Î so

RRDX = A = DU.DL = 1, then / f ~ MEM = simple reading); / SZ = HÏÏU

RRDX-A = DU = 1, then / MEM = Direct; / SZ-HWU

RRDX-A = DL = 1, then / MEM = Direct; /^_SZ = ZERO.

5.If STR-SGL = 1, then if FCHAR = 1, then / ~ MEM = simple writing;

/ SZ = Sgl and if FCHAR = 1, then / MEM = nothing.

If TRF = 1, then if FTRF-TST.FABUF-ACTV = 1, then /^—MEM = ^ extract-instruction) / SZ = B and if FTRF-TST.FABUF-ACTV = l, then /^—MEM = extract 1 instruction) £ sZ = A and if FTRF- TST = 1, then / ~~ MEM = nothing.

If EFF-ADR + EFF-ADR-ESC = l, then / “MEM = direct; /“ SZ = HWU

If LD-DBL + LD-DBL-ESC4LD-DBL-FP-ESC = 1, then / MEM ^ double closing.

If RD-CLR = 1, then / MEM = delete read If STR-DBL = 1, then FMEM = Double write; / SZ = DBL If STR-HWU-1, then FMEM = simple writing FSZ = HWîf If LD / STR-SGL-ESC = 1, then / ~ MEM = simple reading / ~ SZ = Sgl; / ~ R / W = l If LD / STR-HWÜ-ESC = l, then / _ MCM = simple reading; / ”SZ: HWU; / ~ P / W = 1.

FSTR ORDER STATUS

1. REG (RRDX-A) -ZX;

2. (ENAB-ZX-A2 = 1;

3. ZX, ZX-A2 - / ZDO;

4. RZESB - »RADO;

5. / END -i;

ORDER STATUS FSTR-DBL

1. REG (RRDX-A) - * ZX;

2. — 1;

3. ZX, ZX-A2-&gt; ZDO;

4. ZRESB -&gt; RADO;

5. 0010 -RRDX-A;

6. 1 - ^ R29.

181

FESC ORDER STATUS

1. If / DIBUF / PIPE = 10 + 11 or / “PIPE = 001 + 100_7, then / END = 1.

2. If / DIBUF / PIPE = 11 or / “PIPE = 1OO_7, then 1 -5&gt; FWF-REL

ORDER STATUS FWF-IND

ZDI - ^ RDI

If (RI + IR + IT-I) = 1, then ZDI ——? RSIR ZDI-&gt; RRDX-A, R29,

If RI. (DXED-RPTS) = 1, then 1 -3&gt; FRI _L0 If (IT-I). -j | —— = 1, then O- ^ RRDXAS_Q_₃

If IT. = 1, then RRDX-A -ZRDXAS_Q_₃ and

-FIR.

ORDER STATE FIT-I 1. RRDXAS. - - - RRDX-A_q_₃₁₅ 2. 1 -FIRL 'FIRT ORDER STATE

1. If RSIR-31 = 1, then RRDXAS —-RRDX-A and

-Z&gt; FIRL

FXRRT ORDER STATE

1. CCS -CCS -REC ²⁰ ORDER STATE FTS X 1

l.IC-zx

2. ZX —-&gt; ZDO '

3. ZRESB -; tRDI

4. 1- ^ FTSX2 ²⁵ c FDEL ORDER STATE

1. [.0 + O + REA-tJ ——&gt; ASEA; and

[. .0 + O + REA-TJ + ZBASE -5&gt; ASFA.

2. ASEA -&gt; REA; ASFA -&gt; RADO; and^ZBASE33-35 —&gt;^RBASE33-35^{; and}³⁰ 3. fèÇÀCHE-REG = 1

4.51 DEL-STR-SGL = 1 then / ~ MEM = write SGL; / SZ = SGL.

5. If DEL-STR-DBL = 1, then / MEM = write DEL; /^-SZ = DBL.

6. If DEL-STR-SGL.DEL-STR-DBL = 1, then / MEM = nothing.

7.51 LD-SGL-DEL + LD-DBL + LD-HWU-DEL = 1, then / END.

ORDER STATEMENT PFI-INIT

1. If FTSX2 = 1, then / θ + RIC + O) —- ^ ASEA;

If FTSX2 = 1, then / θ + O + REA-T _ / - ASEA;

ASEA + ZBASE —-sASFA.

182

2. 0 - ^&gt; FTSX2

3. ASEA -&gt; REA; ASF A- ^ RADO

4. / ÇCACHE-REG = 1. '

5. ASEA -REA-T

6. Involve FÂBUF-ACTV.

7. / ~ MEM = INST-FETSCHl.

8. / ~ INIT-IBUF-OPS = 1.

FTRF ORDER STATUS

1. / “4 + O + REA-T) -&gt; ASEA and / ~ 4 + 0 + REA-T) + ABASE -&gt; ASEA.

2. ASEA-RE A; ASFA - \&gt; RADO (introduction 00-i&gt; RAD0g₂_gg)

3. / ^ CACHE ^ REG = 1.

4. RBAS-B - ^&gt; ZBAS-C; O, REA-5&gt; RDI; 1-&gt; FTRF-TST.

5. ZDI - *&gt; RBIR, RSIR, RBAS-A, RRDX-A, R29.

6. / ~ READ-IBUF / ZIB (0PS) = 1.

ORDER STATUS FTRF- NG

1. / 0 + 0 + REA-T J - τ 'ASEA; and / ~ 0 + 0 + REA-T_7 + ZBASE- ^ ASFA.

2. / ~ END = 1.

ORDER STATEMENT FPIM-1

1. / “4 + 0 + REA-T_7 ASEA and / 4 (forces 00 -—8AD0₃₂_₃g) + 0 + REA-T) + ZBASE —i&gt; ASFA.

2. ASEA&gt; REA; ASFA J&gt; RADO (inyroduction 00 —RADOgg_gg) and £ £ ACHE-REG = l.

3. ASEA-&gt; REA-T; and /^_MEM = INST-FETCH1; and RBAS-B —- ^ ZBAS-C.

ORDER STATEMENT FPIM-2

1. / “4 + 0 + REA-T -&gt; ASEA.

2. ASEA .--- REA; and ASFA -&gt; RADO (force 00 - ^&gt; RAD0g₂_gg); and / ^ CACHE- REG.

3. If ASFA-C27 = 1, then ASEA-REA-T; ASFA, ZWS-&gt; RIB-VA,

RIB-WS; and / ~ MEM = INST-FETCH2; IPTR-CUR-SEL -? / “SZ; and

If ASFA-C27 = 1, then / ~ MEM = nothing, and RBAS-B -; - Î&gt; ZBAS-C, and

ZDI -—&gt; RBIR, RSIR, RBAS-A, RRDX-A, R29, and / “READ-IBUF / ZIB = 1.

183

ORDER STATUS FWF-IBUF

1. If IBÜF-RDY = 1, then READ-IBUF / ZIB (CUR) and

ZIB - ^ jRBIR, RSIR, RBAS-A, RRDX-A, R29.

FPIM-EIS ORDER STATE

1. / “4 + O + REA-T_7-—5&gt; ASEA: and /“ 4 + O + REA-T _ / + ZBASE- ^ ASFA.

2. ASEA-&gt; REA, and ASFA --5 RADO (force OO - =&gt; RADO₃₂_₃₃) / ~ $ CACHE-REG = 1.

3. ASEA-REA-T; and / MEM = INST-FETCH1; and_1Q R3AS-B -t'ZBAS-C; ASFA-C27-&gt; FEIS-STP-CPR; and

ZIB - ^ RSIR, RBAS-A; and

If BÏT.MIM-MÎR = 1 / then ZIB -f'RTYPq ^; and

If IBUF-RDY = 1, then / “READ-IBUF / ZIB, and

CCS -— ^ CCS-REG.

ORDER STATUS FWF-DESC ¹⁵ 1. If 1 BUF-RDY = 1, then / READ-IBUF / ZIB; and

CCS&gt; CCS-REG.

ZIB -—&gt; RSIR, RBAS-A; and

If BIT.MTM-MTR = 1, then ZIB * - ^ ΑΤΥΡθ ^.

. _ ORDER STATEMENT FPQP '

1. If FINH-ADR = 1, then. /^-Y (29) EIS + X (RRDXtrA, RTÎP, FNUM) + ADR (29,

RTYP_q) _7 —- ^ ASEA;

/ ”Y (29) EIS + X (RRDX-A, RTYP, FNUMe + ADR (29, RTYP_Q)_7 +

ZBASE -&gt; ASFA.

2. If FINH-ADR = 1, then / “O + O + REA-T_7 —-ASEA;

/ “O + C + REA-T) + ZBASE -&gt; ASFA.

3. If FID = 1, then

HOLD-E = 1 qn

RSIR -&gt; ZIDD

ZIDD -&gt; RRDX-A, R29

4. ASEA - ^ REA; ASFA - &gt;&gt; RADÛ;

/ ”^ CACHE-REG = 1;

_{3 5} If FIG-LEN = 1, then ZLN -&gt; RLEN

5. ASEA —to REA-T (RDESC);

/ ~ FID / + FRL + FÀFI_7 '——&gt; FINDA; (TYP = 6) .FINH-ADR - $ “FINDC;

184

ΤΥΡ = 9 + FINH-ADR -FINDB; FINDC + / “SET-FINDC-5&gt; DINDC;

FINDA + / “SET-FINDA -— &gt;&gt; DINDA;

FINDB + / “SET-FINDB —-&gt; DINDB.

FPOP ORDER STATUS (continued)

6. RDESC = 00 (first descriptor)

If FNUM. EDI T = 1, then

RSIR ^ 23 - $&gt; R1DW; RTYP_Q_₁ -5&gt; RTF1;

If FIG-LEN = 1, then ^RSIR24-35 - ^ RXPA, RLN1

If FINH-ADR = 1, then ASFA ^^^ g-4-RPA;

ASFA ^₄__3g- =? RPO if RSIR21 = 1

ASFA_%4__3ft- \ RPO if RSIR21 = 1

If FNÜM.EDIT = 1, then

RSïR₂i_23 -? R1DW; ^rTYP_q_₁ -&gt; RTF1, ASFA-g₄_₃₆^RSIR24-29- ^ RXPA;

If FIG-LEN = 1, then RSIR_3O_₃₅_&gt; RLN 1

If RSIR_have - 1, then ASFA₃₄_₃₃_ -&gt; RPO

If KSIR₂₁ = 1, then ASFAg ^ _₃g -? ΈΡ0

If FNUM = 1, then

RSIR₂₄_₂₉ -9RXPA; HSIR₂₁_₂₃-&gt; R1DW; RTYPO (O) -&gt; RTF1;

If FIG-LEN = 1, then RSIR_3Q_₃₅- / RLN1 ^ASFA34-36~ * ^ECN10-2

If RSIRgi = 1, then ASFA₃₄_₃₅ &gt; RPO

If RSIR₂₁ = 1, then ASFA₃₄__3g-&gt; RPO.

FPOP ORDER STATUS (continued)

A. If /TTFïD.FRL.FAFI. (TYP = 6 + FINH-ADR) J = 1, then

1. 0 —-&gt; FINH-ADR, FIG-LEN

2. If MTM-MTP, where DREV = MRL + TCTR + SCAN-REV = 1, then 1 = / ~ READ-IBUE / ZIB ·

ZIB RSIR, RBAS-A;

01 - ^ - RDESC; If TRANC = 1, then IR 30 -FAFI;

If TRANC = 1, then RBIR₀_₁₇-? ^ZIDD27-35-^{29 ;}

RRDX, A, FID, FRL;

If TRANCv 1, then ZIB -&gt; R29, RRDX-A;

If CÂN.CMPC.CMPCT = 1 then ZIB - ^ RTYP;

If EDIT: 1, then 0&gt; FNUM.

3. SiS /^_TCT + SCAN-FWD + MVT + CONV /. /^-ΖΙΪΝ „. _o = 0. '* ._____ “ώ4-ύθ

FIG-LEN_7. FIRE, then MEM = ISE-READ.

4. If (NUM2 + NUM3 + EDIT) (ZLN_3Q_₃₅= O + FIG-LEN).

FIRE, then

185 / MEM = PRE-READ.

5. If MLR (ZLN „. _OK= 0 + FIG-LEN). FElT = 1, then (TYP = 9). FESCD = 1, then /^-MEM = LD QUAD;

._ 1 = (INIT-1BUF; and if (TYP = 9.FESCD = 1, then / ~ MEM = PRE-READ.

6. If (CMPC + CMPCT) (ZLN₂₄_₃₅= 0 + FIG-LEN.FËÏÎ = 1, then (ΊΎΡ = 9), FESCD = 1, then / ~ MEM = RDSGL; (SZ: Z0NED;

(TYP = 9.FËSCD = 1, then / ~ MEM = PRE-READ7. If OIHERWISE - '= 1, then / MEM - nothing.

FPOP ORDER STATUS (continued)

B. If /FÎD.FRL.îÂFI.(TYP= 6 + FINH-ADR) _7 = 1, then

1. / ~ MEM = nothing.

7. RDESC = 01 (second descriptor)

If ÈDÏT.FNUM = 1, then

RSIR₂₁_₂₃ -R2DW, RTYPO-1 -&gt; RTF2;

If FINH-ADR and RSIR21 = 1, then ASFA₃₄_₃₅~ -&gt; RP1

RSIR21 = 1, then RSFA₃₄_₃₆ __ ^ASFA33-35-*^RP6·

If FNUM.EDIT = 1, then

RSIR₂₁_₂₃-tR2DW, RTYPO-1 -3RTF2;

^ASFA34-36 ~ ^^ 2 () - 2 'if FIG-LEN = l, then RSIR_3q_₃₅- "LN2.

If FNUM = 1, then

RSIR₂₄__2g-&gt; RXPB; RSIR₂₁_₂₃—--&gt; R2DW.

RTYPO, (0) - tRTF2; ASFA₃₄__g6-&gt; RCN2_Q_₂

If FIG-LEN = I, then RSIR_3Q_₃₅- ^ ILN2.

A. If FÏD.FRL.FAFI. (TYP = 6 + FINH-ADR) = 1, then

1. 0-5 ”-FINH-ADR, FIG-LEN

2. If (NUM3 + EDIT) = 1, then

RBIR_Q_₈- =&gt; ZIDD₂₇_₃₅- $&gt; R 29, RRDX-A,

FID, FRL;

(READ-IBUF / ZIB (CÜR); IR30 - ^&gt; FAFI

ZIB -—&gt; RSIR, RBAS-A, RTYP.

FPOP ORDER STATE (CONTINUED

3. If (NUM2 + NUM3 + EDIT) &lt;ZLN₃₀J₃₅= 0 '+ FIG-LEN). FË21, then / “MEM: PRE-READ.

10-tPDESC if NUM2 + NUM3.

4. (ZLN_24-35= 0 + FIG-LEN) .ΪΈ2Ι.

5. If (CMPC + CMPCT) = I, then / MEM = PRE-RD.

242511ô

186

6. If OTHERWISE = 1, then / MEM = nothing.

b. If FID.FRL.FAFI (TYP = 6 + FINE -ADR) = 1, then 1. / MEM = nothing.

8. RDESC = 10 (third descriptor)

If FNUM.EDIT = 1, then

RS^IR₂i_₂₃--τ'RIDW. If RTYPO-1 = 00 = 1, then 1 -&gt; RTF3

If RTYPO / lf00 = 1, then 0-&gt; RTF₃

If FIG-LEN = 1, then RSIR₂₄__g5-RLN1

If FINH-ADR = 1, then ASFA₃₄__3g-&gt; RPA;

If RSIRg · ^ = 1, then ASFA₃₄__3g-— ^ RPO

If RSIRgj = l, then ASFA₃₄__3g-&gt; RPO.

If FNüM.EDIT = 1, then ^^ 21-23-If RTYP0-I = 00 = 1, then 1 -&gt; RTF₃

If RTYPO-1 = OO 1, then 0 -RTFg

If FIG-LEN = 1, then RSIR_3Q_₃₅· - ~&gt; RLN1

If RSIR ^ = 1, then ASFA₃₄_₃₅-RPO

If RSIR₂^ = l, then ASFA₃₄__3g- =&gt; RPO.

PPQP ORDER STATEMENT (continued)

If FNUM = 1, then

RSIR₂i_₂₃—-RIDW; if RTYPO = O = 1, then 1 -&gt; RTF_g if RTYPO / O = 1, then C -RTF₃

If FIG-LEN = 1, then RSIR_3Q_₃₅ -&gt; RLN1

If RSIR₂₁ = 1, then ASFA₃₄_₃₅-î&gt; RPO

If RSIR₂₁ = 1, then ASFA₃₄__3g -4&gt; RP0.

A. If (FID .FRL FAFI (TYP = 6 4- FINH-ADR) = 1, then l. /^-MEM = nothing.

B. If ^ SET-FESC = 1, then 1 -FESCD.

FIDESC ORDER STATE 1. / ~ Y (29) + X (RRDX-A) + ADR (29) _ / -&gt; ASEA;

/ “Γ (29) + X (RRDX-A) + ADR (29) _ / + Z5ASE -&gt; ASFA;

ASEA -? REA; ASFA -—&gt; RADO;

/ “CACHE REG = 1;

If DU + DL = 1, then / “MEM = READ-SNGL; ^ SZ = single); 1 = ^ HOLD-E; O -&gt; FID; RBIR30 -&gt; FAFI;

If RDESC = 00, then RBIR- ---&gt; ZIDD - =&gt; R 29

RRDXA, FRL;

If RDESC = Ql, then RBIR_g_₁₇ -&gt; ZIDD - ^ R29, RRDXA, FRL;

If RDESC = 10, then ΗΒΙΕ_θ__§—- / ZIDD - ^ R29, RRDX-A, FRL;

187

ORDER STATEMENT FWF-IDESC 1. ZDÏ J ^ RBIR, RBAS-A;

HOLD-E = 1 If IDESC = 00 and if BÎT.MTM.MÏR = 1, then ZDI: RTYP If RDESC = 01 and if (SCAN + CMPC + CMPCT) = 1, then ZDI -&gt; RTYP if RDESC = 10, then ZDI ——&gt; RTYP.

ABBREVIATIONS OF TERMS USED IN THE ACTION MATERIAL ORDER STATEMENTS ACTIONS

1. Y (23)

2. Y (29) EIS

3. X (RRDX-A)

4. ADR (29)

5. RBAS-A (29)

RSPP

6. / “READ-IBUF / ZIB (CUR) = R29 = RSIR,

R29 = RSIR,

0-17 3.3,3.3-17 = R29 = RSIR_|R29 = RSIR,

0-20

ZY

ZY

-&gt; ZY

3,3,3,3, -20 = RSIRgo = ENAB-ZX depending on

5? S0 = R 29 = 0

RRDX-A = DISABLE ZX?&gt; ZZ

R29 = ZAR

0-19

0-20&gt; ZZ

0-19; o-? ZZ = R29 = 0010

-&gt; RSPPQ

R29 = 1, RBAS-A_Q_₂ = / READ-IBUF / ZIB FABUF-ACTV = 0 - b-3 TO&gt; RSPP

- ^ DRDB

0-3

7. / READ-IBUF / ZIB (OPS) =

FABUF-ACTV = 1 / read-ibuf / zib FABUF-ACTV = 1

-&gt; DRDB

FABUF-ACTV = 0

DRDB -&gt; DRDB = If XED RPT RPL RPD XEC, then ZIB -&gt; RBSIR, RSIR, RBAS-A, RRDX-A, R29;

8. / “END if FTRF-TST./TRGO = 1 and if (IBUF-EMPTY.IBUF-RDY) = 1, then /“ READ-IBUF / ZIB (CUR);

if FTRF-TST = 1 and

188 if EIS + FTRFNG = 1, then IÇ + 1;&gt; IC; if EIS .F1RFNG = 1, then IC + CCS-K ^ -&gt;

ic;

if (IBUF -EMPTY.IBUF-RDY) = 1, then 5 / ~ READ ~ IBüF / ZIB (CUR);

if FTRF-TST = 1, then O - &gt;&gt; RINH-ADR.

9. RI = RSTR 30. 31.

10. IR = RSIR 30. 31

11. IT-I = (RSIR 30.31) (RRDX-AO.Ï.2.3.

12. X (RRDX-A, RTYP, FNUM - ENABLE ZX depending on RRDX-A,

RTYP, FNUM

13. ADR (29, RTYPq) = R29 = 0 - &gt;&gt; ZZ_Q_₂₀

R29 = ZAR_q_₁₉-&gt; ZZ₀_i9 '

RTYP_q = ZAR20- / · 21.22 +

21.23 -&gt; ZZ20

RTYP_Q= O · —--&gt; ZZ20.

14. ASEA-zREA-T (RDESC) = ASEA-5&gt; REA-T

RDESC = 00 = 000 -ZBAS-C

RDESC = 01 = 001 -&gt; ZBAS-C

RDESC = 10 = (01, FABUF-ACTV) -&gt;

ZBAS-C.

15. ^ RTYP-B = If BIT = 11 - ^ RTYP-B_Q_₁

If BIT = RTYP_q, RTYP ^ FNUM-&gt;

rtyp-b_q_₁

16. / ^ CACHE-REG = sample cache control registers)

17. CCS-&gt; CCS-REG - = ZEEG (CCS-R -— RREG - ^ RRDX-B next clock pulse; CCS-O2FNUM.

= CCS-O_O_₂-^{5&gt; EOP}O_2

18. ΤΥΡ9 =? ΚΤΥΡθ - + RTYPO. FNUM.

19. TYP6 = RTYP-. . FNUM.

O 1

189

We will now describe the operation of the device of the present invention with reference to several instructions. As an example, if we refer to the specific flowchart in FIG. 12, it is assumed that the instruction buffer contains two instructions which correspond to an instruction for loading A (LDA) followed by an instruction addition to A (ADA). These instructions have the format shown in Figure 13a. To facilitate the explanation of the description given above, it will be assumed that the part tm of the indicator area of ​​each instruction does not determine an indirect address operation. In addition, it is assumed that the instructions do not indicate a higher direct type of operation (DU) or a lower direct type of operation (DL).

It is assumed that the first instruction (LDA) contains an address specifying the first word (0) of a block of 4 words which is not in cache 750 and that the second instruction (ADA) contains an address specifying the third word from the same block of 4 words. The shortest time during which a block can be transmitted from main memory 800 to cache unit 750 is two words followed by a free cycle during which no information is transmitted, itself followed by two more words. During this free cycle, the processing unit 700 can execute the instruction ADA except that, as explained, the requested data word will not be received from the main memory 800. The following example shows how the arrangement of the present invention prevents interference between commands resulting from the processing of the two instructions and eliminates the issuance of double commands. This is done during all the necessary recovery by processing instructions in a pipeline mode.

The operation codes of the LDA and ADA instructions refer to locations in the CCS 701-2 command memory comprising CCSS zones having the code 000000. This means that the LDA and ADA instructions are included in the LD-SGL class.

Referring to FIG. 11, it can be seen that the circuits of the hardware of the processing unit which end the operating cycle I follow the path FPOA -&gt;

point XXX -&gt; FPOA. During the FPOA command status cycle, the unit 700 performs the following operations under control of the

190 equipment. It generates an effective address as a function of the content of register R29 704-162, register RBAS-A 704-156 and register RRDXA 704-158. The resulting effective address is loaded into the REA register. It is also added to the base address and then loaded into the RADO register 704-46 in Figure 3e. Since the tm portion of the instruction indication field does not specify indirect addressing, the EA control flag is forced to ONE binary. In addition, a code (RSIR 24-26 specifying the register A is loaded in the register RREG 714-42 of FIG. 3g.

As mentioned, the CCS area indicated by the LDA instruction is coded to specify an LD-SGL sequence. Since the td portion of the instruction indication area does not specify a DU or DL ​​operation, the processing unit circuits in block 704-108 generate a simple read command to be sent to the processing unit. cache 750 under hardware order.

More specifically, the generated address which corresponds to the absolute descriptor address loaded in the RADO register 704-46 serves as the command address. In addition, control bits 104 and inset bits 5-8 are generated by the circuits 704-108 of Figure 3c and a switch 704-40. These signals are sent via switch 704-40 instead of bits 1-8 from switch 704-46 while bits 0 and 9 are forced to ZEROS. Out-of-text bits 5-8 are set to binary UNS since they are not used for read commands. Control bits 1-4 are converted to a control code of 0111 by the decoder circuits of a block 704-118. This command code specifies a quad memory read instruction which makes it possible to extract a block of 4 words from the main memory 800.

The circuits in block 704-108 operate to generate control signals by the cache memory control hardware [meMOTB to [mEM3TB, in response to the CCS area and to control status signals from block 7041.02. In the case of a simple cache read command, the signals ^ MEMOTB to pÆEM3TB correspond to a code of 1000 The circuits of block 704-108 generate the signals ^ MEMOTB to

MEM3TB according to the following Boolean expressions:

191

MEMO-TB = FDEL. DELSTRG + TERMG.ÉÀ.ËlS.ESC.TRF + TERMG.FCHAR.EA.DU-DL. (STRG + RDCLR + LDDBLG + LDHWUG + LDSGLG).

MEM1-TB = FPOA.TRF.EA.FTRF-TST + FTRF + FPIM-2 + FPI-INIT + FPIM-1 + FPIM-EIS + FDEL.DELSTRG + FPOA.TERMG.EA.FCHAR.STRG + EIS TERMA + EIS TERMB.

[MEM2-TB = TERMG.EA. FLDDBLG + STRDBL | ~ ΜΕΜ3-ΤΒ + FDEL.DEL-STR-DBL J + EIS TERMA + EIS TERMB FTRF + FPIM2 + TERMG.EA. Γ (DU-DL). FCHAR + RD-CLR + EFFADRG J^L + EISTERMA in which TERMG = FPOA. (FTRF-TST + jjTRGO);

EIS TERMA = FP0P.DESC0.FE11N. (CMPC + CMPCT +

SCAN-FWD

MVT + TCT + C0NV + DNUM2 + DNUM3 + Ep, IT). „+ FP0P.DESC1.FE2N (DNÜM2 + DNUM3 + EDIT + CMPC + CMPCT); and

EIS TERMB = FPOP.DESC0.FE11N.MLR These expressions show the relationship between the CCS codes and the control signals sent on the DNEM lines.

Other circuits in block 704-108 decode the CCS area and generate the j_SZ signals which indicate which half of the RDI register 704-164 should be loaded. The signals j_SZ serve as dimension indicator producing information making it possible to indicate whether it is an operation of the higher direct type (DU) or the lower direct type (DL) or a simple operation. In the case of a simple read operation, the SZ signals are binary ZEROS.

The circuits in a 704-106 block force the ^ CACHE-REG and pCCS register sampling signals to binary UNS. The ^ CACHE-REG signal loads the simple read command code in the RMEM register 704-130 while the £ cCS signal loads the address of the CCS word sent by the bus 704-204 to be loaded in the address register ECS 701-10 of the figure

3b.

24251 ÎO

192

The cache control code stored in the RMEM register 704-130 is sent via the decoder circuits of block 704-118 on the DMEM lines while the command word loaded in the RADO register 704-48 is sent to l 'cache unit 750 via RADO / ZADO lines. In addition, the decoder 704-120 forces a flip-flop REQCAÇ 704-134 to ONE binary, in response to the signals ^ MEMOTB to {MEM3TB. The command is thus reported to the cache unit 750. During the command state cycle FPOA, the unit 700 performs an operation ^ END under hardware control, by which the instruction counter is updated and the following instruction (ADA) is loaded into the registers RBIR, RSIR, RBASARBX — A

A / et R29. In addition, the hardware circuits of block 704-102 return to the FPOA command state to begin execution of the ADA instruction during the next cycle or the second operating cycle.

ADA instruction also requires a cycle to be completed. The processing unit 700 performs the same operations as those which have been mentioned in connection with the LDA instruction.

The only difference concerns cycle E, in which a different microinstruction is specified by the CCS address.

During the next cycle which corresponds to a second FPQA cycle, the cache unit 750 executes a cache cycle in parallel with the execution of the operations of cycle I.

For the cache unit 750, the single read command (ZAC) sent on the ZPSWAO-39 lines in response to the binary DREQCAC line being set to ONE, is written to an empty slot in the RZAC 750 buffer. -102 specified by the content of the counter 750-106. As mentioned, the address of this location is determined by the states of the activity bits. However, by way of example, it is assumed that the buffer 750-102 is empty and that all the activity bits are reset to zero. The ZAC command is therefore written in location 0. This introduction is made independently of the fact that there is a match condition or a no match condition (that is, the state of BPSD).

193

Referring to Figure 12, it can be seen that when the DREQCAC line is ONE binary, the cache unit 750 has access to the directories 750-500 and 750-502 and to the cache memory 750-700 using the address signals from RADO lines 25-33 sent through the switch 750-702. This is done by decoding the cache command sent over the DMEMO-3 lines by a 750-166 decoder.

The comparison circuits 750-536 to 750-542 compare the instruction address LDA with the address read in the directory 750-502. Since the word specified by the LDA instruction is not in cache 750, circuits 750-560 maintain the BPSD match signal at binary ZERO. However, during the directory search cycle and before the cache unit 750 detects a match or no match condition, the ZAC command is loaded into an SIU 750-174 output register with 1 ' ZPSWA 750-110 switch and ZPSW 750-178 switch. Cache unit 750 assumes an absence condition.

As can be seen in FIG. 12, since the result of the directory search cycle is a condition of no correspondence, the decoding of the simple cache read command causes the flip flops to be set to binary UNS. CAOPR, UGCOGTH and RBPSD control status for blocks 750-3. The cache unit 750 can thus execute the three operations in parallel indicated in FIG. 12 during the next operating cycle which corresponds to a directory assignment cycle. Due to the no match condition, the cache unit 750 sets the activity bits (one pair) to one and increases the address pointer (not shown) by one towards the empty location next (location 1). Since this is a quadruple read command, two activity bits are set to binary UNS and the resulting value is loaded into the MIES register 750-138.

This coding is used to identify which words of the quadruple read command are pending.

194

Under the control of the UGCOGTH control state flip-flop the cache unit 750 performs a directory assignment cycle in which the most significant address bit signals contained in the ZAC control address previously entered in the buffer RZAC 750-102 pass through a switch of ZAC 750-152 and which, instead of being compared as in the previous cycle, are entered in the distributor 750-502 at the location specified by the content of the block register 750 -524. The block address, described above, is generated as a function of the state of the full / empty bits (F / E) or of the permutation bit (RR) when the set of full / empty bits is set to , which indicates that all the blocks are full and that one of them needs to be replaced. As mentioned, these bits are read during the directory search cycle and decoded to establish the available block address.

As shown in Figure 12, the cache unit 750 generates signals which set the full / empty bit corresponding to the specified block to ONE binary, which indicates that the location contains valid data. In addition, cache unit 750 sets the wait bit corresponding to this same block to binary ONE in accordance with the state of signals BKDCDO-3. These signals are sent via an OR circuit of a 750-512 block. It will be noted from FIG. 4 that the decoding of the block location written therein which corresponds to the signals BKDCDO-3 is also registered in a register location of a block 750-520 specified by address signals PRZACWO -1. This indicates which wait bit should be reset later when word 4 of the requested block is received.

The wait bit once set indicates that the operation is now on hold. In addition, during the directory assignment operation, the cache unit 750 makes a request to the SIU 100 for a memory operation, under the control of the flip-flop CAOPR.

More specifically, the flip-flop CAOPR forces the register AOPR to ONE binary, which signals a memory request to the SIU 100. At this time, the cache memory unit 750 sends the ZAC command on the DTS lines while appropriate memory identification signals and maneuvering signals

195 vre are sent on the MITS and SDTS lines, respectively.

The memory identification signals generated by setting one of the activity bits in response to the quadruple read command are sent via the MITS register 750138 previously loaded by a register 75Ô-106 and a switch 750-139 . The operating signals are generated conventionally by means not shown. For more information concerning the use of operating signals, reference may be made to US Pat. No. 4,006,466.

SIU 100 signals acceptance of the cache memory request by forcing the ARA line. to ONE binary.

As can be seen in FIG. 12, the cache unit 750 puts the processing unit 700 off, under the control of the flip-flop RBPSD, by forcing the line CPSTOPOO to binary ZERO. This completes the series of parallel actions generated in response to the signal sent on the DREQCAC line which is indicated by the symbols END.

At this time, all the flip-flops except for the RBPSD flip-flop (that is to say, CAOPR, UGCOGTH, etc.) are delivered to binary ZEROS until a request for next cache.

As shown in FIG. 12, the remaining operations performed by the cache unit 750 take place following the responses from the main memory SD 0 indicated by forcing the ARDA line to ONE binary. It is assumed here that the main memory 800 is capable of processing the quadruple read command: cache immediately when it operates during a following cycle to transfer a first pair of data words of the requested block. By such a transfer, the SIU 1OO unit forces the ARDA line to ONE binary, which indicates that the even word of the pair (word 0) is available on the DFS lines. The SIU 100 also forces the DPFS line to ONE binary which indicates a double word transfer.

During the time that the ARDA line is ONE binary, the cache unit 750 loads the first data word into the register RP 750-179. In addition, multiple gate identification signals from the MIFS lines which indicate the pair of transferred words are loaded into the RMIFS register 750125. It is assumed that the · MIFS signals indicate that the words 0 and 1

196 of the block of 4 words requested are received (for example, a code of 000).

Bits 2 and 3 of the MIFS signals stored in register 750-125 are used to gain access to the ZAC read command stored in location 0 of buffer RZAC 750-10 2. The address is sent via the ZAC 750-152 switch to the 750-700 cache memory and the 750-500 and 750-502 directories.

In parallel, by accessing the directories 750-500 and 750-502 and the cache memory 750-700, the first data word is transferred to the RDO register 750-180. The signal sent on the DPFS line changes the flip-flop ΌΑΤΒ to ONE binary. Under the command of this toggle, the second word (word 1) is loaded into the register RP 750-179. It is then loaded into the RDI register 750-180. When a following clock pulse occurs, the THCFD flip-flop changes to ONE binary. Under the control of this flip-flop, the pair of words (words 0 and 1) are written to the block location of cache memory 750-700 specified by the control address bits ZAC through the intermediary of the ZAC 750-152 switch. In addition, the first activity bit is reset to zero in accordance with the coding of the MIFS1-3 signals.

As can be seen from FIG. 12, the cache unit 750 transfers the requested data word (word 0) to the processing unit 700 by forcing signals 0PSW0-2 to a predetermined configuration to validate the transfer of word 0 via a ZDO 750-9 switch and a ZBP 750-902 switch.

The cache unit also forces the DATA-RECOV signal to a binary ONE to validate the sampling of the data word in the processing unit register. At the end of the THCFD cycle, the RBPSD flip-flop is authorized to be reset to binary ZERO. Laligne CPSTOPOO is thus set to ONE binary, which switches on the processing unit 700. However, the unit 700 does not perform any operation until the next cycle.

At this point, only the first pair of words is received and there are two more words pending. The unit 700 having completed the operations of cycle I relating to the instruction ADA will have generated another read command ZAC in the same way as that which has been described. The difference is that this command includes

197 an address specifying a block word 3 which is estimated. However, since the unit 700 was off, the cache unit 750 operates to accept the coded read command to specify a quadruple read operation signaled by the RADO / ZADO lines. At this time, the DMEM lines are reset to one to specify a simple cache read command while the DREQCAC line is set to ONE binary.

Likewise, the cache unit 750 writes the second read command to location 1. During this cycle, unit 700 also ends execution of the LDA instruction under microprogrammed command. This is how the requested data word is loaded into register A as a function of the content of register ERDX-B.

As previously described, the cache unit 750 performs a directory search by sending the most significant address bits to the directories 750-500 and 750502. During this time, while the comparison circuits of blocks 750-536 to 750-542 generate an output signal indicating a correspondence condition, the waiting bit invalidates the correspondence detection / absence of directory correspondence circuits 750- 560 by preventing them from forcing the BPSD signal to ONE binary. In addition, the PENBIT signal used to generate the signals setting the busy status indication bits to one is binary ZERO. This prevents the setting of one such indication bits in registers 750-120 and 750-122.

As can be seen in Figure 12, since the wait bit for the requested block has been set to ONE binary, the cache unit 750 is in operation to perform the 4 groups of actions in parallel indicated. Of course, when the wait bit is not set to ONE binary, the cache unit 750 transfers the requested word to the processing unit 700. First, the waiting bit set to one causes the PBPSD flip-flop to go to ONE binary, which in turn turns the processing unit 700 off. It remains off until the data word is received from main memory 800.

The wait bit set to one also prevents the CAOPR command flip-flop from being set to binary ONE. From the operation of the circuits generating requests to the main memory 800, the command is therefore effectively seen as a condi2425110

198 tjon of absence forced by the wait bit set to one. This action prevents a double command from being sent to the main memory 800.

It can be seen in FIG. 12 that the waiting bit set to one causes the setting of binary UNS of the flip-flops ZCDL, PENBIT-WAIT and PENBIT. The ZCDL flip-flop establishes a standby state used as explained to reset the execution of other commands stored in the buffer RZAC 750-102. In this way, when incompatibilities regarding redundant commands or recovery conditions which could occur by transferring incorrect data to unit 700 are detected by cache unit 750, which sets the bit of wait, the ZC-DL flip-flop is thus set to ONE binary.

The PENBIT-WAIT flip-flop once set to ONE binary delays the execution of the operation sequence starting with the PRE-OK state until all memory commands are waiting which request data from memory main whose operation was blocked by setting the wait bit to one is processed. Of course, this relates to commands other than the command being executed by the cache unit 750.

The PENBIT flip-flop once set has the essential function of establishing the conditions existing during the initial reception of the command (DREQCAC) to which a response had not been made due to the wait bit set to A binary. Until reception of the requested data, the ZCDL flip-flop remains at binary ONE. As long as it is at ONE, it ensures that the unit 700 remains off-circuit in all cases. ~

In the present case, the main memory 800 then transmits the first word (word 2) of the block of 4 words requested from the cache unit 750. This is how, by this transfer, the SIU unit 100 forces again the ARDA line has a binary ONE, which indicates that the even word of the pair (word 3) is available on the DFS lines. Again the SIU 100 also forces the DPFS line to ONE binary to indicate a double word transfer.

While the ARDA line is ON, the cache unit 750 loads the third data word into the register RP 750-179. In addition, identification signals from

199 multiples from the MIFS lines, coded to indicate the transfer of a second pair of words from the requested block, are loaded into the RMIFS register 750-124. This is how MIFS signals indicate that words 2 and 3 are received (for example, a code of 100).

In addition, the MIFS signals select the corresponding part at a location 0 to establish whether the pair of words is the second pair. If this is the case, the exclusive OR circuit 750-131 which forces the positioning signal BB to ONE binary. It follows that the SECRCV signal is set to ONE binary.

As described previously, MIFS bit signals 2 and 3 are used to gain access to location 0 of the buffer RZAC 750-102 which stores the first read command ZAC, now being executed. The control address is sent via the ZAC switch 750-152 to the cache memory 750-700 and to the directories 750-500 and 750-502.

In parallel with this access, word 3 is transferred to the register RDO 750-180.

By switching the OATB flip-flop, the second word (word 3) is loaded into the register RP 750-179. It is then loaded into the RDI register 750-180. When the next clock pulse occurs, the THCFD flip flop goes to binary ONE. Under the control of this flip-flop, the second pair of words (words 2 and 3) are written into the block location of cache memory 750-700 specified by the ZAC command address bits sent by the switch. ZAC 750-152.

The second activity bit is also reset to sero in accordance with the coding of the MIFS1-3 signals at the end of the THCFD cycle. Since the SECRCV signal is at binary ONE, it allows the wait bit to be reset to binary ZERO. This reset is done by means of an AND circuit contained in block 750-512. This AND circuit combines the RSPENO-3 complement signals with the wait bit signals read from the read wait block of the 750-500 command directory. The RMIF bit signals 2 and 3 are used to select the register memorizing the signals written to the BKDCDO-3 signal whose complements correspond to the RSPENO-3 signals. 2425110

200 te that the wait bit previously set to one is masked and the resulting value is re-written to the control block of 750-500. Thus, the wait bit previously set to one is reset to binary ZERO.

As seen in FIG. 12, the completion of the execution of the first simple read command makes it possible to reset the PENBIT-WÂIT flip-flop to binary ZERO. This is due to the fact that at this time no read pending command implements main memory (i.e., no reception of other data from main memory is pending). The operations for this series of actions are terminated as indicated by the symbol END. Resetting the PENBITWAIT flip-flop allows the cache memory unit 750 to initiate the synchronization sequence following the ZCDL status cycle.

Since the unit 700 has not finished processing the second read command, the read address pointer value produced by an output counter, not shown, has not been increased. Thus, when this value is compared with the address indicating the next empty location, the result indicates that there is still a read command in the buffer RZAC 750102.

Consequently, the PRE-OK toggle changes to A BINARY. When set to one, this toggle indicates that the cache unit 750 has attempted to execute a read command and has formed the wait bit set to one which corresponds to the block specified by the command address. Under the command of the PRE-OK toggle, the read command stored in a location 1 specified by the output counter (COUT) is read and the command address is sent via the ZAC 750-152 switch to 750-500 and 750-502 directories and 750700 cache memory.

Following the extraction of the command, the PRE-OK flip-flop is reset to zero while the UG-OK flip-flop is set to ONE binary. This flip-flop allows the cache memory unit 750 to perform operations similar to those performed in response to setting the DREQCAC line to one. However, such actions will not include shutting down the processing unit 700, establishing a directory assignment, and

201 sending a memory request.

Under the control of the flip-flop UG-OK, the cache unit 750 performs a directory search operation. Since the launching of this sequence of operations is carried out for a read command whose implementation has been delayed, the comparison circuits of blocks 750-536 to 750-542 generate an output signal indicating a correspondence condition. Since the wait bit associated with the specified block has been reset, the cache unit 750 performs the indicated remaining operations.

It will be noted that, when the flip-flop UG-OK is set to binary ONE, it validated the reset to binary ZERO of the flip-flop PENBIT (that is to say, UGOK. HOLDCAC.CACBSYl = 1). This in turn ends the actions associated with the PENBIT toggle as the END symbol indicates. Consequently, it allows the unit 700 to be switched on during the UG-OK state cycle. Before that, however, the output counter address advances by one and the requested data word (word 3) is transferred to unit 700.

At this time, the DATARECOV signal is forced to ONE binary, which validates the sampling of the processing unit registers. This ends the sequence of actions at the end of which the UG-OK flip-flop is reset to binary ZERO. During the next operating cycle, the unit 700 executes, under microprogrammed command, the instruction ADA. This is how the execution unit adder 714-20 adds the content of register A, selected according to the content of register RRDXB sent on the lines ZEB, to the value sent on the lines RDI by the unit. 750 cache memory. The result is transferred to register A via the ZRESA bus and switch 714-36.

Note that if there are more deferred commands, the same sequence is executed but the ZCDL flip-flop cannot be reset to binary ZERO. The ZCDL toggle can only be reset when there are no other pending commands. An example in which additional read commands can be deferred is where the unit 700 issues two pre-read commands followed by a single read command.

202

In addition, it should be noted that the arrangement of the present invention prevents incompatibilities during the extraction of new instructions. For example, it is assumed that the processing unit 700 begins processing a transfer instruction. During the operating cycle I, the unit 700 generates a pair of commands sent via the DMEM lines. As previously described, the cache unit 750 operates to set a first wait bit in response to the extract command 1 from I and a different second wait bit in response to the command extract 2 from X. When the cache unit 750 receives the 4 words from a block of the main memory 800, it switches on the unit 700 which begins the execution of a first instruction contained in the first block extract. Thus, the extract command 2 of I is treated as a pre-read command in the sense that the unit 700 can continue to operate during the extract operation.

Such an instruction is meant to be an A load instruction which includes an address designating one of the words in the block which is retrieved in response to the extract cache command 2 of I.

Consequently, the cache unit 750 operates, in response to the simple read command generated in response to the loading instruction of A, by detecting the presence of the wait bit set to delay the execution of the read command until all the words of the block specified by the extract command 2 of î are received. In addition, the unit 700 is switched off. When the words of the second block are received, the cache unit 750 performs operations similar to those described in connection with the second read command discussed above.

From the above it can be seen how the arrangement of the present invention prevents interference between memory commands as well as the issuance of duplicate commands.

In addition, the arrangement of the invention can be used to facilitate the diagnosis of the cause of errors or faults in the processing unit. In the system of FIG. 1, the input-output processing unit 200 is capable of emitting corn2425110

203 PI commands which make it possible to examine the content of the various registers contained in the processing unit 700.

In addition, this unit 200 is capable of examining the content of memory blocks contained in the cache unit 750. If we assume the presence of an apparent fault in the unit 700, the unit 200 transmits a coded PI command to specify that the preparation counter 75O-lOO0 can be loaded with a particular address.

By decoding the PI command, the requested signals are generated to send an address value on ZPIDT29-35 lines for loading into the 750-1000 counter.

Then, the unit 200 issues a second coded PI command to specify a read operation. A predetermined part of the control signals is sent via the lines ZPIB9-10 to the decoder circuits 750-1002. During a cache read operation, circuit 750-1002 generates signals which select the appropriate group of command directory signals (ie, signals RSPENO-3, 0LDPEND0-3, RDR F / EO-3, etc ....). These signals joined to the most significant address signals from the 750-502 directory are sent to the OR circuits of a block 750-712 and transmitted to the unit 200 via the PDTS lines of the PI interface 602. By examining the states of the wait bit signals, the unit 200 can establish an unsuccessful completion of the operation of sending a memory request and returning all of the words of a block. In such a case, the unit 200 extracts from the directory 750-502 the address corresponding to a group of waiting bits. By receiving such address signals and matching the signals to the least significant address signals, the utility 200 could then access main memory 800 to find which instruction or data being the subject of a execution or access upon detection of the fault. In this way, by being able to examine the contents of waiting bits of the 750-500 command directory, it is possible in a short time to limit the problem to a particular zone.

14251U

204

APPENDIX A

SINGLE-WORD INSTRUCTIONS

DATA MOVEMENT

LDA Loading A

LDQ Loading Q

LDAQ Loading AQ

LDA C Loading A and delivery to O

LDQC Loading Q and delivering to O

LDXn Loading Xn (n = O, 1, .... 7)

LXLn Loading If from least significant bits (n = G, 1, ... 7) LCA Loading complement A

LREG Loading registers

LCQ Loading Q supplement

LCAQ AQ complement loading

LCSn Load complement Xn (n = O, 1, .... 7)

EAA Effective address for A

EAQ Effective address for Q

EÀXn Effective address for Xn (n = 0, 1, .... 7)

LUT Loading register indicator

SIA Memorization A

STQ Memorization Q

STAQ AQ memorization

STXn Loading Xn in most significant bits (n = 0, 1, ... 7)

SXLn Loading Xn in least significant bits (n = O, 1, ... 7)

SREG Register storage

STCA Character storage of A (6 bits)

STCQ Character storage of Q (6 bits)

SI3A Character storage of A (9 bits)

STBQ Q character storage (9 bits)

STI Register indicator storage

STT Register synchronizer storage

SBAR Memorization of registry address

STZ Zero storage

STCI Meter instruction memorization plus 1

S TC 2 Counter instruction save plus 2

ARS Offset A right

QRS Shift Q right

LRS Long Shift Right

ALS Offset A left

LLS Long Shift Left

205

APPENDIX A (continued) SINGLE-WORD INSTRUCTIONS

ARL DATA MOVEMENT Logic A on the right

QRL Logic Q right

LRL Logic Long right

ARL 'Ηοΐη £ 1 ° η.Α left QLR Rotation Q left

LLR Long Rotation left

APPENDIX A

SINGLE-WORD INSTRUCTIONS

CALCULATION IN COMMA ΕΙΧΕ

ADA Add to A

ADQ Add to Q

ADAQ Add to AQ

ADXn Add to Xn (n = 0, 1, .... 7)

ASA Add stored value to A

ASQ Add stored value to Q

ASXn Add stored value to Xn (n = 0, 1, ... 7)

ADLA Add logical value to A

ADLQ Add logical value to Q

ADLAQ Add logical value to AQ

ADLXn Add logical value to Xn (n = O, 1, ... T)

AV CA Add with carry forward to A AWCQ Add with carry forward to Q ADL Add least significant to AQ AOS Add a stored value SDA Subtract from A

SBQ Subtract from AQ

SBXn Subtract from Xn (n = 0, 1, .... 7)

SSA Subtract stored value from A

SSQ Subtract stored value from Q

SSXn Subtract stored value from Xn (h = 0, 1, .... 7)

SBLA Subtract logical value from A

SBLQ. Subtract logical value from Q

SBLAQ Subtract logical value from AQ

SBLXn Subtract logical value from Xn (n = 0, 1, ... 7)

SWCA Subtract with carry over from A

SWCQ Subtract with carry over from Q

<td></td><td>206 APPENDIX A (continued) SINGLE-WORD INSTRUCTIONS = FIXED-POINT CALCULATION</td>

<td>Mpy</td><td>Multiply whole number</td>

<td>JIPF</td><td>Multiply fraction</td>

<td>DIV</td><td>Divide whole number</td>

<td>SAID</td><td>Divide fraction</td>

<td>NEG</td><td>Reverse A</td>

<td>NEGL</td><td>Reverse Long. BOOLEAN OPERATIONS</td>

<td>ANA</td><td>AND on A</td>

<td>ANQ</td><td>AND on Q</td>

<td>ANAQ</td><td>AND on AQ</td>

<td>ANXn</td><td>AND on Xn (n = 0, 1, .... 7)</td>

<td>ANSA</td><td>AND on stored value A</td>

<td>ANSQ</td><td>AND on stored value Q</td>

<td>ANSXn</td><td>AND on stored value Xn (n = 0, 1, ... 7)</td>

<td>ORA</td><td>OR on A</td>

<td>ORQ</td><td>OR on Q</td>

<td>ORAQ</td><td>OR on AQ</td>

<td>ORXn</td><td>OR on Xn (n = 0, I, .... 7)</td>

<td>ORSA</td><td>Or on stored value A</td>

<td>ORSQ</td><td>OR on stored value Q</td>

<td>ORSXn</td><td>OR on stored value Xn (n = 0, 1, .... 7)</td>

<td>ERA</td><td>OR exclusive on A</td>

<td>ERQ</td><td>OR exclusive on Q</td>

<td>ERAQ</td><td>OR exclusive on AQ</td>

<td>ERXn</td><td>OR exclusive on Xn (n = 0, 1, ..... 7)</td>

<td>ERSA</td><td>OR exclusive on stored value A</td>

<td>ersq</td><td>OR exclusive: on stored value Q</td>

<td>ËKSXh</td><td>Exclusive OR on stored value Xn (n = 0, 1, ... 7). COMPARISON</td>

<td>CMPA</td><td>Compare to A</td>

<td>CMPQ CMPAQ</td><td>Compare to Q Compare to AQ</td>

<td>CMPXn</td><td>Compare to Xn (n = 0, 1, .... 7)</td>

<td>CTK</td><td>Compare to limits</td>

<td>CMG</td><td>Compare to a size</td>

<td>CJK</td><td>Compare to hidden value</td>

SZN

ZSNC 'CANA CANQ

CANAQ CANXn CNAA CNAQ CNAAQ

CNAXn

FLD

DFLD

LDE

FS T

DFST STE FS IR. DFSTR.

ADF

UFA

DFAD

DUFA

ADEi FSB UFS DFSB DUFS

FMP

UFM

DFMP

DUFM

207

APPENDIX A (continued)

SINGLE-WORD INSTRUCTIONS

COMPARISON

Set one of the Zero and Negative Memory Indicators

Reset and Reset Zero and Negative Memory Indicators

AND comparison with A

AND comparison with Q

AND comparison with AQ

AND comparative with Xn (n = 0, 1, ... 7)

NOT compared with A

NOT compared with Q

NOT compared with QA

NOT comparative with Xn (n = 0, 1, ...- .. 7)

FLOATING POINT

Floating point loading

Double precision floating point loading

Exhibitor loading in register

Floating point storage

Double precision floating point memory

Exhibitor loading in register

Floating point rounding and storage

Floating point rounding and storage with double precision

Floating point addition

Non-standard floating point addition

Double precision floating point addition

Non-standard floating point addition, double precision

Add Exhibitor to Register

Subtract floating point

Subtract non-standard floating point

Double precision floating point subtract

Subtract non-standard floating point and double precision

Multiply floating point

Multiply non-standard floating point

Double precision floating point multiply

Multiply non-standard floating point, double precision.

242511θ

<td></td><td>208 APPENDIX A (continued) SINGLE-WORD INSTRUCTIONS FLOATING POINT (continued)</td>

<td>FDV</td><td>Split floating point</td>

<td>EDI</td><td>Divide in floating point and with inversion</td>

<td>DFDV</td><td>Double precision floating point split</td>

<td>DFDI</td><td>Split into double precision floating point and with inversion</td>

<td>FNEG</td><td>Perform a floating point inversion</td>

<td>FNQ</td><td>Floating point normalization</td>

<td>EDF</td><td>Floating point rounding</td>

<td>DFRD</td><td>Floating point rounding with double precision</td>

<td>FCMP</td><td>Floating point comparison</td>

<td>FCMG</td><td>Floating point size comparison</td>

<td>DFCMP</td><td>Double precision floating point comparison</td>

<td>DFCMG</td><td>Comparison of size and floating point, double preci if we</td>

<td>FSZN</td><td>Setting to zero and negative floating point memory flags TRANSFER OF ORDER</td>

<td>IRA</td><td>Unconditional transfer</td>

<td>ISXn</td><td>Transfer and update to a registry index</td>

<td>ISS</td><td>Transfer and set to a slave ”</td>

<td>RET</td><td>Return</td>

<td>ΊΖΕ</td><td>Transfer to zero</td>

<td>ΊΝΖ</td><td>Transfer to non-zero</td>

<td>TMI</td><td>Transfer on less</td>

<td>TPL</td><td>Transfer over</td>

<td>TRC</td><td>Transfer on deferral</td>

<td>INC</td><td>Transfer on non-carryover</td>

<td>TOV</td><td>Transfer on overshoot</td>

<td>TEO</td><td>Transfer on positive exhibitor overrun</td>

<td>TEU</td><td>Transfer on negative exhibitor overrun</td>

<td>TTF</td><td>Transfer to OFF counting end indicator disabled</td>

<td>TIN</td><td>Transfer to end of ON counting indicator validated</td>

<td>TPNZ</td><td>Transfer over plus and non-zero</td>

<td>TMOZ</td><td>Transfer to minus or zero</td>

<td>IR IN</td><td>Transfer to valid ON truncation indicator</td>

<td>TRTF</td><td>Transfer to OFF OFF section indicator.</td>

NOP

BCD GTB XEC XED MME ^DRLRPT RPD RPL RCCL ^SPLLPL

LARn

LAREG

2o SARn SAREG AWD

AOBD

A6BD

A4BD

ABD

SWD

S9BD

S6BD

S4BD

209

APPENDIX A (continued)

SINGLE-WORD INSTRUCTIONS

VARIOUS

No operation

Switching from binary to decimal binary coded

Switching from Gray code to binary code

Execution

Double execution

Main or master mode input

Deviation

Repetition

Double repeat

Repeat link

Reading clock calendar

Storage pointers and lengths

Loading pointers and lengths.

ADDRESS REGISTER

Loading address register n

Loading address registers

Storage in address register n

Storage in address registers

Addition of word displacement and AR address register content specified

Addition of 9-bit character displacement and AR address register content

Addition of 6 biis character shift and AR address register content

Addition of 4-bit character displacement and AR address specified register content

Addition of bit shift and AR address register content specified

Subtraction of word displacement and AR specified register content

Subtracting 9-bit character displacement and AR address register content

Subtracting a 6-bit character move and the specified address register content AR Subtracting a 4-bit character move and the specified address register content AR

210

APPENDIX A (continued)

SINGLE-WORD INSTRUCTIONS

ADDRESS REGISTER (continued)

SBD Subtraction of bit shift and AR address register content

AARn Alphanumeric descriptor in address register n, ARn NARn Numeric descriptor in address register n, ARn ARAn Address register n, ARn, to alphanumeric descriptor

ARNn Address register n, ARn, to digital descriptor SINGLE-WORD INSTRUCTIONS

MAIN MODE

DIS Delay until interruption

LBAR Loading base address into register

LDT Synchronizer loading in register

LLUF Loading lock in defective register

SCPR Replacement by SFR

SFR Faulty register storage

LCCL Loading clock calendar

RIMR Reading mask of interrupts in register

LIMR Nasal loading of interrupts in register

RRES Reading reserved area in memory

CIOC I / O input / output channel connection

MEMORY EXTENSION

LBER Loading base extension in registry

LMBA Loading Marten bar A

LMBB Loading Master Bar B

SBER Memorization of base extension in register

SMBA Master Bar Memorization A

SMBB Master Bar Memorization B

MLDA Loading Master A

MLDQ. Loading Master Q

MLDAQ Loading Master AQ

MSTA Master A Memorization

MSTQ Master Q Memorization

MSTAQ AQ Master Storage

RPN Reading the processor number

HALT Stop.

MLR 5 URL

MVT

CMPC

SCD

SCDR

TCT TCTR SCM SCMR

MVN

CMPN

AD3D

AD2D

SB3D SB 2D MP3D MP2D DV3D

DV2D

CSL

CSR

SZTL

SZTR

CMPB

DIB

BTD

211

APPENDIX A (continued)

MULTIPLE MONTH INSTRUCTIONS

ALPHANUMERICS Alphanumeric value transfer from left to right Alphanumeric value transfer from right to left Alphanumeric value transfer with translation Alphanumeric character string comparison Double character analysis

Reverse double character analysis

Character control and translation

Character check and translation in reserve

Analysis with mask

Analysis with mask in reserve '' MULTIPLE MONTH INSTRUCTIONS

DIGITAL

Digital value transfer

Numerical value comparison

Addition using three-decimal operands Addition using two-decimal operands Subtraction using 3-decimal operands Subtraction using 2-decimal operands Multiplication using 3-decimal operands M ultiplication using 2-decimal operands Division using 3-decimal operands Division using 2-decimal operands.

BIT CHAINS

Combination of bit strings to the left

Combination of bit strings to the right

Zero indicator and truncation with bit chains to the left

Setting a zero indicator and truncation with bit strings to the right Comparison of bit strings

SINGLE-WORD INSTRUCTIONS

CONVERSION

Decimal to binary conversion

Binary to decimal conversion.

212

TRANSFER OF VALUE FORMATTED MVE Transfer of alphanumeric value formatted

MVNE Transfer of formatted digital value

MULTIPLE MONTHS

CMPCT Character Comparison and Translation

MTR Transfer to registry

MTH Transfer to memory

MVNX Explicit digital value transfer

CMPNX Explicit numerical value comparison

AD3DX Addition using 3 explicit decimal operands AD2DX Addition using 2 explicit decimal operands SB3DX Subtraction using 3 explicit decimal operands

SB2DX Subtraction using 2 explicit decimal operands MP3DX Multiplication using 3 explicit decimal operands

MP2DX Multiplication using 2 explicit decimal operands

DV3DX Division using 3 explicit decimal operands DV2DX Division using 2 explicit decimal operands MVNEX Transfer digital value formatted and explained

VIRTUAL MEMORY CONTROL

PRIVILEGED INSTRUCTIONS

LDWS Loading registers workspace

STWS Memorization in registers workspace

LDSS Loading content from register to register

STSS Storage of content from register to register

LDAS Loading stack of arguments in register

LDPS Loading stack of parameters in register

LPDBR Loading table directory page in basic register

SPDBR Memorization of table directory page in basic register

LDDSD Load data stack descriptor into register STDSD Storage of data group descriptor into register

LDDSA Loading of data stack address in STDSA register Storage of data stack address in CAMP register Erasing of an associative memory organized in pages

213

APPENDIX (CONTINUED) VIRTUAL MEMORY ORDER

PRIVILEGED INSTRUCTIONS

CCAC Clear cache

EPAT Effective address and control pointer

VIRTUAL MEMORY CONTROL

ALL MODES INSTRUCTIONS

LD0 Optional loading in register ST0 Optional storage in register STPS Storage of parameter stack in register STAS Storage of argument stack in register

NOT POP argument stack

LDDn Loading descriptor (register) n

SDRn Descriptor storage (register) n STPn Pointer storage n

LDPn Loading pointer (register) n

STDn Storage descriptor in register n

EPPR'n Effective pointer in register n of LHEAn pointer Loading extended address n

CLIMB Transfer domain

214