Untitled record

Mandatory: Public establishment known as: National Research Development Agency, Aurore Tower, Cedex n. 5, 92080 Paris-Défense.

Multiple recording system on a single track, and corresponding equipment.

72J Invention of: Gérard Vicente.

33) (32 (31

Conventional priority;

Sale of booklets at IMPRIMERIE NATIONALE, 27, rue de la Convention - 75732 PARIS CEDEX 15

The invention relates to recordings with pluralities of tracks among which it is intended to occupy only one track to locate and identify each part of the recordings on the other tracks.

More specifically, the invention aims to quickly and precisely identify time, particularly interesting sequences during recording on a multitrack recorder, and the invention still aims to identify and characterize events produced or occurring during said recordings. The interest is clear to occupy for these purposes only one track, and to keep all the other tracks for the recordings proper.

Briefly, th e signal on the single track according to the invention can take five levels, defined in advance, three of which correspond respectively to rest, to monitoring, and to the marking of events, and two of which respectively correspond to time tracking and digital tracking of recordings. The invention also relates to an apparatus allowing said recordings on the single track.

The invention, its system and an apparatus according to the invention will be described with reference to the following figures, which are given by way of non-limiting examples:

- Figures 1, 2, 3 are three explanatory graphs, said five levels as a function of time;

- Figure 4 is a block diagram of an apparatus according to the invention; ^x ·.

- Figure 5 is the block diagram of the time base of Figure 4;

- Figure 6 is the block diagram of a clock of Figure 5;

- Figure 7 is the block diagram of a scale of Figure 5;

- Figure 8 is a graph of the signals of the rocker of Figure 7;

- Figure 9 is the block diagram of a counter beyond Figure B;

- Figure 10 is the block diagram of the reset of the counter of Figure 9;

- Figure 11, similar to Figure 10, relates to another counter of Figure U;

- Figure 12, is the block diagram of a registration generator

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E 4;

'' a monostable from par 5 of an adaptation circuit of

- Figure 31 is the block diagram of the remote display of Figure U;

- Figure 32 shows a fragment-sequence drawer of an apparatus according to the invention;

. ,, of a device,.

- 'Figure 33 shows an events drawer / according to the invention.

The signal provided by the five-level technical track according to the invention is recorded on one of the chains of the recorder (magnetic, paper ...) and can then be re-read by an operator or directly by a computer.

For this, we show at the output terminals of the device a voltage which can only take five values ​​or levels, defined in advance: F, S, E, C ^, Co.

With reference to Figure 1:

1 °) The level F (- 0.5 volt) is used to indicate the parts of the layout where no particular event occurs. This level will be conventionally called: Fragment.

2 °) Level S (+ 0.5 volts) identifies the other periods which will generally be processed by a computer or calculator. This level will be called sequence. .

3 °) During this sequence, a level E (+ 1 volt) will be used for marking particularly interesting events.

It is important to note, that the passage from level F to level S (beginning of sequence), must coincide with the arrival of the 1st event 'to be treated, and that the duration between the last event and the end of the sequence, must be at least equal to the processing time of the event considered.

We can finally, to differentiate various events, adopt durations of level E different and 'specific to each of them.

With reference to figure 2:

level C ^ indicates one (1) and level C ^ indicates zero (0).

levels C ^ and 0θ are used for temporal location of the fragment. Using a clock associated with a counter, a series of coded pulses determining a number is regularly recorded (with a time interval which is fixed beforehand). This number, readable on the recording, can be selected by a computer.

The periods thus delimited are transcribed in serial DCB code (binary coded decimal), language perfectly readable on a paper recording.

The reading is done from left to right, the first four pulses indicate the hundreds, the next four the tens and the last four the units of a number.

The periods thus identified, it is useful to be able to also distinguish certain sequences. We therefore use, in an identical manner, the preceding methods and devices, the inscription being made before the start of each sequence, (fig. 3).

We can for example use the numbers 0 to 99 for tracking sequences, and the numbers 100 to 999 for tracking periods. Finally, the output signal from the technical track according to the invention can have the appearance of FIG. 3.

With reference to FIG. U, which is a block diagram of an apparatus according to the invention: this apparatus ensures the following main functions:

- the time base 100;

- 200 counters and displays;

- the registration generator 300;

- the shift register 400;

- the event sorting circuit 500;

- the summator 600;

- 700 remote viewing of meters.

This set has a control input C (fragments, sequences), an input E (events), and an output S.

With reference to Figure 5; this time base 100 comprises an oscillator or clock 101, a frequency divider 102, and an RS flip-flop 103; it is provided with said control input C,. „_x of an input 106 of fip of sequence of an input 104 of stop, of an input 105 of start of sequence, / of an output 107 of period, and of an output 108 of epoch number.

With reference to Figure 6; the oscillator or clock 107 comprises two logic circuits BT 109 and 110, two NPN transistors 111 and 112, and an RC circuit with capacitor 113 and resistance adjustable by jumps 114.

The oscillation frequency is set ·· ¹ ir capacitance 113 (10 microfarads) and resistor 114 variable: a factor allows the value R to be changed in leaps and obtaining 6 frequencies. For operation to be possible, inputs A and B must be at 1 (A = B = 1). Under these conditions, the two ETs and 112 only have a reversing role. 111 adapts the output impedance formed by the RC cell to the input of transistor 112. R can thus take very large values ​​(400 kiloohms). At time To, we have B '= l, a state which implies D = 0 and A' = 0. The voltage of 5 volts charges the capacitor 113 through the resistor 114. At time T ^ the voltage on the base of 112 unlocks it, whence passage of the oscillator in the complementary state.

The cycle continues identically. To block the oscillator, simply set one of the inputs A or B to the 0 ”state.

When A = 0 the oscillator stops immediately.

When B = 0 the oscillator stops at the end of the cycle.

In both cases, the oscillation resumes as soon as A and B are returned to the 1 ”state.

The frequency divider by 16 (reference 102 from there Figure 5) allows. do not excessively increase the RC product of the clock 101 when it is desired to have a very long period (for example 100 seconds). This divider can for example be conventionally constituted by four stages of division by two, for example four JK flip-flops, and will therefore not be described in detail.

This divider can be in the same integrated circuit SN 7493 N.

With reference to FIG. 7: this flip-flop 103, composed of two AND circuits, composed of two AND gates, controls the operation of the oscillator at input A (fig. 6). It is necessary that the oscillations only occur in fragmented position at the exit of the technical track. The operation of the assembly is explained by the graph according to FIG. 8. By connecting output Q to input A of the astable (clock control), we see that the oscillations stop because the pulse on DS causes * 7 to go to state 0.

With reference to FIG. 9: the technical track according to the invention comprises three counters (block 200, fig. 4) which are used to count respectively s

- epochs (with three digits)

- sequences (with two digits)

- events (with two digits).

They are identical in their designs (fig. 9). Two characteristics differentiate them:

- the number of decades

- reset.

Each decade is made up of four JK flip-flops connected in a conventional manner such that there are four outputs marked A,

B, C, D the information contained in the decade in parallel binary coded decimals. Their respective weights are: 2,2,2,2³.

Each decade is achieved by an integrated circuit SN 7490 N.

The epoch counter must indicate the numbers between 100 and 999 and the purpose of resetting is to preposition it to 99 (fig. 10).

a) When the appliance is powered up by pressing the push button 205.

b) When the counter reaches the number 999 / that the next pulse will reset it to 0. The transition taking place on the output D of the decade of hundreds, it triggers a monostable which sends a brief pulse positioning the counter at 99.

The reset of the sequence counter is simply carried out by a push button.

The reset of the event counter (fig. 11) is carried out in an identical manner to that of the Epochs, the zeroing being done by a push button during power-up, and by a signal from the RS flip-flop ( fig. 7) when switching to Sequence.

The display of the information contained in each decade is executed in a conventional manner and will therefore not be described.

With reference to FIG. 12: this registration generator 300 comprises a monostable rocker 301 making it possible to write the Epoch number, an oscillator 303, a monostable rocker 302 making it possible to write the sequence number, a divider by five 304 , and a circuit 305 for routing the various signals.

The registration generator provides three groups of four pulses spaced 20 mns apart; the duration between two groups being 60 min (fig. 13).

The monostable 301 (fig. 14) receives the signal from the time base 100 to register the period number. It includes doors allowing it to be triggered on any signal from various sources and an RC delay circuit making it possible to adjust the width of the pulse in C. All these circuits are located in an SN 79121 box.

To have 560 mns of duration, ο, υ uses R = 30 Kiloohms and C. = microfarads. The monostable vi allows the oscillator to operate during these 560 minutes, thus delivering a train of 19 pulses.

The monostable 302 (fig.16) is identical to the previous one: it gives a pulse of 560 mS to register the number of the Sequence, and it is triggered by the signal coming from the rocker RS ​​103 (fig.7).

An AND gate (fig. 15) prohibits the operation of this monostable if an Epoch number is being registered. If the operator goes into Sequence during this time. The information is stored and the monostable 2 acts as soon as the monostable 1 has finished operating.

The oscillator 303 is identical to the oscillator 101 of FIG. 6. It includes the same elements. Its operation is controlled by monostables 301 and 302 (fig. 16). To have 20 ms pulses, you have to put 220 Kiloohms in 119 and 0.1 microfarad in 113.

by 5

The divider / 309 (fig.17) suppresses the 5th and 10th pulses supplied by the oscillator 303, so as to have 60 ms between two groups of four pulses.

The divider itself is formed of tees according to Figure 17 using a three JK flip-flops integrated SN 7990 N. circuit.

The operation of the assembly is shown in Figure 18.

The switching circuit 305 includes an AND (fig. 15) controlling the operation of the monostable 302.

- the inverter circuits, OR and AND (fig.17) allow the correct functioning of the divider by 5 of the oscillator.

- a circuit AND controls the oscillator either by the monostable 301, or by the monostable 302.

With reference to Figure 19: the shift register (block 400 of Figure 4) includes:

- three shift registers 401 type SN 7494 N allowing the parallel-series transformation of the information contained in the counters;

- a monostable 404 for zeroing putting the registers at rest before each entry of a number, a monostable 405 for selecting the Epoch counter, a monostavle 406 for selecting the Sequence counter, and routing circuits 407. This assembly has two outputs: an output of which the bis signifying the zero, the other output gives the bits signifying the one.

With reference to FIG. 20: a register 401 is made up of 4 master-slave RS flip-flops. A set of switches allows you to select the counter to validate. The pulses from the registration generator are applied to input T.

Each pulse from generator 300 transfers information from one flip-flop to the next. At the end of the last one, there is successively the information of all the previous flip-flops, placed in series. Before each operation, a short pulse is applied which validates the counter 200 from which the information is output. This pulse imposes on the rocker the state corresponding to that of the counter.

Note (Figure 21) that the zero setting monostable delivers a pulse of 500 mano-seconds, and the selection monostable delivers a pulse of 1 microsecond.

The information is entered into the shift register during the time T₃ - T_2&gt; It is therefore obvious that the duration of the pulse of the selection monistable must be greater than that of the zero-setting monostable.

The routing circuit 407 (FIG. 22), by successive comparisons sorts at the output of the register the bits intended to mark the 1s, from those intended to mark the 0s.

With reference to FIG. 23: the sorting of events (block 500 of FIG. 4) includes:

an adaptation circuit 501 which makes the synchronization signal of the events compatible with the TTL circuits composing this technical track;

a circuit 502 for shaping these event signals;

- an authorization circuit 503 de-'ined to let events pass only when one is in; sequence sequence;

- a coincidence 504 which ensures i · switching to Sequence, from the first event to be processed; and¹ ·&gt; Passage at the end of the sequence on the event following the last one to consider;

- the stop 505 of the sequence which could be either manual using a push button, or determined '·&gt;' by the event counter.

The adaptation circuit 50i (fig. 21) includes a transistor 511 2N 3904 mounted as an emitter follower. r output is connected to the input of a TTL integrated circuit causing its switching as soon as the input exceeds the 2.5V threshold. Thanks to the Zener 512 type 1 N 750 diode, the event synchronization pulse can reach 100 V.

The shaping circuit 502 (fig. 25) is made up of a monostable flip-flop 515 type SN 74121 N..It provides an always identical event signal (10 ms) as soon as it is passed in sequence. For this a double security exists:

1) the 515 monostable scale only works if there is an authorization.

2) the event signal is only available at output if the sequence signal is present.

The event authorization circuit 503 consists of an AND with 3 inputs. It authorizes the operation of the monostable scale (fig.25) if the track does not mark numbers (Ep'oque or Sequence) and if there has been passage in Sequence.

Coincidence 504 tfig.26): between the passage in sequence of the signal of the track and the coming of an event, is done thanks to a rocker type D 517 controlled by a rocker RS ​​518.

In a flip-flop of type D, the output Q takes the same state as the input D on each command on the input T. The latter is connected directly to the output q of the event adaptation circuit 501 and therefore receives in permanently synchronize event signals. Input D is connected to an RS 518 flip-flop which is in state 0 if we are in fragment and in state 1 if we are in sequence. Figure 27 illustrates the operation of such an arrangement.

Stopping 505 of the sequence (fig. 28) can be done in two ways: 1 °) by acting on a push button 521,

2) by a predetermination of the event counter.

By acting on push-button 521, direct action on a monostable switches the rocker RS ​​518 to 0 (fig. 26).

The predetermination is done using two ten-position contactors 522 (one for the units, one for the tens) connected to the output of the event counter decoder 200. As soon as the number entered on the counter is equal to that displayed by contactors, a signal acts on the monostable. The effect is identical to the action of the push button. An inverter enables this predetermination to be switched off.

With reference to Figures 29 and 30 which relate to the adder (block 600 in Fig. H: at the output of all the circuits, the signals have a level of approximately 5 Volts in state 1 and of 0 Volt in state 0. To have a signal similar to that of fig.3, it is necessary to make the algebraic sum of the signals code 1, code 0, Sequence and Events.

In general, at the output of a circuit defined as in Figure 29, the output voltage V is equal to R₂ ”

Ri

R. + R. in // ή in

-E l_not in II ^ll_not in // with r ·· * 'τη in // and

E ^Rl_notⁱⁿ//

The diagram of the summer 600 being that of FIG. 30, the output voltage therefore has the value:

. _ς ς ς ^VS = - 77 &lt;^VS0&gt; - Î5Ô ^{U5 V) +} üô ^(VS!&gt; ⁺ you ^{(EV) +} fo

Cj}, (Ev.) And (Séq.) Being the logic levels of 5 V supplied by the different operators of the device.

Depending on the positions, the voltage V has the value: a) in the fragment position (15 V) = - 0.5 Volt

150

he

b) when a zero is marked:

5_ (15 V) 71 (4 V)

- 1 Volt

c) when one is marked

150

V) + y) = 0 Volt

d) in sequence position

V (15 V) + | θ (4 V) = 0.5 Volt

e) when marking an event

V = jfj &lt;15 V) ₊ dd (»V) + (4 V) = 1 Volt

Variable resistors in series with the input resistors are used to best adjust these different values.

With reference to Figure 31: the purpose of remote viewing (block 700 of Figure 4) is to reproduce the information contained in the Period or Event counters depending on whether the technical trail operates in fragment or in sequence.

In an application of the invention to medical research, this reproduction is placed in the field of the camera which monitors the subjects during the 'recording'. The images being taken on a / video recorder, one can thus make a correlation in replay between the video images and the physiological recordings.

The implementation diagram is given in Figure 31, it requires 4 pieces of information to have 1 digit. The Epoch counters being 3 digits, 12 circuits identical to that of Figure 10 are required to perform this operation.

In an application of the invention to medical research, the device described above was produced in integrated circuits, according to the technique known as medium-scale integration (MSI) and according to the technique known as transistor-transistor (TTL). The device was built in standardized chassis, that is to say in three drawers pluggable in a rack of 4 pumice; a power drawer (+ 5V2, 5A, +

15V10mA; -15V10mA; stabilized at 0.2%) and the two drawers described \

below.

The fragment-sequence drawer, the front panel of which is shown in Figure 32, includes:

- the 3-digit period counter 801 and that of the 2-digit sequence 802. On either side of these counters, are respectively the setting to 100 and to 0 (803, 804).

- a 6-position switch 805 allows you to select the duration between 2 epoch numbers (2 - 5 - 10 - 20 - 50 and 100 seconds for example).

- a start 806 and end of sequence command (manual 807) and a socket for these same remote commands 808, 809.

It is possible to stop the counting of epochs without going in sequence with a command provided for this purpose (810).

It is also possible to retranscribe the information of the Period or Event counters by a remote control socket (811). (Visualization of digital displays in another room for example).

The events drawer, the front panel of which is shown in Figure 33, includes:

- taking input of the indication of an Event 851.

- two output sockets reproducing this indication in a form compatible with vLogiqu © TTD (one positive 852), the other negative 853.

- the Event counter £ 54.

- the selection of predetermination 855 allows both to go back automatically in sequence, after a certain number of events chosen in advance.

· * General zeroing 856.

-, a switch 857 which enables the predeter mination to be switched off.