Circuit arrangement for composing and separating speech and data during the transmission in a digital switching network

A circuit for combining and separating speech and data

The invention relates generally to the fields of digital telecommunications and telecommunications, and more particularly to a circuit for combining and separating voice and data for transmission over a digital switching field, especially for home exchanges, wherein two or more terminals may be connected to the digital switching field. . The invention is particularly applicable to Electronic Private Automatic Branch Exchanges (EPABX) with voice and data capabilities, office automated telephone systems, technical workstations and smart terminals. The data can be utilized at end-user terminals or the data can be used to control and communicate between the beginning and end of the voice path.

Various PABX devices are known in the prior art, represented by U.S. Patent Nos. 3,943,297, 20,028,498, and 4,136,263. The first generation EPABX device recorded program control and used either electromechanical switching circuits such as an X-beam or a vacuum relay; or electronic analog circuits. These systems provided greater possibilities than the systems of a standard telephone unit with the activation of special25 codes interpreted by the system.

The prior art second generation EPABX uses digital switching circuits formed in either time-subscriber (TST) or space-time-space (STS), which resulted in a significant reduction in space. Examples of such second generation EPABX devices are the ROLM CPX and Wescon's digital PABX.

Going forward, telephones include multifunction devices that meet the requirements of both voice and data transmission, in fact with a digital data connection. Thus, the telephone unit actually includes, when forward, a digital data interface and an EPABX switch for both the digital data transmission network and the normal voice network. Therefore, it is necessary to transmit speech and data in digital form via a digital transmission network. A digital transmission network capable of transmitting speech and data in digital form over a network is described in U.S. Patent 4,201,891, entitled Expandable Digital Switching Network, issued to A. Lawrence et al., Which is assigned to the assignee of the present invention. Another example of a speech and data transmission system is U.S. Patent 4,317,962, issued to J. Cox et al., Also assigned to the assignee of the present invention. This invention, which can be considered as belonging to the third generation of EPABX technology, is capable of simultaneously transmitting speech and data on the same PCM channel, and is highly advantageous when used in connection with a digital transmission network, such as the aforementioned U.S. Patent No. 4,201,891. speech and data are transmitted on the same PCM channels. However, in U.S. Patent No. 4,201,891, speech and data in digital form are transmitted sequentially, whereas in the present invention, speech and data in digital form are transmitted simultaneously, i. at the channel times of each trunk.

The present invention discloses a data partitioning technique in which the data area of ​​speech PCM transmission is used to include both speech in digital form (e.g., from a telephone) and other data (e.g., from a data terminal) on the same channel in an information body having a large number of channels, i. 32 channels. This allows speech and data to be combined in a common information area and simultaneously transmitted on the same channel, frame by frame, via a digital transmission network to other system users, including PABX subscribers. Also, in accordance with the present invention, system users may separately selectively access a database system via a PABX so that the same information can be sent from the database system to a number of PABX subscribers, or so that different information can be obtained in the database system to multiple PABX subscribers and simultaneously transmitted to different users on different channels. . Information is transmitted from the database system via the voice bus of the telecommunications system.

In order to enable simultaneous transmission of voice and data to the same subscriber by a digital transmission system, such as that described in the aforementioned U.S. Patent No. 4,201,891, it has been found that the spare five bits of 16-bit PCM words per channel can be allocated for data transmission. so that one byte uses two frames. 5-bit and 8-bit information fields are not distinguished, but the complete channel is transmitted to both data and speech destinations. The target device, data terminal, or telephone keypad, etc. then separates the information field it needs. Alternatively, the data and voice fields can be separated in the PABX and transmitted / received independently of the terminals and telephone units. The system of the present invention combines 5-bit and 8-bit data and speech information fields into a single channel, thus allowing two fields to be transmitted simultaneously to a destination, such as a subscriber with a telephone keypad and a digital telephone. Of course, when such a terminal does not need / allow simultaneous traffic of speech and data; it can be used to communicate with other data terminals; data that uses the speech path as a transmission medium with converters, as is done today in the prior art. This does not preclude additional transmission of 5-bit data if desired.

For example, a four-wire terminal for a digital telephone provides an 8-bit path for digitized speech and a 5-bit data path. Speech and data originating from a single terminal can be transmitted over a digital transmission network to two or more destinations independently combined on a 16-word PCM channel. In a digital interface, speech and data bits mapped from two PCM channels in a separate network can be separated for transmission to a single digital telephone.

Data can be transmitted to terminals from data sources via the telephone voice bus. For example, the voice bus provides about 20 free channels for high-speed (64 K bit / second) transmission of voice data at high speeds, and 5-bit / channel / frame can be used to provide a 32 K bit / s serial path to up to thirty terminals simultaneously, regardless of on the use of speeches.

Therefore, it is a primary object of the present invention to provide in a telecommunications system in general and in a PABX exchange in particular the possibility of simultaneous transmission of speech and data on the same channel between one or more user terminals.

Another object of the present invention is to provide simultaneous voice and data traffic on a channel between multiple system users and / or PABX subscribers.

It is a further object of this invention to provide simultaneous voice and data traffic on a channel between one or more system users and / or a PABX subscriber and a database-based system.

It is a further object of this invention to provide a large number of system users, including PABX subscribers, simultaneously selectively transmit or receive speech and data to each other individually or by distribution, and simultaneously achieve a database system such that each subscriber can receive the same or different data from the database system. simultaneously via the voice bus of the system or PABX together with the users and / or subscribers of one or more other systems.

The above and other features and advantages of the invention are achieved by a circuit having the features given in the appended claims, which will be described in more detail below with reference to the accompanying drawing, in which

Figure 1 is a generalized block diagram showing a PABX switch that provides simultaneous bi-directional transmission of voice and data to users of a two-port system.

Figure 2 is a generalized block diagram of the system of Figure 1 adapted for use by a large number of users of a dual port system.

Figure 3 is a generalized block diagram of the systems of Figures 1 and 2, expanded to a three-port system that provides voice and data transmission and access to a database system.

Figure 4 is a generalized block diagram of four system users, each with voice and data capability, connected to each other and to a database system via a digital transmission network.

Figure 5 shows a data representation for combining digital speech and data on the same channel for simultaneous transmission in accordance with the present invention.

Figure 6 is a block diagram of a digital interface in accordance with the present invention.

Figure 7 is a transfer register representation useful for converting data words of one bit length to data words of another bit length.

Figure 8 is a representation of an audio bus suitable for use in the present invention.

Figure 9 shows the data flow of Channel 25 Associated Signaling (CAS) data when talking between CAS / DATA RAM and serial / parallel data conversion circuits.

Figure 10 shows the coupling and separation of half-byte data between CAS / DATA RAM and serial / parallel data conversion circuits.

Figure 11 is a CAS / DATA RAM control suitable for use in address generation and mapping read / write control to move data in and out of the CAS / DATA RAM.

Reference is made to Figure 1, which shows the simultaneous transmission of speech and data in a two-port traffic system. The voice and data are connected to the automatic subscriber exchange (PABX) 10 from a large number of voice and data terminals, one of which is illustrated by the telephone subscriber unit 12 and one of which is illustrated as the data terminal 14.

The subscriber telephone 12 and the data terminal 14 are connected via two-wire lines 16 and 18 to a transmission interface circuit 20 in a PABX switch 10, which is adapted to positive and negative pulses and also to allow the clock to be set. Alternatively, a conventional RS-232 converter for the computer terminal can be used for this purpose when used at either end of the cable 18.

The digitized speech and digital data are coupled to the digital interface circuit 22 to provide a two-way traffic link between the digital interface 22 and the digital transmission network 24, with forward links provided between the transmission interface 20 and the data terminal 14 and the subscriber unit 12. Alternatively, complete bidirectional transmission can be provided in a known manner to the PABX 10 by a well-known anti-reflection method, i.e. by 4-wire lines. The digital transmission network 24 preferably comprises a distributed control transmission network, the details of which are described in U.S. Patent No. 4,201,889. The digital transmission network 24 connects the channels of the digitally encoded data channels and the digital speech from any desired subscriber and data terminal to any other desired telephone subscriber or data terminal.

Figure 1 typically shows the connection of the subscriber 12 and the data terminal 14 to the subscriber 26 and the data terminal 28 via the relay network 24. Terminal interface 30 and digital interface 32 operate in the same manner as terminal interface 20 and digital interface 22. Control circuits 34 and 36, as described later and in the appended U.S. Patent No. 4,201,899, operate to provide and maintain transmission paths in the transmission network 24. The control circuits 34 and 36 also include a processing capability 35 for processing protocols between and between the digital interfaces 22 corresponding to the subscriber units and data terminals. For example, the control circuit 34 may be an Intel 8086 microprocessor for use, for example, in detecting an OFF HOOK message and adding ring tones, as described in U.S. Patent No. 4,349,703 to R. Chea and assigned to the assignee of the present invention.

Referring now to Figure 2, there is shown a simplified block diagram of the connection of multiple voice and data terminals to the PABX arrangement of Figure 1. The subscriber telephone units 1 ... N are connected to a part 100 of the analog speech interface 100 of the transmission interface. The data terminals 1 ... N are connected to the data terminal 102 of the transmission interface 20. An accessory interface 104 common to telephone line circuits, as mentioned above, is also included, for example, generating a ring signal, as described in the aforementioned U.S. Patent 4,349,703, also connects keyboards for controlling / exchanging data with the controller 34. Since only the level of the transmission interfaces 21 is shown, it will be appreciated that several similar levels may be used in a PABX exchange, and the use of such multi-levels in a transmission network is well known and is described in the aforementioned U.S. Patent 4,201,891. Pulse code modulated (PCM) speech and data buses, illustrated, respectively, 106: 11a, 108: 11a, and 110: 11a, are bidirectional, with each bus containing a pair of unidirectional transmission paths, each of which is reserved for data flow in one direction. For example, each unidirectional path 106, 108, and 110 has 32 digital data channels, time period interleaved (TDM) in bit sequence format. Each TDM format body comprises 32 channels, each channel having, for example, 16-bit information at a bit rate of 4.096 Mbps. Respectively, the PCM speech and data buses 106 and 108 are connected to a digital interface circuit 22, where the speech and data are combined, as will be described later, for simultaneous transmission through the transmission network 24. The keyboard interfaces are connected to the digital interface via the transmission path 110. As previously mentioned, control processors 34 and 36 operate to provide a path through network 24.

Referring now to Figure 3, a three-port system is shown in which a user of a voice or data system on port-1 comprising a subscriber unit 200 and a data terminal 202 can selectively communicate with either port-2 or port-3. Port-2 includes a second voice and data system with a user subscriber unit 204 and a data terminal 206. Port-3 includes a database system including a data processor 208 and a database interface 210. Processor 208 may comprise a device, such as a stored program computer, that has data stored for retrieval by users on ports 1 and 2. Interface 210 operates to connect data streams directly to PCM channels and includes a digital interface, such as digital interface 22, in accordance with the present invention, which will be described later. In the same way, port-2 is connected to the transmission interface 212 and the digital interface

214 via the transmission network 24. Port-1 is connected to the transmission network 24 via the transmission interface 216 and the digital interface 218.

The three-port system of Figure 3 is a two-way system in which both subscribers 200 and 204 have a simultaneous voice connection with common interaction through their respective data terminals 202 and 206 to the database system 208, respectively. According to a feature of the present invention, both subscribers interact with the common database 208 so that they both receive similar data retrieved from the database 208, although each subscriber may transmit different data, or (b) they receive different data back from each subscriber from the database. Line 220 comprises a high speed parallel data bus. Digital interface 210 provides serial / parallel conversion, channel allocation, and synchronization for 2-PCM links 222 and 224, each having, for example, 32 channels.

The transmission of digital information from one port to multiple ports is known and is described in detail in U.S. Patent 4,293,946, issued to 35 m. Kuras et al., To the assignee of the present invention. Figure 3 shows the transmission of data and digital speech through the network 24 between ports 1 and 2 between the database on port 3. Although it is known to send speech or data to multiple ports in a speech field, i. M. In U.S. Patent No. 4,293,946 to Kuras et al., The problem remains concatenating the data in the number of bits (e.g., 5-bits) of data words used. Because it is necessary to be able to receive digitized speech from port 1 to port 2 and data from port 1 to port 3. This is accomplished by sending a single data word that includes both digitized speech and data to a combined information field for both destinations (port-2 and port-3). With the digital interface on Port-2, speech is only picked up and data is deleted (rejected). With the digital interface 210 of Port-3, only the data is picked up and the speech is deleted (rejected). Similarly, to transfer speech and data from port-2 to porttil and port-3, respectively, the same method is effectively used.

However, in the prior art, the problem arises from retrieving data from port-3 (database system) to both port-1 and port-2 and delivering it to the same terminals that transmit. A 16-bit PCM could transmit in the same way as described above, but it uses only 30% of the available bandwidth and one of the available voice channels on ports 1, 2. Thus, an additional transmission and combination device is absolutely required. It has been found that an already existing telephone exchange PABX can actually be used for this purpose. Alternatively, a separate transmission bus must also be provided separately for the purpose of this data, regardless of which voice transmission mechanism prevails in the PABX, even if such a voice transmission mechanism is similar. For example, the voice bus 230 may be a 32-channel PCM transmission link located between each of the telephone subscriber ports, such as ports and port-2, on each of the digital interfaces 218 and 214. The conventional use of the voice bus in a telephone subscriber network is to transmit audio signals, such as ringing, busy and queuing signals, etc., so that the telephone subscriber hears these sounds on the voice channel. Since each telephone subscriber can always be connected to the voice channel 230, i.e. each of the 32 channels on the voice bus can be connected to each telephone subscriber, both subscribers on port-lz and port-2 can be connected on data sent from either port-1 and port-2 that require different data from port-3, then the data can be simply transmits 32-channel TDM via voice bus 230 on different channels of the PCM data frame. The audio connection is shown at 232. For an understanding of the present invention, it is sufficient that voice generation and transmission be known in the prior art. A representation of a suitable audio bus is shown with reference to Figure 8. Since the database interface circuit 210 may be similar to the digital interfaces 214 and 218, it is understood that only data insertion and retrieval is required, as the digital interface 210 for the database system 208 may be included in any known data insertion and retrieval circuit.

Referring now to Figure 4, a simplified block diagram is shown of combining four separate system users A, B, 20 C and D, each with voice (telephone) and data (terminal) access to a database system 208. Large number of channels in PCM speech and data frames transmitted via the digital transmission network 24.

Speech and data from users A, B, C, and D are combined at digital terminals 250, 252, 254, and 256, respectively, into digital words corresponding to speech and data, and divided into two busses 258 and 260 by digital terminal 210. Bus 258 is a digitized speech bus and bus 260 is a data bus. The voice bus 258 connects users A, B, C, and D to the conference circuit 262 to provide a simultaneous voice connection for all users. The conference circuit may comprise, for example, the conference circuit described in the aforementioned U.S. Patent No. 4,293,946 to M. Kuras et al. The data bus 260 simultaneously connects all users to the database system 208 separately to send or receive data therefrom. The data obtained may be common data sent to some or all users or different data to each user. The database system 208 may be an Intel 8086 microprocessor or an IMB 370, depending on the amount of data required by the users. A database system may typically have computational capability in addition to accessing the database for processing and calculating data groupings or numbers.

Referring now to Figure 5, the data format used to provide simultaneous speech and data transmission in the digital interface block diagram shown in Figure 6 will be described. Format A is a 16-bit data format commonly used in telephony and represents the 32-channel PCM channel content of a data body. The bit IDs are:

P = Protocol - 2 bits

N = RESERVE - 1 bit

S = Speech - 8 bits

X = Data - 5 bits

It will be appreciated that the protocol bits P in the described system may be SPATA protocols, such as 10, as described in the aforementioned U.S. Patent 4,201,891 to A. Lawrence et al.

The transfer rate is typically 4.096 M bits / s.

Format B is an 8-bit digital speech sample for A's channel word. It is a digital representation of an analog speech sample. An 8-bit digital speech sample is either obtained or interposed in the channels in all frames. A speech sample is taken out or interposed when the interface to the voice transmission interface from the digital interface is 8-bit x 32 channels per frame. When the PCM speech bus 106 of Fig. 2 has 16 bit words, there is no need to intervene or remove speech samples. However, speech samples can of course be interposed or removed for matching at the telephone interface 100, as described, for example, in the aforementioned U.S. Patent 4,201,891. The speech transmission rate is 64 K bits / s, obtained at 8 K frames / s and 8 bits / channel per channel. frame.

Form C shows two 5-bit data words interleaved in a 16-bit BCM Form A data field (X-bits). Only the first 4 bits of a 5-bit data field are valid data. The extra bit is used to indicate which of the extracted or intervened odd or even parts C of D is represented. The extra bit, either high or low (1 or 0) is sometimes called a half-byte pointer, and each half-byte of 4-bit data from an 8-bit data word D has an opposite half-byte pointer to each other, i.e. half-byte pointers are never both 0 or 1.

Thus, the 5th bit in each half-byte C is used to form two 4-bit half-bytes of the 8-bit data word D. The data word D has a transmission rate of 32 K bit / s. For the combined fields, samples C are interposed for transmission over a digital transmission network. For separate fields, samples C are retrieved upon receipt from the digital transmission network.

Referring now to Figure 6, which shows a digital interface circuit 22. The voice and data PCM channel bodies in Form A of Figure 5 are transmitted and received from the transmission network 24 via Tx and Rx lines connected to the synchronization detector and buffer 300. The PCM input from the transmission network 24 is used to synchronize all other inputs to the digital interface 22. Thus, the insertion and deletion of data is performed in synchronization with the synchronization of the body and the channel received from the digital transmission network 24. Thus, a timing relationship is determined between the operation of the feed relay network 24, the operation of the digital interface 22, and the transmission via wires / trunks to users via the transmission interface 20 to lines 302 (voice bus), lines 304 (data bus), and lines 306 (keyboard applications). The eight-bit PCM in A or B data format from the user terminal voice bus 302 is buffered by PCM buffers 308 and coupled in 32-channel A or B format to the timing RAM 310 to schedule the transmission data frame rate connected from the buffer 300 on line 312 timing -RAM 310, timing RAM data / audio isolation circuit 314, and timing RAM 316.

Timing RAMs are memories in which information is written at the frame rate of received data from wires and obtained and read at the timing of the internal digital interface. Each timing RAM has an address counter (not shown) incremented on each channel time channel N, N + 1, N2 ... so that successive 8-bit bytes are written to consecutive locations in memory. The address counter counts down to thirty-two, then starts again at the same frequency but at a different phase. For addresses with a consecutive 8-bit data bit rate of 2,048 M bits / s, the counter counts at a count rate of 256 K bits / s. Logic is also provided (not shown) to initialize and synchronize the address counter to A or B format timing.

Eight-bit PCM speech is interposed in a 16-bit field to form a relay transmission format. This is accomplished by converting 8-bit to 16-bit with the 8/16-bit converter 320 shown in Figure 7. When channel associated signaling (CAS) or data needs to be mapped to a 16-bit channel, it is read from CAS / DATA RAM 322 and connected to the PCM word stream in addition to the speech field. When channel-related signaling is used, it is connected / disconnected from the speech field. The 16-bits are sent to the transmission network 24 in the form / channel of line 324, 8/16-bit converter 320, and lines 326/16-bit. CAS / DATA The CAS part of the RAM 322 has a memory card, 8-bit wide and 128 slots, each of which is 8-bit (per 1 channel). The data part of CAS / DATA RAM is 128-digit, each with 4 bits. The operation of the CAS part of RAM will be described later. The data is read from the data portion of the CAS / DATA RAM 322 half a word at a time (+ pointer bit) added as it is read, as defined by the address counter (not shown) associated with the RAM 322 and fed from the address development read / write controller 328. The address counter rotates the RAM For 322 through each channel. The memory map is retrieved and the data is read and pasted into memory. The memory map 328 receives and stores data grouping from the control logic 34, which, when read again locally in the 328, allows data to be read / written to the DATA RAM from channel-specific sources. The keyboard RAM 330 is designed to be similar in structure to the CAS / DATA RAM 322 and contains 2 ... 2N memory word slots (assuming separate transmit Tx and receive 5 Rx slots), depending on the number of data channels (N) it is desired to send to the keyboard. Keyboard synchronization and buffer 332 are provided with read / write control from RAM 328, such as timing circuits 314 and 316 and an 8/16-bit converter 320. Data to be transmitted / received from keyboard 10 is written or read from keyboard RAM via control logic 34 via local control logic 329 via a parallel control interface. . The control logic 34 can similarly read / write to CAS RAM 322 to transfer information.

Data in C or D format is connected from data bus 304

Through the PCM data buffer 318 to the timing RAM 316. The data is received on the data bus 304 in successive channels in which the data is included as 5-bit or 8-bit fields at an effective bit rate of 32 K bit / s / channel. When the data fields received on bus 304 are 8-bit long, they are converted to 5-bit fields containing a half-byte bit. When the data fields are 5 bits long, they already contain a half-byte bit. The data is timed to the forward frame rate 316 and written to CAS / DATA RAM 322 as 4-bit fields with a half-byte bit defining an odd or even address in RAM.

The transmission to the transmission network and the connection of the data, including the simultaneous transmission of the data written during the previous 31-channel run, have been described above.

The transmission from the transmission network 24 to the wires and the separation of the data 30 will now be described. The data is received from the transmission network 24 by a synchronization detector 300 in 16-bit format and the synchronization is separated. 8-bit speech is separated by an 8/16-bit converter 320 and written to timer RAM 310 or connected directly to PCM buffer 308. If channel-related signaling or data is mapped to a particular channel, the DATA / CAS field is separated by 320 and written to CAS / CAS. DATA to RAM 322. If data is mapped to voice bus 334 on voice port 336 for reception, the voice bus data field is separated by timing, clock, and data / voice separation circuit 338 and written to CAS / DATA RAM 322 under address generation and read / write control 328. Data is sent simultaneously, i.e. during the next 31 channel times, the simultaneously transmitted data is read from the CAS / DATA RAM 322 as a 4-bit field and either combined into an 8-bit field or left 5-bit (4-bits + odd / equal address half-byte detector bit), bit to the output stream 316 and sent to line 308 (and other lines with other digital interfaces 22 identical in shape to Figure 6). As already described in detail, the timing of the PCM information of the transmission network 24 may be out of phase with all other data - which is characteristic of the transmission network 24, as described in A. Lawrence et al., U.S. Patent No. 4,201,891, cited above. , separation and PCM timing for all PCM digitalized speech and data and sounds from the trunks and lines are synchronized with the PCM information obtained from the transmission network 24.

The control logic 329, which includes repeater level inputs and address loop inputs for wire / remote line selection and connection to the microcomputer, control 34 of Figure 1, such as the Intel 8086, is a conventional circuit and provides standard means for microcomputer connection. Thus, the control logic 329 provides a path for control words from the microcomputer to set and clear words in the mapping RAM 328 to control the data stream that actually allows the microcomputer to read / write to CAS / DATA RAM 322 and keyboard RAM 330. As a standard interface between the microcomputer and the remaining 22 329 includes conventional register buffers, decoders, address development and identification registers, and initialization control.

Referring now to Figure 7, an 8/16 bit converter 320 coupled to CAS / DATA RAM 322 is shown in a simple manner. The circuit provides 8/16 bit conversion, concatenation, and decompression of data / CAS. Circuit 320 consists of 16-bit and 8-bit shift registers of serial-to-parallel conversion

400, 402, 404 and 406, which provide serial data as parallel data and parallel data as serial data, as shown. The counters cycle through each channel 0-31 to ensure that the data is synchronized through the registers to the correct channel. The protocol and NACK bits are unchanged.

Figure 8 shows the voice bus network and its distribution through a buffer hierarchy for a large number of digital interfaces. Audio bus 230 is a phase asynchronous 32-channel 16-bit PCM digital stream, such as in transmission network 24. The audio bus is divided through a hierarchy of buffers 500 into a large number of digital interfaces shown 22, 22A ... 22N connected to transmission network 24 or other required destinations. Digital connections 22A and 22N illustrate a number of digital connections with which the audio busses are divided via buffers 1, 2A ... 2N, i. voice busses 20,230, two of which are represented by 2AL and 2NM.

The audio circuit 502 comprises a digital audio generator 504 that provides digital PCM sequences per 8KHz 8-bit sample for various sounds used by the control panel (or PABX). These tones may be programmable in frequency, amplitude, harmonic content, and other parameters by a controller 34 that switches commands to the tone generator 504 on the control bus 506.

The external interface 508 converts or receives external sources, such as music, continuous announcements, etc., and encodes these into 8-KHz, 8-bit PCM streams. The time slot investor 510 receives the 32-channel 16-bit PCMs from the digital interface 22 under the control of the controller 34 and connects the 8-KHz, 8-bit PCM samples from the digital audio generator 504 and the external interface 508 to the channels located in the PCM frame in the speech field. The digital interface 22 receives 5-bit data fields, as described in the PCM data from the transmission network 24, and passes this data to a time slot locator 510 to multiplex with other 8-bit, 8 KHz inputs to form 16-bit PCM words on the voice bus 230.

Referring now to Figure 9, data relating to channel associated signaling (CAS) when talking between CAS / DATA RAM 322 and serial-to-parallel conversion circuit 320 is shown. The parallel input-serial output register 323a and the serial input-parallel output register 323b correspond to the registers 400 and 404 of Fig. 7, respectively.

CAS is data that is connected to successive frames of a PCM stream in a single channel, a voice channel, forming a repetition period known in telephone technology as a multi-frame. When a suitable channel is transmitted or received to digital interface 22, CAS RAM 322 is taken from or exported to the speech field. Controller 34 can then write or read CAS RAM 322 to send or receive control or signal information. The CAS capability is provided for both the proxy network 24 and the terminal. Using the same channel as a CAS channel is used to signal to the network or further to the terminal.

Counter 600, for example 5-bits, is incremented into each frame by a frame clock to create a 32-frame multi-frame data sequence, providing 8 x 32 = 256 bits of signaling for reception and transmission in each direction on lines 602, 604, 606 and 608. Parallel speech transmission is possible. when not received or transmitted on the CAS channel. Channel mapping, if required, is described elsewhere.

CAS RAM 322 comprises four blocks, e.g., 8-bit 32-slot. The four blocks of CAS RAM 322 are:

An IA acting as a buffer for data from the controller 34 to the network 24;

IB, which acts as a buffer for data from the network 24 to the controller 34;

2A, which acts as a buffer for data from the subscriber terminal to the line

606 via controller 34; and 2B, which acts as a buffer for data from the controller 34 to the subscriber terminal via line 608. Referring now to Figure 10, attaching half-byte data¹⁸ 79640 and the separation between CAS / DATA RAM 322 and serial-to-parallel converter 323 is described.

Initially, 8-bit data is held in two 64 X 4-bit RAMs 700 and 702, where adjacent slot pairs of RAMs contain both half-bytes of the 8-bit byte and so that the last character bit (LSB) of the address separating adjacent locations operates high / low. -puolitavu pointer.

The 322 data RAM parts of the CAS / DATA RAM can be considered as two equal parts. DATA RAM 1, shown as 700, is used as a buffer and channel mapping from the terminal to the network.

DATA RAM 2, shown as 702, is used as a buffer and for channel mapping between data sources and a terminal or terminals.

The DATA RAM: 11a 700 is an address for reading the data input channel mapped to the PCM channel that will be sent to the network. The contents of the DATA RAM 700 at this address are stored in the transfer register 323a prior to transferring the PCM channel to the network 24.

DATA RAM: 11a 700 is the address for writing, the data channel number received from the terminal. Thus, on the network PCM channel to be transmitted, the data is obtained from the mapped location in RAMx 700 by the data channel address obtained from the mapping RAM 800, which will be described with reference to Fig. 11.

The DATA RAM: 11a 702 is the number of the data channel to be sent to the subscriber terminal for reading as its address. To write the address of the DATA RAM 702, the data input channel number is obtained from the mapping RAM 800 by location search in the mapping RAM 800, which is indicated by the channel number of the PCM received from the network 24. Thus, data is mapped to network channel on line 602 from data channel on line 704 and from network channel on line 604 to data channel on line 706.

There are also two other data sources written to the DATA RAM 702 selected from the contents of the mapping RAM 800. These other data sources are either audio data or free grouping, which is used when neither the network nor the audio data is connected to the data terminal.

The high / low half-byte pointer is used to write and read the address as an LSB to RAM 700 and 702.

Referring now to Figure 11, a CAS / DATA RAM controller 328 is described. The mapping RAM 800 comprises 32 slots in 12 bits and is obtained twice during channel time, once when transmitted to channel network 24 and once when received from channel network 24. Each direction has its own address counter 804 and 806 , which are cleared at each suitable frame rate connected to counters 804 and 806 by lines 808 and 810, respectively. As a result of each read acquisition, the read data in the mapping RAM 800 is stored in buffer registers 812 and 814, which are for each of the PCM stream input and output directions.

The mapping RAM 11a 800 also has read and write access from the controller 34 via the control logic 329, which writes the mapping groupings to the RAM 800 and can read them for verification. RAM 800 is larger than 8-bits, and can thus become addressable in two ways, with a 12-bit range (32 locations) for channel mapping and a smaller range of control data, i. With an 8-bit range (64 slots, 32 half-used) for controller 34 access.

The 12-bit data rate of the RAM 800 is preferably denoted as follows:

one bit - select free grouping to RAM 702 one bit - select CAS channel

5-bit - mapped data channel

5-bit - mapped audio channel

If the voice bus 302 is to have channel mapping to the relay network PCM digital interface 22, this can be accomplished by the same technique as described with reference to Figures 9, 10 and 11 and extending the scope of the mapping RAM 800 to include the voice channel channel number field.

When the PCM channel of the network is to be transmitted to the relay network on the line 602, the number of this channel traced by the counter 804 is assigned to read the mapping RAM 800, the read data of the volumes from the RAM 800 to the output control register 812.

The control word in register 812 contains a CAS enabling bit. If set, the speech field in shift register 323a is loaded from CAS RAM IA (322) obtained from the multi-frame address obtained by multi-frame counter 600. CAS is also loaded into CAS RAM 2A (322) from the terminal's 8-bit speech field on the line 606 with multi-frame read address. The data field in the DATA RAM 700 is loaded into the shift register 323a from the address determined by the data channel number of the mapping RAM 800 previously loaded into the output controller register 812.

When the network PCM channel is received on line 604 to shift register 323b, the number of this channel traced by counter 806 is used as an address to read mapping RAM 800, to load the assigned content into input controller register 814. If the CAS enable bit is set, CAS is loaded into CAS RAM IB (322) from the received speech field in the shift register 323b and the CAS are also sent to the terminal from the CAS RAM 2B (322) in the speech field on line 608. The CAS RAM addresses are determined by a multi-frame counter 600. DATA RAM 702 is loaded in the PCM of the network received from the 5-bit field in the shift register 323b if the audio data channel mapping address in the input controller register 814 is zero and the selection-free grouping bits in the register 814 are not set.

If the field of the voice data channel in the input controller register 804 is not zero, then the voice data is read from the location indicated in this field in the RAM located in the timing and synchronization, data and voice separation circuit 314 referred to in Figure 6, and DATA is loaded To RAM 702 at the location indicated by the data channel field previously loaded into the input controller register 814. If the select-free grouping bit is set, the free grouping is placed in the mapped location in the DATA RAMx 702. This overrides the scrambling of the content of the voice data channel field in register 814.

The read / write control and address mapping 328 also includes periods that control different read and write accesses at specific time slots synchronized to the network PCM trunking, channel timing, and 4.096 MHz timings.

Since the present invention has been described in connection with its preferred embodiment, it is to be understood that additional embodiments, variations, and applications that will be apparent to those skilled in the art are included in the spirit and scope of the invention as set forth in the appended claims. For example, many forms of data transmission can be implemented in accordance with the present invention using known transmission interfaces. These include single connection to single connection, data only, or data and speech simultaneously. For data only, data could be transmitted in 64 K bits bidirectionally in the speech field or data could be transmitted in speech bandwidths using transducers and transmitted in the speech field. Simultaneously for data and speech, data could be transmitted in 32 K bits and speech in 64 K bits bidirectionally using 5 spare bits in SPATA format; or if 32 K bit speech is encoded and accepted, then the 5 and 8 bit fields can be reserved so that 64 K bit data can be transmitted in two directions. Multi-terminal (greater than or equal to 2) with or without a common database access, the data can be transmitted in conference format with the following variations: the conference circuit separates the data and forms a common database stage forwarding, routing forwarding or access manipulation so that common data is returned to all terminals or message forwarding is established between terminals. Bidirectional paths are formed between each terminal and the conference circuit. For multi-terminals formed in a non-conference format (with or without a common database access), data may be transmitted between two terminals having a direct voice connection and a data connection via a common database so that each terminal receives the same retrieved data from the database or alternatively that each terminal transmits (using the 79640 transmission capability) a 16-bit channel combined with speech and data to both the other terminals and the common database, and the common data is returned via an audio channel that allows transmission on the 30-channel on all terminals.

Two terminals with a direct voice connection and a data connection via distribution can be connected to one, one or more data bases so that each terminal receives a different recovered data.