Method for processing transmitted and reflected signals for removing unwanted signals and noise form wanted signals.

Method for processing transmitted and reflected signals to remove unwanted signals and noise from desired signals

The invention relates to a method for processing signals in an identification system, which is described in the preamble of claim 1.

The invention is designed for use in an identification system consisting of a transmitter, a mobile bit-coded passive radar transponder that provides identification, and a receiver unit that together form a processing system.

The radar transponder can be implemented using SAW (surface acoustic wave) technology. In terms of application, this technique has many advantages, namely, it is inexpensive, simple to produce, maintenance-free, and independent of external power sources, etc. However, a radar transponder made according to this technique has a feature that is a drawback, namely high insertion loss. This means that the reflected return signal is weak relative to the incoming interrogation pulse. The drawback is accentuated when a low-radar radar is used in the transmitter unit at the frequency used to meet the beam output power requirements.

The overall result is that the power of the required return signal to the receiver unit of the system is very low compared to the unwanted signals, the noise and the inherent noise of the receiver itself.

Other known solutions

The traditional method of processing signals to improve the signal-to-noise ratio in said applications is to digitize the reflected signal directly with an A / D converter and then perform digital processing. The processing is performed by calculating the averages of the digital values ​​of the analog signals over several repetitive return signal cycles. This improves the signal-to-noise ratio because the required signal is identical in each cycle, while the noise is different. On the other hand, this method requires an efficient digital processing unit. The unit must be fast and have considerable computing power to average a sufficient number of cycles. At the same time, the A / D converter must be the fastest and most advanced type available. As a result of this solution, processing efficiency is clearly limited by the technology used, and it also requires expensive digital processors and A / D converters.

Another traditional method used in radar technology is to use delay lines to delay the signal by one cycle and to obtain an average by adding these signals analogously. The limitation of the method is that the number of averages to be generated is very limited and there is no synchronization with the cycle.

U.S. Patent No. 3,706,094 describes a receiver for a low output radar tracking system, wherein the receiver consists of equipment for analog processing of received repetitive pulse signals, each pulse signal being divided into a number of time slots in the gate control circuits. In addition, the signal from each gate circuit is fed to the integrator for repeated integration of the pulse signals, the repetition frequency of the pulse signals being significantly higher than the low-pass filtering frequency of the integrator. The pulse signal can be reconstructed from the transponder by reading the output of the integrator.

The main object of the present invention is to provide reliable means for identifying a radar signal reflected from a passive, coded radar transponder by phase modulation of the transmitted signal.

This can be done using the method mentioned in claim 1. Other aspects of the invention are set out in the other claims.

The present invention differs from the method disclosed in said patent publication in that the invention utilizes the interaction of transmitted and reflected signals. This is done with a random binary number sequence that modulates the transmitted signal, and using the same bit sequence when the demodulated reflected signal needs to be identified. This generates a large number of phase modulated pulse trains, which are preferably different. This is accomplished by dividing the above random bit sequence and using these bit sequence dividers to route the demodulated reflected signal to a storage medium such as an integrator arranged so that the medium contains the averages of the desired signals, while the unwanted signals and noise are clearly reduced.

Advantages of the application of the invention

The technique used in the invention consists of analog averaging the signal before digitizing it.

The method has several advantages over traditional methods. Significant processing capacity can be achieved by using only completely standard, commercially available inexpensive components. The result is speed and the ability to average repetitive cycles, which are much of the traditional ways mentioned above. At the same time, a lower read speed means that standard type A / D converters and later a digital processing unit can be used, making this commercially viable.

Because the bit sequence is used both in the transmission to modulate the signal to be transmitted and in the receiver to control recording and averaging the demodulated, reflected signal, all noise types and unwanted signals are significantly reduced compared to the desired signal. Because the aforementioned bit sequence is part of a random bit sequence, noise and unwanted signals are reduced even though they are part of an unfavorable repetitive cycle.

It is also possible to achieve better transmission by using phase modulated and preferably different pulse trains instead of a single pulse, whereby the increased pulse train length is further limited by the time of the first reflected pulse train.

Embodiment of the invention

An example of an embodiment of the invention is given below with reference to the figures.

Figure 1 is a block diagram of some means for carrying out the invention, including the main components,

Figure 2 shows in more detail the transmitter unit of this particular embodiment,

Figure 3 shows in more detail the receiver and decoder unit of this particular embodiment, and

Figure 4 shows, in chronological order, the transmitted and reflected signals of an embodiment of the present invention.

The embodiment of Figure 1 comprises a transmitter unit 11, an identification chip 12, which could be, for example, a passive SAW radar transponder, and a receiver unit 13 connected to a set of integrator parts 16. The device 14 generates a random bit set fed to a transmitter unit 11 and a shift register 17 The device 15 generates a time-limited signal which is fed to the transmitter unit 11 and the shift register 17.

The implementation works as follows:

The transmitter unit 11 transmits a phase modulated pulse train, which is received and reflected back by the coded radar transponder 12, wherein the reflected signal consists of a series of pulse trains and intervals without pulse trains which together form an identity consistent with the radar transponder code, which also consists of phase modulated. The receiver 13 receives the desired signal and demodulates it and sends it to an integrator set 16 controlled by the aforementioned bit set from the device 14 together with the time slot from the device 15.

Figure 2 shows the transmitter unit in more detail. This consists of an oscillator 21 which generates a fixed frequency signal. This signal is phase modulated by a series of random bits from device 14. Once the signal is modulated, it is divided into pulse trains by means of a gate device 23, which is controlled by time slots from the device 15. The pulse trains are amplified by amplifier 24 before being transmitted.

Figure 3 shows the receiver and decoder unit in more detail. The signal is demodulated at the receiver 13 into a time- and phase-encoded signal 31a which overlaps with the unwanted noise. In this example of the invention, signal 31a arrives at the switch

36a leading to the integrator portion 37 of the signal 31a. This integrator portion 37 may be, for example, an RC filter having a large time constant (e.g., 10,000 times greater) compared to the cycles of the individual signals.

The bit sequence from the device 14 and the slot signal from the device 15 form the input of the AND gate 32a, whereby the output goes to the shift register 33a, which then receives exactly the same bit sequence as the bit sequence used to generate the phase modulated pulse train at the transmitter. This set of bits is synchronized in the shift register 33a by an external clock signal (not shown). It is possible to receive a signal from different positions in the shift register, i.e. after certain time intervals after the signal is input to the shift register 33a. When the time interval equal to the time delay of the first bit in the radar transponder 12 has elapsed, the signal is removed from the shift register and used to control the switch 36a which opens or closes for the demodulated signal 31a coming from the receiver 13 and going to the integrator section 37.

The signal 31a can be inverted by inverter 34 to signal 31b, which is also fed to integrator 37. This is done by feeding a random bit sequence 14 through inverter 35 to second shift register 33b and removing it from position 1 corresponding to first shift register 33a and controlling switch 36b to open or close integrator 37 for the incoming inverse signal 31b. Both switches 36a and 36b can be controlled, e.g., so that logic 1 in bit set 14 opens the switch for the untranslated signal 31a from the receiver and closes the switch for the inverse signal 31b; if bit set 14 has a logical 0, the opposite happens.

During the period in which no pulse train is generated at the transmitter 13 due to the logic value 0 being 0, the AND gates 32a and 32b always have a logic 0 at their output, ensuring that both switches 36a and 36b are open and prevent unwanted noise from entering the integrator section.

The integrator set 16 is formed from a plurality of integrator portions 37, which typically correspond to the number of bits of the reflector device 12 or a multiple thereof. The individual integrator sections 37 can be read at any time after the desired set of pulses has been processed. This reading can be performed asynchronously, without having to take into account what has happened in the past.

Figure 4 shows chronologically how two pulse strings are transmitted from transmitter 11 and how they are reflected from radar transponder 12. In the example, radar transponder 12 has a four bit resolution and is encoded in this case by bit sequence 1101.

The first pulse train 41a is a phase modulated signal modulated by a first portion of a random bit sequence from device 14, the length of which is determined by the time interval generated by device 15. The radar transponder 12 receives the first pulse train 41a and is reflected when coded to a logic value of 1. Since the radar transponder in this case has a code 1101, the reflected signal forms the pattern shown in step 41b, where bit 1, bit 2, and bit 4 reflect the pulse train, while bit 3, which has a logical value of 0, does not reflect the signal. The reflected pulse strings 41b can overlap and overlap at different bit positions without this having negative consequences for the result.

When the last reflected pulse train is received, a second pulse train is transmitted. This is phase modulated by a second part of a random bit sequence, which is different from the first pulse train, and which comes from device 14, which is activated for a certain period of time determined by device 15. This second pulse train 42a is then reflected from the radar transponder 12 as in the first case, forming a row of reflected pulse trains 42b.

A large number of pulse trains corresponding to pulse trains 41a and 42a, which are phase modulated differently, can be transmitted, reflected, and routed to integrator set 16 so that the desired signal is averaged and unwanted signals that are random and asynchronous are greatly reduced.