Phase to digital converter in all digital phase locked loop

ES 2 809 488 T3

DESCRIPTION

Fully digital phase lock loop phase-to-digital converter

BACKGROUND

Field of the invention

[0001] The invention relates to the field of electronic circuits. More particularly, the invention relates to the field of oscillators and phase locked loops (PLL).

Description of Related Art

[0002] Phase and frequency controlled oscillators are used in a variety of electronic applications to provide stable and controlled frequency references. A digital device can use a frequency controlled oscillator as a clock source for timing, for example, as a clock for a digital microprocessor circuit. An analog device can include a phase locked oscillator such as a local oscillator used to convert radio frequency (RF) signals to frequency. The phase and frequency controlled oscillator can be a fixed frequency oscillator or it can be a tunable oscillator that is implemented using a programmable frequency synthesizer.

[0003] A frequency controlled oscillator for a digital device can be implemented digitally, while a phase locked oscillator for an analog device can be implemented using exclusively analog building blocks. However, as operating speeds of digital circuits increase, it is increasingly feasible to implement at least parts of a phase-locked oscillator for traditionally analog applications using digital building blocks.

[0004] Some of the improvements in the operating speeds of the digital circuits may be attributable to the improvements in the processes of uses for the manufacture of the digital circuits. Process improvements that reduce the size of the underlying transistors used in digital integrated circuit designs are related to improvements in operating speeds. CMOS circuits can be implemented using sub-micron processes, such as 90nm, 65nm, 45nm, or 35nm processes.

[0005] The supply voltage used in CMOS circuits has continuously decreased due in part to decreases in dimensions and also due in part to desires to reduce the total power consumed by such devices. In advanced CMOS processes, such as 65nm, the power supply voltage generally drops to around 1.1V. At this low voltage, conventional analog building blocks, such as function amplifiers and current mirrors, do not perform well and are difficult to design. Therefore, a conventional analog PLL is difficult and difficult to design. Therefore, a conventional analog PLL is difficult to design with such a process. Also, an analog PLL typically needs a large area to implement a filter function, whereas at 65nm, the silicon unit area is more expensive than the die area for larger processes.

[0006] Advances in digital processes result in greater limitations on the ability to implement traditional analog circuits, such as a PLL. Additionally, advanced digital processes make traditional analog implementations more expensive. It is desirable to capitalize on process improvements in the digital domain while minimizing negative effects on traditionally implemented circuits using analog building blocks.

[0007] Attention is drawn to document WO 2008/005853 (A2), which describes a digital audio system that includes a digital phase lock loop circuit (26) for the generation of a clock signal with modulation of pulse width, PWM, applied to a pulse code modulation to pulse width modulation converter. The digital phase lock loop includes a phase detector to measure the phase error between a reference signal and a feedback signal. A digital version of the phase error, after filtering through a loop filter, is converted into a digital delay control word that is sampled at twice its frequency. Successive samples of the delay control word control the propagation delay of the first and second delay cells in an oscillator.

[0008] Attention is also drawn to an article by VOLODYMYR KRATYUK ET AL, A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, IEEE SERVICE CENTER, NEW YORK, NY, United States, (20070301), vol. 54, n.⁸ 3, ISSN 1057-7130.

[0009] Furthermore, attention is directed to US 2003/076913 (A1). Describes a digital phase locked loop compiler including a pre-divider, a digital phase converter, a digital to analog voltage converter, a voltage control oscillator, a high frequency oscillator, a back divider, a divider output and a

ES 2 809 488 T3 built-in self-test. The digital phase lock loop compiler operates in digital mode and uses a preset phase adjustment value to reduce the phase lock time. Also, the absence of a low-pass filter in the digital phase-locked loop compiler and the small size of the built-in self-checker greatly reduces the overall area of ​​the digital phase-locked loop compiler.

Furthermore, attention is directed to US 2007/075785 (A1). A phase locked loop (PLL) is described here that includes a phase frequency detector along with a time-to-digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the difference of phase between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.

[0011] Finally attention is drawn to document US 2006/103566 (A1) which describes a new time-to-digital converter (TDC) used as a replacement for the charge pump and the phase / frequency detector in a fully PLL. digital inside a digital radio processor. The TDC core is based on a pseudo-differential digital architecture which makes it insensitive to NMOS and PMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the best logic level regenerative time in CMOS. The TDC is self-calibrating with an estimation precision greater than 1%. The TDC circuit can also serve as a CMOS process resistance estimator for analog circuits in large SoC dies. The circuit also employs power management circuitry to reduce power consumption.

BRIEF EXPLANATION

[0012] In accordance with the present invention, a method and a phase-to-digital converter are provided, as set forth in the independent claims. The embodiments of the invention are claimed in the dependent claims.

[0013] Embodiments not within the scope of the claims should be construed as useful examples to understand the invention.

[0014] Described herein is a phase-to-digital converter, an all-digital phase-lock loop, and an apparatus having an all-digital phase-lock loop. The phase-to-digital converter includes a phase-to-frequency converter that drives a time-to-digital converter. The time for the digital converter determines a magnitude and a sign of the phase differences emitted by the phase-to-frequency converter. The time-to-digital converter uses tapped delay lines and loop feedback counters to allow measurement of small timing differences typical of a loop tracking process and large timing differences typical of a loop acquisition process. Tapped delay lines allow the measurement of fractions of a reference period and allow lower power operation of the phase-to-digital converter by reducing the speed requirements of the reference clock.

[0015] A PDC can take reference clock (FREF) and N-fractional divider output (NDIV) as inputs and can provide a digital representation of its phase difference as output. The PDDC updates the output of each FREF edge (where by FREF edge refers to the rising edge, unless specified) and the output that follows a FREF edge corresponds to a pair of UP-DOWN signals generated by a phase detector. at the frequency in which the anterior FREF edge was involved. If an UP-DOWN pair extends more than one FREF cycle (which will happen if FREF comes first, that is, the pair starts and the NDIV edge does not arrive before the next FREF edge), then the phase difference is divided in subdivisions in FREF edges such that no UP-DOWN pair is longer than TREF (1 / FREF) and each subdivision is considered a separate UP-DOWN pair.

[0016] The PDC can provide the output as a counter and the digital output as a tapped delay line. When the counter output (binary code C <0: 4>) is not zero, the delay line output (thermometer code D <0:47>) can be ignored as this is a case of large phase difference ( > ~ 1.5 ns), which is typical of a phase locked loop acquisition period, and where reduced accuracy is acceptable.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The features, objects, and advantages of the embodiments of the present disclosure will become more apparent from the detailed description set forth below when considered in conjunction with the drawings, in which the elements themselves are identified by the same reference numbers.

Figure 1 is a simplified functional block diagram of an embodiment of a wireless communication device having all fully digital phase lock loops.

Figure 2 is a simplified functional block diagram of an all-digital phase-locked loop.

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Figures 3A-3B are simplified functional block diagrams of one embodiment of a phase-to-frequency detector and sign generator embodiments.

Figure 4A is a simplified functional block diagram of one embodiment of a time-to-digital converter.

Figure 4B is a simplified functional block diagram of an embodiment of a phase-to-digital converter.

Figure 5 is a simplified functional block diagram of an embodiment of a pulse generator.

Figure 6 is a simplified functional block diagram of an embodiment of a tapped delay line.

Figure 7 is a simplified functional block diagram of an embodiment of an edge aligner.

Figure 8 is a simplified functional block diagram of one embodiment of a counter.

Figure 9 is a simplified functional block diagram of an alternative embodiment of a meter.

Figure 10 is a simplified schematic of one embodiment of a counter clear generator.

Figure 11 is a simplified schematic diagram of an embodiment of a control signal generator Sel.

Figure 12 is a simplified diagram of an embodiment of a start / stop generator.

Figures 13A and 13B illustrate generator embodiments for Sel_1 and Sel_2 signals.

Figures 14A and 14B illustrate embodiments of generators for feedback control signals.

Figure 15 is a simplified diagram of an embodiment of a discharge control generator.

Figure 16 is a simplified flow diagram of one embodiment of a phase-to-digital conversion procedure.

Figure 17 is a simplified flow chart of one embodiment of a time-to-digital conversion procedure.

DETAILED DESCRIPTION OF THE MODES OF EMBODIMENT OF THE INVENTION

[0018] Described herein is an all-digital phase-locked loop (ADPLL) that implements all PLL functions in digital circuits with reduced silicon area and no off-chip components. The digital PLL can operate with low supply voltage. A phase-to-digital converter (PDC) design described herein forms an important operating block that enables the all-digital PLL.

[0019] The proposed PDC converts analog phase information into a digital word which can in turn be fed to a digital signal processor. The PDC works to convert the input phase information with fine resolution and high linearity, especially around the zero phase transition point. Due to device mismatches, a PDC can convert the positive phase and negative phase inputs with different gains or offsets. The different gains or tradeoffs are equivalent to non-linearity in a PDC conversion transfer function. This non-linearity degrades the overall performance of the PLL and works to increase phase noise and spurious response. The proposed ADPLL with PDC solves non-linearities with a symmetric topology. The PDC described herein also covers a wide range of phase input during PLL acquisition and lock modes. The proposed ADPLL and, in particular, the PDC described herein supports wide phase input ranges that typically occur during acquisition by implementing an edge recycle counter that contributes a small power consumption overhead.

[0020] The PDC can convert both the sign and magnitude of a phase signal into a digital word for digital signal processing and can be used in an all-digital PLL in deep sub-micron processing and low power supply voltage. The proposed PDC can convert both large phase inputs (wide pulses)

ES 2 809 488 T3 of the order of tens of nanoseconds as small phase inputs (narrow pulse) in tens of picoseconds. Support for wide and narrow phases is needed to support different PLL operating conditions, namely acquisition and locked modes. Large phase inputs are processed by an edge recycling counter with no power consumption overhead.

[0021] The PDC processes large and small input phase signals by applying a fine delay line to process the small phase inputs and an edge recycle counter to process the large phase inputs. The PDC achieves high linearity even when processing positive and negative phase inputs by having a symmetric topology for the UP and DOWN signals that are generated based on an oscillator signal and a reference clock. Delay mismatches in symmetrical parts will typically introduce compensation but not non-linearity. The delay in a DFF (D flip-flop) is measured and subtracted from the results. In addition, other techniques, such as pulse generation and discharge control, are used in the PDC to achieve the general functions used in the steady state operation of an ADPLL.

[0022] The ability to determine both coarse and fine phase-to-digital conversion, as well as to operate linearly, allows the ADPLL and PDC to be implemented in traditionally analog configurations, such as RF applications that typically require higher performance than is typically required. in an oscillator for a digital microprocessor application.

[0023] Figure 1 is a simplified functional block diagram of an embodiment of a wireless communication device 100 having fully digital phase lock loops. Wireless communication device 100 is implemented as a transceiver having different transmission and reception processing paths. Each of the transmit and receive processing paths can implement and use an ADPLL as part of a local oscillator circuit. The different transmit and receive oscillators allow for full duplex operation, in which the wireless communication device 100 transmits and receives signals simultaneously.

[0024] Wireless communication device 100 includes an antenna 102 that can be shared by both transmission and reception processing paths. The antenna 102 couples the received wireless signal to a duplexer 110 that can be configured to couple the reception signals from the antenna 102 to the remainder of the reception operating path while isolating the reception path from the transmission signals. The receive output of the duplexer 110 is coupled to a front-end amplifier 120, which may be, for example, a low noise amplifier (LNA). The front end amplifier 120 typically operates to substantially regulate the overall noise figure of the receiver and is therefore typically implemented as an LNA having a gain of 10-20 dB. The output of the front amplifier 120 is coupled to an RF receiver filter 122.

[0025] RF receive filter 122 functions to perform RF selection by removing or attenuating signals outside of a desired receiving RF operating band. RF filter 122 can, for example, contribute to adjacent channel rejection. The output of the RF receive filter 122 can be coupled to an RF input of a frequency converter, here represented as a mixer 130. The second input to mixer 130 is driven by a local oscillator signal that can be generated by a first ADPLL 154 that is implemented substantially or wholly within a transceiver chip 180 that is manufactured using an advanced CMOS process, such as a process of 65 nm.

[0026] The output of the mixer 130 may be a baseband signal that is coupled to an analog-to-digital converter 132 that operates to generate a digital representation of the baseband signal. The baseband digital signal is coupled to a receive input of the transceiver chip 180. The receive input of the transceiver IC 180 couples the digital baseband signal to a receive baseband processor 140 for further processing.

The transceiver chip 180 includes a first ADPLL 154 that operates in conjunction with a first frequency reference 152 to generate a first oscillator signal. The first oscillator signal can be used as a local oscillator for receive frequency shift operation. The first oscillator signal output from the first ADPLL 154 can be coupled to the LO input of the mixer 130 to frequently convert the receive signal to baseband.

[0028] The embodiment of the receiver illustrated in Figure 1 implements a direct conversion technique in which the RF reception signal is converted to baseband in a single frequency conversion step. Of course, the receiver in the wireless communication device 100 is not limited to any particular configuration and may use direct conversion, superheterodyne, or some other configuration.

[0029] Wireless communication device 100 may include a complementary transmitter. The transmitter may include a signal generating portion in the integrated circuit 180 of the transceiver that substantially generates the transmit signal. A transmitting baseband processor 160 can be configured to interact with a data source (not shown) and can format the data for later transmission.

ES 2 809 488 T3

The transmit baseband processor 160 can be configured, for example, to provide the baseband transmit signal to a modulator 170. The modulator 170 can be configured to directly modulate the baseband signal into a second signal oscillator. Modulator 170 can be, for example, a two-point modulator.

[0031] A second ADPLL 158 in conjunction with a second frequency reference 156 can generate the second oscillator signal, which can be, for example, at the desired transmit RF. Although the second frequency reference 156 is represented as distinct from the first frequency reference 152, both the first ADPLL 154 and the second ADPLL 158 may share the same frequency reference, for example, the first frequency reference 152. The second ADPLL 158 can be configured to accept the modulation signal from modulator 170 and can directly modulate the transmit signal onto the second oscillator signal.

The output of the second ADPLL 158 can be coupled to a transmit RF filter 192 that can function to substantially remove unwanted products, including spurious products and harmonics, that can be sent by the second ADPLL 158. The filter output RF transmission amplifier 192 is coupled to a transmission amplifier 194 which may alternatively be referred to as a high power amplifier (HPA). The transmit amplifier 194 can have a variable gain or variable gain stage and can be configured to amplify the second modulated oscillator signal to a desired transmit power level. The output of the transmit amplifier 194 is coupled to a transmit input of the duplexer 110 where it is coupled to the antenna 102.

The transceiver integrated circuit 180 can be implemented in an advanced sub-micron CMOS process operating at a low supply voltage, such as 1.1V, and can implement fully integrated first and second ADPLL 154 and 158 on the integrated circuit without the need for any off-chip elements such as passive off-chip devices, off-chip analog devices, or off-chip oscillators. The ability to use relatively frequency reference clocks that have a period that is much greater than a phase resolution of the phase-to-digital converter allows the ADPLL 154 and 158 to operate at relatively low current draw levels, which translates to at relatively low power consumption.

[0034] Figure 2 is a simplified functional block diagram of an all-digital phase lock loop 200. The ADPLL 200 of Figure 2 may be, for example, the second ADPLL of the wireless communication device of Figure 1, and it may be the first ADPLL of the wireless communication device of Figure 1 if the modulation part is omitted or not used otherwise.

The ADPLL 200 includes a variable oscillator, which may be a digital controlled oscillator (DCO) 210 whose output is the phase and frequency controlled output from the ADPLL 200. The output of the DCO 210 is also coupled to a divider 220, which can be, for example, an integer divisor or a fractional divisor. The divider 220 can be programmed or otherwise controlled to provide a division ratio that tunes the output frequency of the DCO 210 to the desired frequency. The control signal for splitter 220 can be determined, for example, in a baseband controller or some other processor (not shown).

[0036] The divided output is coupled to an input of a phase-to-digital converter (PDC) 230. A reference oscillator (not shown), which may be, for example, a crystal oscillator, is coupled to an input of PDC 230 reference.

The PDC 230 includes a phase-to-frequency detector 232 coupled to a time-to-digital converter (TDC) 234. The PDC 230 is described in much greater detail with respect to other figures. In general, the PDC 230 compares the phase of the reference oscillator with the phase of the divided output and provides a digital value indicative of the phase difference. The output of the PDC 230 can be expressed, for example, as a sign and magnitude, as a two's complement value, or as some other digital format. The digital value output of the PDC 230 is coupled to a loop filter 240 that can be implemented as a digital loop filter. The output of the loop filter 240 is coupled to a first input of a signal combiner 250, here represented as an adder signal.

[0038] Signal combiner 250 is implemented as a part of a modulation circuit and can be omitted from ADPLL 200 configurations that do not require modulation. The output of the combiner 250 is coupled to the control input of the DCO 210.

The modulation circuit is configured to implement two-point modulation. A two-point modulator 260 is configured to receive a transmit signal, such as a transmit baseband signal from a transmit data source (not shown). The two-point modulator 260 processes the transmit signal and drives closed-loop and open-loop modulation inputs on the ADPLL 200.

[0040] The output of the two-point modulator 260 is coupled to a delta-sigma modulator (DSM) 264 that drives the fractional divider to implement the closed-loop modulation of the ADPLL 200. The output of the two-point modulator 260 also drives a scaler 262 that drives the second input to combiner 250 to introduce open loop modulation of the ADPLL output 200. Scaler 262 can be configured to compensate for the

ES 2 809 488 T3 gain of DCO 210. However, the value of scaler 262 need not be related to the gain of DCO 210 and can be configured to provide a gain that works in conjunction with the output of two-point modulator 260 to provide the desired modulation.

[0041] Figure 3A is a simplified functional block diagram of an embodiment of a phase-to-frequency detector 232 coupled to a sign generator 320. The phase-to-frequency detector 232 may be, for example, the detector of phase to frequency of the ADPLL of Figure 2. The signal bit output from the signal generator 320 may indicate, for example, whether the divider input to the phase-to-frequency detector 232 is ahead or behind the reference clock of the reference oscillator.

[0042] The phase-to-frequency detector 232 may be implemented as an UP / DOWN counter controller. Although the UP and DOWN outputs can be used to drive the inputs corresponding to an UP / DOWN counter, hence the names. Although the time-to-digital converter described herein as part of the PDC does not use UP and DOWN counts, it may be useful to refer to the outputs of the PFD 232 as UP and DOWN output signals to allow comparisons with implementations that use a counter. UP AND DOWN. Of course, the UP and DOWN labels are arbitrary and the PFD 232 outputs could be labeled as 1st and 2nd output or by some other distinctive name.

The PFD 232 includes two D (DFF) flip-flops, 312 and 314, which have an input value of high, Vdd, coupled to each of the D inputs. The two DFFs 312 and 314 are described as on. per rising edge, but could be reconfigured to use any combination of rising and falling edge triggers.

[0044] The PFD 232 receives the divided frequency divider signal coupled to the DCO, NDIV, on the clock input to the first DFF 312. The first DFF 312 synchronizes the Vdd value with the Q output to output a high active DOWN signal on the rising edge of the NDIV signal. Similarly, the second DFF 314 receives the reference clock, FREF, at the clock input and synchronizes the Vdd value with the Q output to output a high active UP signal on the rising edge of the FREF signal.

[0045] One of two AND gate inputs 318 has a first input coupled to the Q output of the first DFF 312 and a second input coupled to the Q output of the second DFF 314. The output of the AND gate 318 is coupled to the Reset inputs. of the first and second DFFs, 312 and 314. AND gate 318 operates to reset both DFF 312 and 314 after each UP / DOWN pair.

[0046] The sign generator 320 operates on the UP and DOWN outputs of the PFD 232, as well as the FREF signal. However, the token generator 320 can also be reconfigured to operate to use the NDIV signal.

[0047] The output of the signal generator 320 indicates which input, up or down, reaches the signal generator 320 first. The DOWN output of the PFD 232 is coupled to the D input of a first DFF sign 322 and the UP output of the PFD 232 is coupled to the DFF 322 first sign clock. The DOWN output of the PFD 232 is sampled by the rising edge of the UP signal to indicate the sign of the current UP / DOWN pair.

The sign of the UP / DOWN pair is read by a second sign flip-flop 324 synchronized by the FREF reference clock. The Q output of the second sign DFF 324 indicates the sign output of the system. The Sign output indicates the sign of the UP / DOWN pair in which the previous FREF edge was involved. The reason for using UP to sample DOWN is that the UP edge comes with each FREF edge, while the DOWN signal has no such predictability. If the duration of an UP / DOWN pair is greater than one FREF period, then there is no UP edge with each FREF edge. But in this situation, the sign for each FREF period that belongs to the wide phase difference is the same as it was at the beginning of the current phase difference. Therefore, the output of the first DFF 322 sign would be the correct sign to read at each FREF edge by the second DFF 324 sign.

[0049] Figure 3B is an alternative embodiment of a sign generator 320 that does not rely on a phase-to-frequency detector, but determines the sign directly from the two inputs, FREF and NDIV to a phase-to-frequency converter. digital.

The embodiment of the sign generator 320 of Figure 3B includes a Flip-Flop D (DFF) 330 and an OR gate 332. The reference clock signal, FREF, is coupled to input D to DFF 330 The divided signal (NDIV) of the frequency divider coupled to the DCO is coupled to the inverted D input (/ D) of the DFF 330. The output of the DFF 330 indicates the sign.

The reference clock signal, FREF, is also coupled to a first input of a logic OR gate 332. The split signal, NDIV, is coupled to the second input of logic OR gate 332. The output of the gate OR 332 is coupled to the clock input of the DFF 330. Therefore, the first of the FREF or NDIV signals synchronizes the DFF 330. The inputs to the DFF 330 function effectively as a differential input signal whose phase at the edge of the clock indicates the sign.

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[0052] Figure 4A is a simplified functional block diagram of an embodiment of a magnitude converter part of a time-to-digital converter 400. The magnitude converter part 400 can be used in conjunction with the sign generator. and the PFD of Figure 3A to implement a phase-to-digital converter, such as the phase-to-digital converter of Figure 2. The magnitude converter 400 portion of the time-to-digital converter may be implemented, for example, within the PDC of Figure 2 to facilitate the implementation of an ADPLL that has low current requirements but provides high phase resolution.

The magnitude converter portion 400 includes symmetric processing paths, with a first processing path triggered by the UP signal from a PFD and a second processing path triggered by the downstream signal from the PFD. The results of one of the first or second processing path are selected for the magnitude value based on the selection processing.

The first processing path includes the first control multiplexers 410-1 that are used to initialize the processing path. The first processing path includes a download multiplexer 412-1 that selectively couples one of the UP signals or a predetermined signal to the processing path. In the embodiment of Figure 4A, download multiplexer 412-1 selectively couples a low or zero value to the processing path to download the previous contents of the processing path to ensure that the processing path begins in a state known. During time-to-digital conversion, download multiplexer 412-1 couples the UP signal to the processing path.

[0055] The output of the download multiplexer 412-1 is coupled to an input of a feedback control multiplexer 414-1 that operates to selectively feed back a pulse that has traversed an entire delay in the processing path. The feedback control multiplexer 414-1 initially selects the output of the discharge multiplexer 412-1 and selects the feedback pulse if the time for digital conversion has not yet completed.

[0056] The output of the control multiplexers 410-1 is coupled to a control input of a pulse generator 420-1. The output of pulse generator 420-1 is coupled to an edge aligner 430-1 that functions to substantially align the timing of the rising and falling edges of the pulse output from pulse generator 420-1.

[0057] Edge aligner 430-1 is depicted as generating a differential output that is coupled to a delay line 440-1. Delay line 440-1 introduces a predetermined fixed delay to the pulse signal emitted by pulse generator 420-1 and aligned on edge aligner 430-1.

[0058] Delay line 440-1 can be configured as a tapped delay line, and each delay line of the tapped delay line can be coupled to a first route selection multiplexer 450. The first selection multiplexer Route 450 selectively routes one of the first processing path or the second processing path with delay line tap values ​​with differential taps to a retrieval register 460. The output of the catch-up register 460 represents a fractional delay across the delay line.

[0059] Delay line 440-1 may be configured to send a single ended delayed pulse signal. The single-ended output of delay line 440-1 represents the feedback pulse that is routed to the second input of feedback control multiplexer 414-1.

The single-ended output of delay line 440-1 is also coupled to a second path selection multiplexer 452 that selectively routes one of the first processing path or second processing path to an input of a multiplexer. counter enable 454. The counter enable multiplexer 454 sends an enable signal to a counter 470 that operates to count the number of full delay transitions of a pulse through the delay line.

The second processing path is configured substantially identical to the first processing path. The second control multiplexers 410-2 include a second download multiplexer 412-2 that has one input coupled to the PFD to receive the DOWN signal and a second input configured to receive the logic low level. The output of the second download multiplexer 412-2 is coupled to a second feedback control multiplexer 414-2 that selectively couples the output of the second download multiplexer 414-2 or a delayed pulse signal to its output.

[0062] The output of the second feedback control multiplexer 414-2 is coupled to a drive input of a second pulse generator 420-2. The pulse output of the second pulse generator 420-2 is coupled to a second edge aligner 430-2. The output of the second edge aligner 430-2 is coupled to a second delay line 440-2.

The single-ended output of the second delay line 440-2 is fed back to the second feedback control multiplexer 414-2. The taps on the second delay line 440-2 are coupled to a second

ES 2 809 488 T3 input of the first route selection multiplexer 450. Similarly, the delayed pulse from a single end is coupled to a second input of the second route selection multiplexer 452.

[0064] After UP and DOWN go up, indicating the end of an UP-DOWN pair, the discharge signal goes down for a short period allowing a zero level on the delay lines. This action clears the delay line and resets it for the next measurement.

[0065] Feedback control: FB-U_ctrl is for the branch of the circuit for the UP input and FB-D_ctrl is for the branch of the circuit for the DOWN input. Whichever input, UP or DOWN, comes first, its feedback control signal goes up allowing pulse recycling. Feedback control signal goes low when UP - DOWN torque ends.

[0066] The Sel signal at the control input of the first path selection multiplexer 450 controls which delay line will be read. If UP comes before DOWN, the delay line output for the UP input is connected to retrieval register 460 and the other way if DOWN comes before UP.

[0067] If UP comes before DOWN, the control signal Sel_1 allows FB-U to pass through the second route selection multiplexer 452 it controls and FB-D if DOWN comes before UP.

[0068] The Sel_2 signal goes up with a start signal that is activated by the first UP or DOWN, | UP DOWN |, allowing the selected delayed pulse to enter counter 470. The Sel_2 signal goes down, thus blocking the pulse, and its rising edge signifies the end of an UP-DOWN pair. So, in a sense, it enables counter 470 when needed.

In operation, both the first and second processing paths are triggered by the respective UP and DOWN signals of the PFC. The trigger signal in each processing path triggers a pulse generator. The pulse from the pulse generator is coupled to a tapped delay line. The output of the tapped delay line is fed back to the trigger input of the pulse generator, so that the delayed pulse works to reactivate the pulse generator. Each complete pulse transition through the delay line increments one counter. At the end of the conversion period, it can be determined that the total delay is the counter value multiplied by the delay of the delay line plus the fractional transition of the pulse through the delay line, which can be determined by examining the taps of a tapped delay line. A selector controller determines whether the counter and derived delay register store values ​​from the first or second processing path.

In the TDC 400, before an UP-DOWN pair is initiated, the Download and Feedback control signals are controlled in such a way that the multiplexer they control will allow the UP and DOWN input to pass through to download content. delay lines 440-1 and 440-2 and to reset counter 470.

In response to the rising UP and DOWN edges the corresponding pulse generator (PG) 420-1 and 420-2 generates a pulse of fixed duration, independent of the high UP or DOWN period. This pulse passes through a respective edge aligner (EA) 430-1 and 430-2, which aligns the rising and falling edges at its output. The rising and falling edges are used within the differential delay line for phase difference measurement. After edge alignment, the pulse enters delay line 440-1 or 4402 for magnitude measurement.

Whichever input is, UP or DOWN, its corresponding feedback control signal goes up after the rising edge passes through the feedback multiplexer 414-1 or 414-2. However, the feedback control signal corresponding to the later arriving input remains low even after its rising edge arrives. In this way, only the pulse that arrives first can pass through the delay line and fall back if the phase difference is greater than the delay line time duration. The later UP or DOWN pulse is used to read the delay line of the main signal and therefore does not need to be repeated.

[0073] The pulse output of delay line 440-1 or 440-2 of the input that arrives first is connected to the input of counter 470 through multiplexers 452 and 454 controlled by Sel_1 and Sel_2. If the phase difference is more than a full delay line time duration, the delayed pulse exiting delay line 440-1 or 440-2 passes to counter 470 increasing its count. This delayed pulse also regresses and passes through its respective 440-1 or 440-2 delay line again. In the embodiment of Figure 4A, the delayed pulse reactivates the pulse generator. This cycle repeats until the second UP or DOWN input arrives. The second input means the end of the current UP-DOWN pair and the control signal Sel_2 goes low, blocking the counter input. At this time, the relevant delay line can also be read, via the later input, and its state is stored in flip-flops or other registers on the delay line.

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[0074] When the next UP-DOWN pair begins, the counter reading is stored in an intermediate layer of flip-flops and from there it is read to the next FREF edge. The control signal Sel connects the selected delay line output (flip-flop outputs) to obtain the recovery register 460. The recovery register 460 can be, for example, a group of flip-flops synchronized by the FREF that reads the delay line output. Therefore, on each FREF edge, the TDC 400 C <0: 4> and D <0:47> outputs are updated.

The selection controller 480 may be implemented as one or more modules that are configured to generate the various control signals based on the UP, DOWN, and FREF signals. Figures 11-15 include some examples of modules within selection controller 280.

[0076] Figure 4B is a simplified functional block diagram of an alternative embodiment of a phase-to-digital converter 230, as may be used in the ADPLL of Figure 2. The embodiment of the phase-to-digital converter digital 230 of Figure 4B is similar to the magnitude converter 400 of Figure 4A. However, the phase-to-frequency converter 230 of Figure 4B can be configured to perform substantially the entire phase-to-digital conversion process without the need for a phase-to-frequency converter and without the need for symmetrical processing paths. A first signal processing path includes elements that determine the digital value of the phase difference during the period of time defined by the second processing path.

[0077] Some parts of the phase-to-frequency converter 230 of Figure 4B have been omitted for the sake of clarity. For example, the hardware to unload delay line 440 is omitted, but may be similar to the hardware illustrated in Figure 4A. Similarly, the hardware associated with reading the status of delay line 440 is omitted from the block diagram, but may be substantially similar to the configuration shown for the magnitude converter of Figure 4A.

[0078] The phase-to-digital converter (PDC) 230 of Figure 4B includes a single delay path and feedback path. The PDC 230 determines the digital value in much the same way as the converter illustrated in Figure 4A, but without the symmetric paths. A 470 counter stores a count value that indicates several complete pulse transitions through the delay line, and the value read from the delay line value indicates the fractional part of the pulse transition through the delay line. 440.

The PDC 230 includes a first fixed delay 490-1 and a second fixed delay 490-2 that function to delay the reference clock and the split signal, respectively. The fixed delays 490-1 and 490-2 are used to introduce a slight delay that allows the processing of the sign value that is used to control the selection of the signals through the two signal processing paths. The outputs of fixed delays 490-1 and 490-2 are coupled to the inputs of a first route selection multiplexer 416-1 and the inputs of a second route selection multiplexer 416-2.

[0080] The first processing path includes the first path selection multiplexer 416-1. The output of the first route selection multiplexer 416-1 is substantially the first arrival signal transition, whether it comes from the reference clock or the split signal. The output of the first route selection multiplexer 416-1 is coupled to an input of a first pulse generator 420-1. The output of the first pulse generator 420-1 is coupled to the first input of a loop multiplexer 492 that is configured to select one of the pulse generator outputs or a delayed pulse output, corresponding to the output of the signal line. delay 440.

[0081] The output of the loop multiplexer 492 is coupled to the delay line 440. The delay line 440 couples the delayed pulse output to an input of the counter 470. Each pulse output from the delay line 440 increments the value. count in counter 470. Delay line 440 couples the delayed pulse output to the second input of loop multiplexer 492.

[0082] Loop multiplexer 492 is initially configured to select the first output of pulse generator 420-1 at the start of each PDC conversion cycle. After the initial pulse transition through loop multiplexer 492, the loop control signal that controls the input selected by loop multiplexer 492 controls loop multiplexer 492 to select the second feedback input. Loop multiplexer 492 continues to select the feedback input until completion of the conversion cycle, as indicated by the second processing path.

The inputs to the second route selection multiplexer 416-2 are inverted with respect to the inputs to the first route selection multiplexer 416-1. The signal selection control for both multiplexers 416-1 and 4162 is coupled to the sign signal. Therefore, the second route selection multiplexer 416-2 in the second processing route operates to select the second incoming signal.

The output of the second route selection multiplexer 416-2 is coupled to an input of a second pulse generator 420-2. The output of the second pulse generator 420-2 is coupled to a first input of a conversion control multiplexer 494. The output of the conversion control multiplexer 494 is coupled to the read input of the delay line 440, as well as to the clock or register input of counter 470.

ES 2 809 488 T3

[0085] A low to high transition of the output of the conversion control multiplexer 494 is the conversion completion signal indicating the end of the conversion cycle, and can function to synchronize the delay line values ​​with taps in the registers and synchronize the counter value 470 with a register.

[0086] The conversion control multiplexer 494 is initially configured to select a predetermined value, such as a low value, or zero, at the start of each PDC conversion cycle. The conversion control multiplexer 494 operates, based on the loop control signal, to select the output of the second pulse generator 420-2 once the pulse generator output in the first processing path has entered the line. delay 440. The use of the second pulse generator 420-2 and the conversion control multiplexer 494 also helps to match the propagation delays experienced by the control signals with the initial signal propagation delays in the first signal processing path. .

[0087] At the completion of the conversion cycle, the digital value of the phase difference is given by the value of the counter and the value of the delay line with taps 440. The value of the counter indicates the number of complete transitions of a pulse through the delay line and the value of the tapped delay line 440 indicates the fractional transition of the pulse through the delay line 440.

[0088] Figure 5 is a simplified functional block diagram of an embodiment of a pulse generator 420, which can be used in the TDC of Figure 4A or the PDC of Figure 4B. Pulse generator 420 is configured to generate a fixed width pulse in response to a rising edge at its input. The width of the pulse can be set to be virtually any width that is less than the total delay of the delay line. The pulse generator 420 of Figure 5 is configured to provide a narrow pulse width on the order of 150 pS. Other pulse generator configurations can be configured to provide pulse widths on the order of 370 pS or some other duration.

[0089] The pulse generator 420 includes a first inverter 510 having an input coupled to the input of the pulse generator 420. The source of a p-type FET 520 and the source of an n-type FET 540 are also coupled to the pulse generator input 420.

The output of the first inverter 510 is coupled to an input of a second inverter 512. The output of the first inverter 510 is also coupled to the gate of the n-type FET 540. The output of the second inverter 512 is coupled to the gate of the p-type FET 520 and to the gate of a grounding FET 530 that has its source coupled to ground or voltage return. The drains for the p-type FET 520, n-type FET 540, and grounding FET 530 share a common connection and are common to the output of the 420 pulse generator.

From a low initial state, the p-type FET 520 is not conducting, the grounding FET 530 is not conducting, and the n-type FET 540 is conductive, thereby coupling and reinforcing the state. low input to output that way.

[0092] On the rising edge of an input signal, the first inverter 510 turns its output to a low state after a propagation delay. This creates a negative gate source potential on the n-type FET 540, causing it to go into a high impedance state.

[0093] The p-type FET 520 experiences a negative gate source potential before the signal propagates through the second inverter 512. During this time period, the p-type FET 520 conducts and couples the input level. stop at the exit.

The transition of the first inverter 510 to the low state causes the output of the second inverter 512 to go high after a propagation delay. As the output of the second inverter 512 goes high, the voltage at the gate of the p-type FET 520 increases, thus cutting off the conduction of the p-type FET 520. Transitioning the output of the second inverter 512 to a high state also causes the grounding FET 530 to conduct, which grounds the output and provides a path from the output to ground to prevent a floating output.

[0095] A transition on the input from a high state to a low state does not cause any state change at the output of pulse generator 420, but causes the grounding FET 530 to go into a high impedance state. However, the n-type FET goes into a conductive state, thus providing a ground path for the output of pulse generator 420.

[0096] Figure 6 is a simplified functional block diagram of an embodiment of a part of a tapped delay line 600. The part of a tapped delay line 600 can be, for example, a part of a delay line at the TDC of Figure 4A.

[0097] Line delay 600 can be configured with three inputs. Two of the inputs correspond to differential inputs that are coupled to the delay element chain. A third input receives a Read signal, which upon arrival blocks the status of the delay chain. The status of the delay elements can be read later or locked in the recovery register block at the FREF edge.

ES 2 809 488 T3

The delay line 600 of Figure 6 has a resolution of 22 ps, which is almost the same as the minimum logic level regenerative delay obtainable in the 65 nm CMOS process and which in turn is substantially the same as the propagation delay of a native inverter. This delay resolution is substantially half the minimum delay through the buffer, which is generally made up of two inverters. In order to obtain an improvement in resolution due to the use of an inverter instead of a buffer memory as a delay element, its odd-even characteristic must match, that is, the rise and fall times must be the same.

[0099] Delay chain 610 is implemented using balanced inverters, eg 612a, 612b, configured in series. The delay chain 610 is implemented using two parallel inverter chains. Inverter strings are alternately read by differential flip-flops, eg 662-k, with a very narrow (~ 2ps) and balanced metastability window. The k-th D flip-flop 662-k after an odd number of inverters has its D input coupled to a first inverter chain and its D input coupled to a corresponding point in the second parallel inverter chain. The D (k + 1) flip-flop, 662- (k + 1), has its D input coupled to the second parallel inverter chain that follows the (k + 1) inverter, 612- (k + 1) and its input D coupled to the first string of inverters following inverter (k + 1), 613- (k + 1). In this way, the registered output of each D flip-flop, for example 662-k, 662- (k + 1), 662- (k + 2), has the same polarity and touches the delay line 610 that follows to each delay element.

[0100] Delay line 610 can be configured with 48 elements (96 total inverters in two parallel delay chains) and therefore a nominal time period of approximately Ins. Two such delay lines 610 are employed by the PDC. On one of the delay lines, a pulse activated by the UP signal runs through the delay chain and the DOWN signal synchronizes the flip-flops and reads the state of the delay chain upon arrival, while on the Another delay line, a pulse triggered by the DOWN signal goes through the delay chain and the UP signal synchronizes the flip-flops, for example 662.

[0101] A select controller determines which of the UP and DOWN signals came first, and controls the relevant delay line from which the flip-flops are read. The load presented to the UP and DOWN signals by the delay lines is not sign dependent. So any time mismatch due to any mismatch in the identical paths for the UP and DOWN delay lines 610 shows up as a simple time offset on the output, which probably doesn't affect phase lock.

[0102] However, if only one delay line is used and, depending on its arrival sequence, the UP and DOWN pulses are routed to a single 610 Delay chain, and then a time mismatch due to non-ideality after sign-dependent routing determines the delay line input will result in non-linearity. A mismatch after sign-dependent routing changes the transfer function to one that has non-linearity expressed as jump or offset at the origin.

[0103] Figure 7 is a simplified functional block diagram of one embodiment of an edge aligner 430, such as the edge aligner used in the TDC of Figure 3A.

[0104] The 430 Edge Aligner takes a differential signal that has a rising edge and a falling edge whose transition times have a small difference (~ 30 ps) and provides edge-aligned output where the rising and falling edges align .

[0105] Edge aligner 430 includes parallel inverter paths, cross-coupling the following signals to the outputs of the individual inverters to equalize the rise and fall delays. The sizes of the inverters used in each string of inverters can be gradually increased along the string to allow the output of the edge aligner 430 to drive buffers that will be heavily loaded. In the embodiment of Figure 7, the part enclosed in a rectangle is the unit that does the edge alignment work. Two of these blocks have been used for best results. The second edge alignment block can have larger transistors to increase drive capabilities along the chain.

[0106] Figure 8 is a simplified functional block diagram of one embodiment of a counter 800. The counter 800 is configured as a five-bit counter and includes a series configuration of flip-flops 8101 through 810-5. Each flip-flop, for example 810-1, connects its inverted output to input D. Also, the output of each flip-flop, for example 810-1, synchronizes the next flip-flop, for example the output DFF 810-1 synchronizes DFF 8102.

[0107] The clear control signal resets the counter 800 before the next counting cycle begins. In an alternate embodiment illustrated in Figure 9, the erase control signal occurs after the outputs of counter 470 are stored in another layer of flip-flops. The start of a count cycle is not related to the FREF edge, as it can be triggered by an NDIV edge. In that case, the output of the old counter must be stored before a new cycle begins to avoid losing the counter value. For

ES 2 809 488 T3 therefore, the reading of counter 800 is stored in flip-flops (not shown) before the next cycle begins from where they are read at the next FREF edge by another layer of flip-flops.

[0108] Figure 9 is a simplified functional block diagram of an alternate embodiment of a counter 470 that has multiple layers of flip-flops, and can be used as the counter in the TDC of Figure 4A.

[0109] When a new UP-DOWN pair starts, a pulse follows in Counter_clear, which stores the counter output in the first layer of flip-flops 910-1 to 910-5, and clears counter 800. Later, after After the FREF edge arrives, the outputs of this flip-flop layer, 910-1 through 910-5, are stored in a second flip-flop layer 920-1 through 920-5. The second layer of flip-flops 920-1 to 920-5 is clocked by DXO, which can be a delayed version of the reference clock, FREF. For example, the DXO delayed reference clock can be implemented by delaying FREF three clk-to-Q flip-flop delays.

[0110] It is preferred to use the delayed clock to address the situation where an UP-DOWN pair starts with FREF. The pulse in Counter_clear follows this FREF edge and the signals emitted in the first layer of flip-flops 9101 to 910-5 could be old and not values ​​that were updated at the FREF edge.

[0111] Figure 10 is a simplified schematic of one embodiment of a counter clear generator 1000 for use in clearing the counter prior to each TDC conversion operation. The counter clear generator 1000 includes a first D flip-flop 1010 having a first buffer 1012 with the input of the buffer 1012 coupled to the Q output of the first D flip-flop 1010 and the output of the buffer 1012 coupled to the reset input of the first D flip-flop 1010. The D input is connected to a high voltage. The clock input is coupled to the FREF reference oscillator. The first D flip-flop 1010 is configured to generate a pulse on each rising edge of FREF.

[0112] The Q output of the first D flip-flop 1010 is also coupled to the clock input of a second D flip-flop 1020. The D input of the second D flip-flop 1020 receives the UP signal from the PFD. The Q output of the second D flip-flop 1020 is connected to the input of a second buffer 1022. The output of the second buffer 1022 is connected to the reset input of the second D flip-flop 1020.

[0113] A first OR gate receives the UP and DOWN signals at its input and sends the logical OR of the two signals. The output of the first OR gate 1030 drives a first pulse generator 1042, the output of which is coupled to an input of a second OR gate 1050.

[0114] The Q output of the second D flip-flop 1020 drives a second pulse generator 1044 whose output is coupled to a second input of the second OR gate 1050. The output of the second OR gate is the counter clear signal.

[0115] Counter clear generator 1000 generates a pulse that follows the beginning of each UP-DOWN pair. If this pair starts due to the rising edge in UP or DOWN, then the pulse is generated in the pulse generator P1 that causes the required pulse. However, if this UP-DOWN pair exists due to activity in the preceding FREF cycle, then no pulse would be generated at P1 as the output of the preceding first OR gate 1030 is already high. In this case, the pulse is generated at P2 from the second pulse generator 1044. In this situation, UP went up on the previous FREF edge and has been high ever since. At the current FREF edge, UP must be high. After the FREF edge of the first D flip-flop exits, 1010 rises and then resets a short period later (effectively a pulse is generated at its output). This pulse samples UP and if it is high, it will generate a pulse from the second pulse generator 1044 at P2 and at Counter_clear. The reason for delaying the FREF edge by a clk-to-Q delay before sampling UP is to avoid pulse generation in a situation where NDIV arrives before FREF but very close to it. In this case, delaying the FREF will allow time for the UP to go down. However, using FREF without delay will not cause many errors, since clearly in this situation the phase difference is large (such as an acquisition period) and the precision is still sufficient for the application.

[0116] Figure 11 is a simplified schematic diagram of an embodiment of a control signal generator Sel. The DOWN signal is coupled to the D input of a first DFF 1, 1110 flip-flop, while the UP signal is connected to the clock input. The Q output of DFF 1 1110 is coupled to the D input of a second D DFF 2 flipflop, 1120. An inverter 1130 reverses the FREF reference clock and couples the inverted signal to the DFF 2 clock input 1120.

[0117] Signal Sel is updated every falling edge of FREF. Therefore, half of a reference clock period, TREF, is available before the FREF edge, for which it is intended. The signal remains valid for half the duration of TrEf. If UP comes before DOWN, the output of DFF 1 1110 is high a few seconds after the FREF edge (UP and FREF are in sync) and the falling FREF edge after this event will lock this value into DFF 2 1120 which will serve as Sel in the next FREF edge.

ES 2 809 488 T3

[0118] Figure 12 is a simplified schematic of one embodiment of a start / stop generator 1200, the start and stop signals of which are used by various other modules within the PDC. These two signals, which are generated from UP and DOWN, are used in TDC to generate various control signals. The rising edge at Start denotes the beginning of the UP-DOWN pair and the rising edge at Stop denotes the end of the pair.

[0119] The UP signal is coupled to the first inputs of an OR gate 1210 and an AND gate 1220, while the DOWN signal is coupled to the second inputs of the same gates. The output of the OR gate 1210 represents the start signal, while the output of the AND gate represents the stop signal.

[0120] Figures 13A and 13B illustrate generators 1300 and 1350 for Sel_1 and Sel_2 signals, respectively, used by control multiplexers. These two control signals for 2 to 1 multiplexers determine when to allow pulses in the counter and from which delay line. The Start and Stop signals are used in the generation of these control signals. Sel_1 determines whether the output pulse from the UP or DOWN synchronized delay line should go to the counter, and Sel_2 determines whether the pulse leaving the delay line should go to the counter or should go a 0 to the counter.

[0121] The Sel_1 1300 generator generates the Sel_1 signal at the / Q output of a D 1310 flip-flop that has / DOWN at its D input and synchronized by the UP signal. The AD flip-flop 1320 with a buffer 1330 is configured as a pulse generator and is used to supply a reset signal to the D Sel_1 flip-flop 1310 on the rising edge of the stop signal. Initially, after receiving the Start signal, Sel_1 is low if UP comes before DOWN and high if DOWN comes before UP. At the arrival of Parada, Sel_1 goes up.

[0122] The Sel_2 generator 1350 generates the Sel_2 signal based on the Start signal. A first 1360 D flip-flop that has its D input connected to a high voltage uses the Start signal to sync the high level to the Q output on the rising edge of the Start signal. The Q output of the first D 1360 flip-flop is used to clock a second D 1370 flipflop that has its D input connected to a high voltage. Therefore, the Sel_2 signal is driven by the Start signal and is delayed by two clocks to delay the Q flip-flop. A third D flip-flop and 1390 buffer configured as a pulse generator sends a pulse to the reset inputs of the first and second flip-flops Ds 1360 and 1370 on a rising edge of the stop signal. Therefore, Sel_2 goes up with the rising edge of Start and goes down with the rising edge of Stop, which prevents the output pulses of the delay line from entering the counter.

[0123] Figures 14A and 14B illustrate generators 1400 and 1450 for the feedback control signals. These feedback control signals determine whether the delay line pulse outputs should go back to trigger another pulse on the input of their respective delay line. The first input signal to arrive, UP or DOWN, you can go back until the second input signal or Stop arrives. However, the second input that arrives does not cause the delayed pulse in its respective processing path to go back.

[0124] The UP feedback control generator 1400 operates to control the UP feedback path. If UP comes before DOWN, the output of DFF1 1410 is high after the rising edge of the UP signal. If Sel_2 is high (which occurs two clk-to-Q after startup), then the delay line it passes UP on goes into feedback mode. AND gate 1412 generates the logical AND of the DFF1 output 1410 with Sel_2 to ensure that the input path is interrupted to form the feedback path only after sufficient time is provided for the input pulse to pass through the feedback multiplexer up to the pulse generator input, since Sel_2 goes high after startup, which in turn goes high again approximately one gate delay after the start of the UP-DOWN pair. The DFF2 reset flip-flop 1420 is configured with a buffer 1430 to generate a reset pulse after the arrival of the Stop signal.

[0125] The DOWN feedback control generator 1450 functions to control the DOWN feedback path, and is configured substantially identical to the UP feedback control generator with the connections to the DOWN and UP signals reversed. If DOWN comes before UP, the output of DFF3 1460 is high after the rising edge of the DOWN signal. AND gate 1462 generates the logical AND of DFF3 output 1460 with Sel_2. The DFF4 reset flip-flop 1470 is configured with a buffer 1480 to generate a reset pulse after the arrival of the Stop signal.

[0126] Figure 15 is a simplified schematic of one embodiment of a discharge control generator 1500. The PDC is configured to discharge or clear the two delay lines of any pulses after the end of each UP-DOWN pair and before the input signals start the next cycle. This is done by disconnecting the input and feedback connections, injecting a logic 0 into the delay line, and waiting a duration greater than the delay chain time duration before reconnecting the inputs.

[0127] The discharge control generator 1500 includes a series connection of D flip-flops 1510, 1520, 1530, the number of which can be determined based on the total delay duration of the delay line. All D inputs are connected to a high voltage. The initial D flip-flop 1510 in the chain is locked by the

ES 2 809 488 T3 stop. The output of the first D flip-flop 1510 drives an inverter 1540 that outputs the discharge control signal. Each subsequent D flip-flop, for example 1520 and 1543, is locked by the output of the previous D flip-flop. The last D flip-flop 1530 drives a buffer 1550 that resets the states of all D flip-flops in the chain.

[0128] Therefore, the chain of flip-flops is configured to provide an output that skips a Q-delay clock and a propagation delay after the stop signal. The download control signal resets the next delays from N clock to Q further delayed by the propagation delay of buffer 1550.

[0129] After reaching Stop, both feedback control signals go down interrupting the feedback paths and then Discharge is also set to low, thus breaking the input connection and injecting 0 into the line. Discharge goes high shortly after (approximately a five-clkto-Q delay) re-establishing the input connection. Since the input connection is interrupted for a short period of time, if the next UP-DOWN pair starts during this period, it will be lost, that is, there will be a blind zone. In this design due to discharge, the blind zone lasts for approximately 1.5 ns under standard conditions. However, it is important to note that because Shock actually happens after Stop arrives and not after an UP-DOWN pair ends, there are no blind zones during phase difference of more than one TREF duration.

[0130] Figure 16 is a simplified flow diagram of one embodiment of a phase-to-digital conversion method 1600. Procedure 1600 can be implemented, for example, by the phase-to-digital converter (PDC) shown in the ADPLL of Figure 2.

[0131] Procedure 1600 begins at block 1610 where the PDC receives the signal from the oscillator, which may be, for example, a split signal from a voltage controlled oscillator. In the ADPLL example of Figure 2, the oscillator signal received by the PDC is a split signal from a digitally controlled oscillator.

[0132] The PDC proceeds to block 1620 where the PDC receives the reference clock signal, which may be, for example, a crystal oscillator signal. In one embodiment of an ADPLL integrated circuit, a crystal that is external to the integrated circuit can be used in conjunction with an on-chip reference oscillator. Although procedure 1600 illustrates that the PDC receives the reference clock after receiving the oscillator signal, the PDC generally receives both signals simultaneously and not serially.

[0133] The PDC proceeds to block 1630 and generates a phase-to-frequency detection (PDC) signal (s) based on the oscillator signal and the reference clock. In the embodiment of Figure 2, the PFD generates an UP signal and a DOWN signal, where the terms UP and DOWN simply distinguish the two signals and are not functionally descriptive.

[0134] The PDC proceeds to block 1640 and generates a time-to-digital conversion based on the PDC signals. In the embodiment of Figure 2, the TDC is configured to generate a sign of the phase difference and a magnitude of the phase difference using symmetrical delay lines, where the digital value is based on one or more than one transition. partial pulse through the symmetrical delay lines and several full transitions through the delay line.

[0135] The PDC proceeds to block 1650 and returns the digital value as a sign and magnitude. The sign is determined from the PFD signals and the magnitude value is determined from the PFD signals in conjunction with the delay line processing.

[0136] Figure 17 is a simplified flow diagram of one embodiment of a time-to-digital conversion procedure 1700. The procedure can be performed, for example, by the TDC of Figure 2, where the sign is determined in the manner shown in Figure 3A and the magnitude is determined in the manner shown in Figure 4A.

[0137] Procedure 1700 begins at block 1710 where the TDC receives one or more signals from the PFD. In the embodiment of Figure 3A, the PFD generates UP and DOWN signals based on the reference clock and the oscillator signal and their timing (phase) relationship to each other.

[0138] The TDC proceeds to block 1720 and determines the sign of the phase difference based on the PFD signals. The sign indicates whether the reference clock comes before the oscillator signal or vice versa.

[0139] The TDC proceeds to block 1730 and generates at least one pulse based on the PFD signal (s). In the embodiment of Figure 4A, the TDC is configured with symmetric processing paths, and the TDC drives a pulse generator on each path. The TDC drives one pulse generator based on the UP signal and a second pulse generator on the second symmetric path, based on the DOWN signal.

[0140] The TDC proceeds to block 1740 and couples the pulses to the respective delay lines in the respective processing paths. The TDC proceeds to block 1750 and determines which route is an active route. That is, the TDC

ES 2 809 488 T3 determines which of the symmetric processing paths to use for the TDC magnitude conversion. The active path represents the path for which a pulse feedback path is valid, which is used if the total time difference exceeds a full delay transition.

[0141] The TD proceeds to decision block 1760 and determines if a pulse has completely passed through the delay line. Otherwise, the TDC proceeds to decision block 1762 to determine if the conversion period has ended. If not, the TDC returns to block 1760 to monitor the progress of the pulse through the delay line. If, at decision block 1762, the TDC determines that the conversion period is over, the TDC proceeds to block 1790 to determine the conversion values.

[0142] At decision block 1760, if the pulse has completely crossed the delay line, the TDC proceeds to block 1770 and increments a counter indicating the number of times that a pulse on the active path has completely crossed the delay line. time delay. The TDC proceeds to decision block 1780 and determines if the conversion period has ended.

[0143] If the conversion period has not yet expired, the TDC continues to lock 1782 and feed back the pulse to the input of the delay line. The TDC can perform pulse feedback by feeding the delayed pulse to trigger a next pulse in the active processing path. After feeding back the delayed pulse to the input of the active path delay line, the TDC returns to block 1740.

[0144] If, in decision block 1780, the TDC determines that the conversion period is over, the TDC proceeds to block 1790 and determines the conversion values.

[0145] Conversion values ​​can include the sign and magnitude of the delay. If the magnitude is less than a full delay across the delay line, the magnitude can be a fine phase difference value that is representative of a partial transition of the pulse across the delay line. If the magnitude is greater than a full delay across the delay line, the magnitude can include an approximate phase difference and a fine phase difference. The approximate phase difference can be represented by the number of complete transitions through the delay line, which is indicated by the counter value. The fine phase difference is the same as described above.

[0146] If the magnitude is greater than a full delay, an ADPLL may be in acquisition mode, and may not need the resolution provided by the fine phase difference. In such an embodiment, the magnitude may be represented only by the approximate phase difference, and may omit the contribution due to the fine phase difference.

[0147] As used herein, the term coupled or connected is used to mean an indirect coupling, as well as a direct coupling or connection. When two or more blocks, modules, devices or apparatus are coupled, there may be one or more intermediate blocks between the two coupled blocks.

[0148] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general-purpose processor, with a digital signal processor (DSP), with a signal processor. reduced instruction set computer (RISC), with an application specific integrated circuit (ASIC), with a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor can be a microprocessor, but alternatively, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors together with a DSP core, or any other such configuration.

[0149] The steps of a procedure, process or algorithm described in relation to the embodiments disclosed herein can be performed directly in hardware, in a software module executed by a processor, or in a combination of the two. The various steps or actions in a procedure or process can be performed in the order shown, or they can be performed in another order. Additionally, one or more process or procedure steps can be omitted or one or more process or procedure steps can be added to procedures and processes. An additional step, block, or action can be added at the beginning, end, or by intervening existing elements of procedures and processes.