Systems and methods of rf power transmission, modulation, and amplification

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DESCRIPTION

RF transmission, modulation and amplification systems and procedures

The present invention relates, in general, to the transmission, modulation and amplification of RF power. More particularly, the invention relates to methods and systems for enhanced power amplification.

5 Prior art

In power amplifiers, there is typically a complex relationship between linearity and energy efficiency.

Linearity is determined by the operating range of a power amplifier on a characteristic curve that relates its input to the output variables - the more linear the operating interval,

10 The power amplifier is said to be more linear. Linearity is a desired characteristic of a power amplifier. In one aspect, for example, it is desired that a power amplifier uniformly amplify signals of varying amplitude and / or phase and / or frequency. Therefore, linearity is an important determinant of the output signal quality of a power amplifier.

Energy efficiency can be calculated using the ratio of total power delivered to a load divided by

fifteen the total power supplied to the amplifier. For an ideal amplifier, the energy efficiency is 100%. Typically, power amplifiers are divided into classes that determine the maximum theoretical energy efficiency of the amplifier. Energy efficiency is clearly a desired characteristic of a power amplifier, in particular, in wireless communication systems in which energy consumption is significantly dominated by the power amplifier.

twenty Unfortunately, the traditional compromise between linearity and efficiency in power amplifiers is such that, the more linear a power amplifier, the less efficient the power. For example, the most linear amplifier is polarized for class A operation, which is the least efficient class of amplifiers. On the other hand, higher class amplifiers, such as class B, C, D, E, etc., are of higher energy efficiency, but are considerably non-linear, which can result in signals.

25 Spectrally distorted output.

The commitment described above is underlined by typical wireless communication signals. Wireless communication signals, such as, for example, OFDM, CDMA and W -CDMA, are generally characterized by their peak to average power ratios. The higher the peak to average ratio of the signal, the more non-linear distortion will occur when non-linear amplifiers are used. He

30 US2004 / 0185805 discloses a LIMC power transmitter.

Offset amplification techniques have been proposed for RF amplifier designs. In various aspects, however, existing phase-out techniques are deficient in satisfying the amplification requirements of complex signals, in particular as defined, for example, by wireless communication standards.

35 In one aspect, existing offset techniques employ an isolation element and / or a combination element when constant envelope constituents of a desired output signal are combined. For example, it is usually the case that a power combiner circuit is used to combine the constituent signals. This combination approach, however, typically results in a deterioration of the output signal power due to loss of insertion and limited bandwidth and, correspondingly, a decrease in

40 Regarding energy efficiency.

In another aspect, the typically large size of the combination elements prevents having them in monolithic amplifier designs.

What is needed, therefore, are procedures and power amplification systems that solve the deficiencies of existing power amplification techniques while maximizing efficiency

Four. Five energy and nonlinear distortion is minimized. In addition, procedures and power amplification systems that can be implemented without the limitations of the techniques, and the power combination circuitry, are necessary.

Brief Summary

Embodiments for the combination power amplification of 50 vectors are disclosed herein.

In one embodiment, a plurality of substantially constant envelope signals are amplified individually, then combined to form a complex complex envelope signal variable in the desired time. The phase and / or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency and / or amplitude characteristics of the complex envelope variable signal in the desired time.

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In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of substantially constant envelope constituent signals. The constituent signals are amplified and then recombined to construct an amplified version of the time-varying envelope signal

5 original.

The embodiments of the present invention can be practiced with modulated carrier signals and with a baseband information and clock signals. The embodiments of the present invention also achieve a high frequency conversion. Accordingly, the embodiments of the present invention represent integrated solutions for high frequency conversion, amplification and modulation.

10 The embodiments of the present invention can be implemented with analog and / or digital controls. The embodiments of the present invention can be implemented with analog components or with a combination of analog components and digital components. In the last embodiment, digital signal processing can be implemented in an existing baseband processor for added cost savings.

fifteen Additional features and advantages of the embodiments of the present invention will be set forth in the description that follows. Even more features and advantages will be apparent to one skilled in the art, based on the description set forth herein, or can be learned by practicing the embodiments of the present invention. The advantages of the embodiments of the present invention will be realized and will be achieved by the procedures and structure indicated, in particular, in the written description and in

twenty the claims of this document, as well as in the attached drawings.

It is to be understood that both the foregoing summary and the following detailed description are exemplary and explanatory and are intended to provide a further explanation of the embodiments of the present invention as claimed.

Brief description of the figures

25 The embodiments of the present invention will be described with reference to the accompanying drawings, in which similar reference numbers generally indicate identical or functionally similar elements. Also, in general, the leftmost digit or digits of the reference numbers identify the drawings in which the associated elements are first introduced.

Figure 1A is an example illustrating the generation of a complex envelope signal that is time-variable.

30 copy. Figure 1B is another example illustrating the generation of a complex envelope signal variable in the exemplary time. Figure 1C is an example illustrating the generation of a complex envelope variable signal in the exemplary time from the sum of two or more constant envelope signals.

35 Figure 1D illustrates the power amplification of an example complex time-bound envelope signal. Figure 1E is a block diagram illustrating an exemplary vector power amplification. Figure 1 illustrates a fasorial representation of a signal. Figure 2 illustrates a fasorial representation of a complex envelope signal that varies over time.

40 Figures 3A-3C illustrate an exemplary modulation to generate a time-bound complex envelope signal. Figure 3D is an example illustrating a constant envelope decomposition of a time-varying envelope signal. Figure 4 is a fasorial diagram illustrating a Vector Power Amplification (VPA) procedure of

Four. Five 4 exemplary Cartesian branches. Figure 5 is a block diagram illustrating an exemplary 4-Branch Cartesian VPA procedure. Figure 6 is a process flow diagram for power amplification according to a 4-Branch Cartesian VPA procedure. Figure 7A is a block diagram illustrating an embodiment of a vector power amplifier for

fifty Implement a 4-Branch Cartesian VPA procedure. Figure 7B is a block diagram illustrating another embodiment of a vector power amplifier for implementing a 4-Branch Cartesian VPA procedure. Figure 8A is a block diagram illustrating another embodiment of a vector power amplifier according to a 4-Branch Cartesian VPA procedure.

55 Figure 8B is a block diagram illustrating another embodiment of a vector power amplifier according to a 4-Branch Cartesian VPA procedure. Figure 8C is a block diagram illustrating another embodiment of a vector power amplifier according to a 4-Branch Cartesian VPA procedure. Figure 8D is a block diagram illustrating another embodiment of a vector power amplifier of

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according to a 4-Branch Cartesian VPA procedure. Figures 9A-9B are fasorial diagrams illustrating an exemplary Vector Power Amplification (VPA) procedure of 2 Cartesian -Polar -Cartesian -Polar Branches (CPCP). Figure 10 is a block diagram illustrating an exemplary 2-branch CPCP VPA procedure.

5 Figure 10A is a block diagram illustrating another exemplary 2-Branch CPCP VPA procedure. Figure 11 is a process flow diagram for power amplification according to an exemplary 2-Branch CPCP VPA procedure. Fig. 12 is a block diagram illustrating an embodiment of a vector power amplifier for implementing a 2-Branch CPCP VPA procedure. Figure 12A is a block diagram illustrating another embodiment of a vector power amplifier for implementing a CPPA 2-Branch VPA procedure. Figure 12B is a block diagram illustrating another embodiment of a vector power amplifier for implementing a CPPA 2-Branch VPA procedure. Figure 13 is a block diagram illustrating another embodiment of a vector power amplifier for

fifteen Implement a 2-Branch CPCP VPA procedure. Figure 13A is a block diagram illustrating another embodiment of a vector power amplifier for implementing a CPPA 2-Branch VPA procedure. Figure 14 is a fasorial diagram illustrating an exemplary Direct Cartesian Branching Vector Power Amplification (VPA) procedure. Figure 15 is a block diagram illustrating an exemplary embodiment of the Direct Cartesian 2 Branch VPA procedure. Figure 15A is a block diagram illustrating another exemplary Direct Cartesian 2 Branch VPA procedure. Figure 16 is a process flow diagram for power amplification according to a

25 Exemplary Direct Cartesian 2 Branch VPA procedure. Figure 17 is a block diagram illustrating an embodiment of a vector power amplifier for implementing a Direct Cartesian 2 Branch VPA procedure. Figure 17A is a block diagram illustrating another embodiment of a vector power amplifier for implementing a Direct Cartesian 2 Branch VPA procedure. Figure 17B is a block diagram illustrating another embodiment of a vector power amplifier for implementing a Direct Cartesian 2 Branch VPA procedure. Figure 18 is a block diagram illustrating another embodiment of a vector power amplifier to implement a Direct Cartesian 2 Branch VPA procedure. Figure 18A is a block diagram illustrating another embodiment of a vector power amplifier.

35 to implement a 2-branch Cartesian Direct VPA procedure. Figure 19 is a process flow diagram illustrating an exemplary I and Q transfer function according to a 4-Branch Cartesian VPA procedure. Figure 20 is a block diagram illustrating an exemplary I and Q transfer function according to a 4-Branch Cartesian VPA procedure. Figure 21 is a process flow diagram illustrating an exemplary I and Q transfer function in accordance with a 2-Branch CPCP VPA procedure. Figure 22 is a block diagram illustrating an exemplary I and Q transfer function according to a 2-Branch CPCP VPA procedure. Figure 23 is a process flow diagram illustrating an exemplary I and Q transfer function of

Four. Five according to a procedure of VPA of 2 Direct Cartesian Branches. Figure 24 is a block diagram illustrating an exemplary I and Q transfer function according to a Direct Cartesian 2 Branch VPA procedure. Figure 25 is a fasorial diagram illustrating the effect of waveform distortion on a representation of a signal phasor. Figure 26 illustrates magnitude-in-phase transform functions. Figure 27 illustrates exemplary embodiments of a polarization circuitry in accordance with the embodiments of the present invention. Figure 28 illustrates an exemplary method of combining constant envelope signals. Figure 29 illustrates an exemplary vector power amplifier output phase.

55 Figure 30 is an exemplary block diagram of a power amplifier (PA) output phase. Figure 31 is a block diagram of another exemplary power amplifier (PA) output phase. Figure 32 is a block diagram of another exemplary power amplifier (PA) output phase. Fig. 33 is a block diagram of another embodiment of the power amplifier (PA) output phase according to the present invention. Figure 34 is a block diagram of another exemplary power amplifier (PA) output phase. Figure 35 is a block diagram of another exemplary power amplifier (PA) output phase. Figure 36 is a block diagram of another exemplary power amplifier (PA) output phase. Figure 37 illustrates an example output signal. Figure 38 illustrates an exemplary embodiment of PA.

65 Figure 39 illustrates an example time-varying complex envelope PA output signal and a corresponding envelope signal.

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Figure 40 illustrates exemplary synchronism diagrams of an output phase intensity of PA. Figure 41 illustrates exemplary output phase intensity control functions. Figure 42 is a block diagram of another embodiment of the power amplifier (PA) output phase.

5 Figure 43 illustrates a phase embodiment of PA. Figure 44 illustrates a PA output signal with exemplary wavy shape. Figure 45 illustrates an exemplary power control procedure. Figure 46 illustrates another exemplary power control procedure. Figure 47 illustrates an exemplary vector power amplifier.

10 Figure 48 is an exemplary process flow diagram for implementing an output phase intensity conformation. Figure 49 is an exemplary process flow diagram for implementing a harmonic control. Figure 50 is an exemplary process flow diagram for power amplification. Figures 51A -I illustrate output phase embodiments of multiple inputs and a single output

fifteen (MISO). Figure 52 illustrates an embodiment of MISO amplifier. Figure 53 illustrates an exemplary frequency band assignment in lower and upper spectrum bands for various communication standards. Figures 54A-B illustrate exemplary feed techniques in advance to compensate for errors.

twenty Figure 55 illustrates a technique of correction of feedback errors based on exemplary receiver. Figure 56 illustrates an exemplary digital control module. Figure 57 illustrates another exemplary digital control module. Figure 58 illustrates another embodiment of digital control module. Figures 59A-D illustrate an exemplary VPA analog core.

25 Figure 60 illustrates an exemplary output phase according to the VPA analog core of Figures 59A-D. Figures 61A-D illustrate another exemplary VPA analog core. Figure 62 illustrates an exemplary output phase according to the analog VPA core of Figures 61A-D.

30 Figures 63A-D illustrate another exemplary VPA analog core. Figure 64 illustrates an exemplary output phase - in accordance with the VPA analog core of Figures 63A -D. Figure 65 illustrates the real-time amplifier class control using an exemplary waveform, in accordance with an embodiment of the present invention.

35 Figure 66 is an exemplary graphical representation of the output power versus the offset angle. Figure 67 illustrates exemplary power control mechanisms using an exemplary QPSK waveform, in accordance with an embodiment of the present invention. Figure 68 illustrates the real-time amplifier class control using an exemplary waveform of

40 according to an embodiment of the present invention. Figure 69 illustrates the real-time amplifier class control using an exemplary waveform, in accordance with an embodiment of the present invention. Figure 70 illustrates an exemplary graphical representation of the theoretical efficiency of the VPA output phase versus the VPA output phase intensity, in accordance with an embodiment of the present invention.

Four. Five Figure 71 illustrates an exemplary VPA in accordance with an embodiment of the present invention. Figure 72 is a process flow diagram illustrating a procedure for real-time amplifier class control in a power amplifier, in accordance with an embodiment of the present invention. Figure 73 illustrates an exemplary VPA output phase.

fifty Figure 74 illustrates an equivalent circuit for amplifier class S operation of the VPA output phase of Figure 73. Figure 75 illustrates an equivalent circuit for amplifier class A operation of the VPA output phase of Figure 73. Figure 76 is a graphical representation illustrating a transform functions of magnitude in

55 Exemplary phase shift for Class A and Class S operation of amplifier of the VPA output phase of Figure 73. Figure 77 is a graphical representation illustrating a spectrum of transformed functions of magnitude in phase shift that They correspond to a range of amplifier operating classes of the VPA output phase of Figure 73.

60 Figure 78 illustrates a mathematical deduction of the magnitude transform in phase shift in the presence of amplitude and branch phase errors.

The embodiments of the present invention will be described with reference to the accompanying drawings. The drawing in which an element appears for the first time is typically indicated by the leftmost digit or digits in the corresponding reference number.

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Detailed description

Index of contents

1. Introduction

1.1. Example Generation of Complex Envelope Input Signals Variable in Time<dl><dt /><dd>5 1.2. Example Generation of Complex Envelope Signals Variable in Time from Constant Envelope Signals</dd></dl>1.3. Vector Power Amplification Set Vision 2. General Mathematical Set Vision 2.1. Fasorial Signal Representation<dl><dt /><dd>10 2.2. Complex Envelope Signals Variable in Time</dd></dl>2.3. Constant Envelope Decomposition of Time-Variable Envelope Signals 3. Vector Power Amplification Procedures and Systems (VPA) 3.1. Vector Power Amplifier with 4 Cartesian Branches 3.2. Vector Power Amplifier with 2 Cartesian Branches -Polar -Cartesian -Polar (CPCP)<dl><dt /><dd>fifteen 3.3. 2 Cartesian Direct Branch Vector Power Amplifier</dd></dl>3.4. Data Transfer Functions of I and Q to Vector Modulator 3.4.1. 4-Branch Cartesian VPA Transfer Function 3.4.2. 2-Branch VCP Transfer Function CPCP 3.4.3. VPA Transfer Function of 2 Direct Cartesian Branches<dl><dt /><dd>twenty 3.4.4. Magnitude for Transformed Phase Shift</dd></dl>3.4.4.1. Magnitude for Transformed Phase Shift for Sinusoidal Signals 3.4.4.2. Magnitude for Transformed Phase Shift for Square Wave Signals 3.4.5. Waveform Distortion Compensation 3.5. Exit Phase<dl><dt /><dd>25 3.5.1. Output Phase Achievements</dd></dl>3.5.2. Formation of Output Phase Intensity 3.5.3. Output Phase Protection 3.6. Harmonic Control 3.7. Power control<dl><dt /><dd>30 3.8. Execution of exemplary Vector Power Amplifier</dd></dl>Four. Additional Exemplary Implementations and Implementation 4.1. Overview 4.1.1. Output Power Control and Energy Efficiency 4.1.2. Compensation and / or Error Correction<dl><dt /><dd>35 4.1.3. Operation of Multiple Bands and Multiple Modes</dd></dl>4.2. Digital Control Module 4.3. VPA Analog Core 4.3.1. VPA Analog Core Implementation A 4.3.2. VPA Analog Core Implementation B 4.3.3. VPA Analog Core Implementation C 5. VPA Output Phase Real-Time Amplifier Class Control<dl><dt /><dd>5 6. Summary </dd></dl><figref>image6</figref> 7. Conclusions 1. Introduction This document discloses procedures, devices and systems for amplification of vector combination power. 10 Vector combination power amplification is an approach to optimize linearity and energy efficiency simultaneously. In general terms, and referring to the flowchart 502 in Figure 50, in step 504 a complex envelope input signal variable in time, with a variable amplitude and phase, decomposes into envelope constituent signals constant. In step 506, the constant envelope constituent signals are amplified and then added in step 508 to generate an amplified version of the complex input envelope signal. Because substantially constant envelope signals can be amplified with minimal concern about nonlinear distortion, the result of the sum of constant envelope signals experiences minimal nonlinear distortion while providing optimal efficiency. Accordingly, vector combination power amplification allows non-linear power amplifiers 20 to be used to efficiently amplify complex signals while maintaining minimum non-linear distortion levels. For purposes of convenience, and not limitation, reference is sometimes made herein to the procedures and systems of the embodiments of the present invention as procedures and vector power amplification systems (VPA). 25 The following provides a high-level description of VPA procedures and systems. For purposes of clarity, certain expressions are defined first in the following. The definitions described in this section are provided for convenience purposes only, and are not limiting. The meaning of these expressions will be apparent to those skilled in the art or subjects based on the totality of the teachings provided in this document. These expressions can be analyzed through the entire descriptive report in additional detail. The signal envelope expression, when used herein, refers to an amplitude limit within which a signal is contained as it fluctuates in the time domain. Quadrature modulated signals can be described by r (t) = i (t) · cos (ω · t) + q (t) · sin (ωc · t) in which i (t) and q (t) represent signals quadrature and in phase with the signal envelope e (t), which is equal to 35 phase associated with r (t) is related to arctan (q (t) / i (t)). The term "constant envelope signal", when used herein, refers to <figref>image7</figref> quadrature and phase signals in which <figref>image8</figref>, with e (t) having a relative or substantially constant value. The term time-varying envelope signal, when used herein, refers to a signal that has a time-varying signal envelope. A time-varying envelope signal can be described in terms of quadrature and phase signals as having a time-varying value. The term "phase shift", when used herein, refers to delaying or advancing the phase component of a constant or time-varying envelope signal in relation to a reference phase. 1.1) Exemplary Generation of Variable Input Signals in the Complex Envelope Time Figures 1A and 1B are examples that illustrate the generation of complex phase and envelope variable input signals that vary over time. In Figure 1A, the time-varying envelope carrier signals 104 106. The resulting signals 108 and 112 can therefore be shifted in phase in relation to signals 104 and 106. In the example of Figure 1A, the phase controller 110 results in a phase inversion <figref>image9</figref><figref>image10</figref> 5 (180 degree phase shift) in signals 104 and 106 at the instant of time to, as can be seen from signals 108 and 112. Signals 108 and 112 represent complex carrier signals variable in time . Signals 108 and 112 have both envelopes and phase components that vary over time. When added together, signals 108 and 112 result in signal 114. Signal 114 also represents a complex time-varying complex signal. The signal 114 may be an example input signal in the VPA embodiments of the present invention (for example, an example input in step 504 of Figure 50). Complex time-varying signals can also be generated as illustrated in Figure 1B. In Fig. 1B, signals 116 and 118 represent baseband signals. For example, signals 116 and 118 may be baseband components in phase (I) and quadrature (Q) of a signal. In the example of Figure 1B, signals 116 and 118 undergo a zero crossing as they transition from +1 to -1. The signals 116 and 118 are multiplied by the signal 120 or the signal 120 displaced in phase 90 degrees. Signal 116 is multiplied by a shifted version 0 degrees of signal 120. Signal 118 is multiplied by a 90 degree offset version of signal 120. The resulting signals 122 and 124 represent complex carrier signals that vary over time. It is noted that signals 122 and 124 have envelopes that vary according to the time varying amplitudes of signals 116 and 118. In addition, both of signals 122 and 124 undergo phase reversals in the zero crossings of signals 116 and 118. The signals 122 and 124 are summed to result in the signal 126. The signal 126 represents a complex signal that varies over time. The signal 126 may represent an example input signal in the VPA embodiments of the present invention. Additionally, signals 116 and 118 may represent input signals by way of example in the VPA embodiments of the present invention. 1.2) Exemplary Generation of Complex Envelope Signals Variable in Time from Constant Envelope Signals The description in this section refers, in general, to the operation of step 508 in Figure 50. Figure 1C illustrates three examples for the generation of complex signals that vary in time from the sum of two or more substantially constant envelope signals. A person skilled in the art will appreciate, however, based on the teachings provided herein, that the concepts illustrated in the examples of Figure 1C may extend similarly to the case of more than two envelope signals. constant. In Example 1 of Figure 1C, the constant envelope signals 132 and 134 are input into the phase controller 130. Phase controller 130 manipulates the phase components of signals 132 and 134 to generate signals 136 and 138, respectively. The signals 136 and 138 represent substantially constant envelope signals, and are added together to generate the signal 140. The phasor representation in Figure 1C, associated with example 1, illustrates signals 136 and 138 as the phasors P136 and P138, respectively. . Signal 140 is illustrated as the P140 phasor. In example 1, P136 and P138 move in phase symmetrically an angle ϕ1 in relation to a reference signal that is supposed to be aligned with the real axis of the fasorial representation. Correspondingly, the signals in the time domain 136 and 138 move in phase in equal amounts but in opposite directions relative to the reference signal. Therefore, P140, which is the sum of P136 and P138, is in phase with the reference signal. In Example 2 of Figure 1C, the substantially constant envelope signals 132 and 134 are input into the phase controller 130. The phase controller 130 manipulates the phase components of signals 132 and 134 to generate signals 142 and 144, respectively. The signals 142 and 144 are substantially constant envelope signals, and are added together to generate the signal 150. The fasorial representation associated with example 2 illustrates signals 142 and 144 as the phasors P142 and P144, respectively. Signal 150 is illustrated as the P150 phasor. In example 2, P142 and P144 move in phase symmetrically in relation to a reference signal. Therefore, similar to P140, P150 is also in phase with the reference signal. P142 and P144, however, phase shift an angle whereby ϕ2 ≠ ϕ1 in relation to the reference signal. P150, as a result, has a different magnitude than P140 of example 1. In the time domain representation, it is observed that signals 140 and 150 are in phase but have different amplitudes in relation to each other. In Example 3 of Figure 1C, the substantially constant envelope signals 132 and 134 are input into the phase controller 130. The phase controller 130 manipulates the phase components of signals 132 and 134 to generate signals 146 and 148, respectively. The signals 146 and 148 are substantially constant envelope signals, and are added together to generate the signal 160. The fasorial representation associated with example 3 illustrates signals 146 and 148 as the phasors P146 and P148, respectively. Signal 160 is illustrated as the P160 phasor. In example 3, P146 phase shifts an angle ϕ3 in relation to the reference signal. P148 moves in phase an angle ϕ4 in relation to the reference signal. ϕ3 and ϕ4 may or may not be the same. Therefore, P160, which is the sum of P146 and P148, is no longer in phase with the signal In summary, the examples in Figure 1C show that a time-varying signal of amplitude can <figref>image11</figref> 5 obtained by adding two or more substantially constant envelope signals (example 1). In addition, the time-varying signal may have amplitude changes, but not phase changes, imparted thereon by the equal displacement in the opposite directions of the two or more substantially constant envelope signals (example 2). By displacing the two or more constituents of the constant envelope of the signal in the same direction, phase changes, but not amplitude changes, can be imparted over the time-varying signal. Any phase and time-varying amplitude signal can be generated using two or more substantially constant envelope signals (example 3). It is noted that the signals in the examples of Figure 1C are shown as sinusoidal waveforms for illustration purposes only. One skilled in the art will appreciate, based on the teachings herein, that other types of waveforms may also have been used. It should also be noted that the 15 examples of Figure 1C are provided herein for purposes of illustration only, and may or may not correspond to a particular embodiment of the present invention. 1.3) Vector Power Amplification Set Vision The following provides a high level overview of the vector power amplification. Figure 1D illustrates the power amplification of a complex input signal variable in exemplary time 172. 20 Signals 114 and 126 as illustrated in Figures 1A and 1B may be examples of signal 172. In addition, signal 172 It can be generated by or being composed of two or more constituent signals such as 104 and 106 (Figure 1A), 108 and 112 (Figure 1A), 116 and 118 (Figure 1B) and 122 and 124 (Figure 1B). In the example of Figure 1D, VPA 170 represents an exemplary VPA system. The VPA 170 amplifies the signal 172 to generate the amplified output signal 178. The output signal 178 is efficiently amplified with a minimum distortion. In the example of Figure 1D, signals 172 and 178 represent the Ventilated voltage (t) and Volt (t) signals, respectively. At any time, in the example of Figure 1D, Vin (t) and Volt (t) are related in such a way that Volt (t) = Keventrada (tat '), in which K is a scale factor and t 'represents a time delay that may be present in the VPA system. For power implication, <figref>image12</figref>wherein the output signal 30 is a power amplified version of the input signal 172. The linear (or substantially linear) power amplification of complex time-varying signals, as illustrated in Figure 1D, is get as shown in figure 1E. Figure 1E is an exemplary block diagram that conceptually illustrates a vector power amplification. In Figure 1E, the input signal 172 represents a complex signal that varies over time. For example, the input signal 172 can be generated as illustrated in Figures 1A and 1B. The signal 172 can be a digital or an analog signal. In addition, signal 172 may be a base band or a carrier-based signal. Referring to Figure 1E, the input signal 172 or equivalent thereof is introduced in VPA 182. In Figure 1E, VPA 182 includes a state machine 184 and analog circuitry 186. The 40 state machine 184 may include analog and / or digital components. Analog circuitry 186 includes analog components. VPA 182 processes the input signal 172 to generate two or more signals 188 - {1, ..., n}, as illustrated in Figure 1E. As described with respect to signals 136, 138, 142, 144 and 146, 148, in Figure 1C, signals 188 - {1, ... , n} may or may not move in phase with each other over different periods of time. In addition, VPA 182 generates signals 188 - {1, ..., n} such that a sum 45 of signals 188 - {1, ..., n} results in signal 194 which can be a amplified version of signal 172. Referring again to Figure 1E, signals 188 - {1, ..., n} are substantially constant envelope signals. Therefore, the description in the previous paragraph corresponds to step 504 in figure 50. 50 In the example of figure 1E, which corresponds, in general, to step 506 in figure 50, each of the signals constant envelope 188 - {1, ..., n} is amplified independently by a corresponding power amplifier (PA) 190 - {1, ..., n} to generate the amplified signals 192 - {1,. .., n}. The PA 190 {1, ... , n} substantially amplify the respective constant envelope signals 188 - {1, ..., n}. The amplified signals 192 - {1, ..., n} are substantially constant envelope signals, and in step 508<figref>image13</figref> they are added to generate the output signal 194. It is noted that the output signal 194 may be a linearly (or substantially linearly) amplified version of the input signal 172. The output signal 194 may also be a version with high frequency conversion of the input signal 172, as described herein. 5 2. General Mathematical Overview 2.1) Fasorial Signal Representation Figure 1 illustrates a fasorial representation<figref>image14</figref>102 of a signal r (t). A fasorial representation of a signal is explicitly representative of the magnitude of the signal envelope and the phase shift of the signal in relation to a reference signal. In this document, for convenience, not limitation purposes, the reference signal is defined as aligned with the real axis (Re) of the orthogonal space of the fasorial representation. The disclosure is not limited, however, to the present example. The frequency information of the signal is implicit in the representation, and is given by the frequency of the reference signal. For example, referring to Figure 1, and assuming that the real axis corresponds to a reference signal of cos (ωt), the phasor<figref>image14</figref>it would translate into the function r (t) = R (t) cos (ωt + ϕ (t)), in which <figref>image14</figref>is the magnitude of <figref>image14</figref>. 15 Referring again to Figure 1, it is noted that the phasor can decompose into a phasor of part<figref>image14</figref> real <figref>image14</figref>and a fasor of imaginary part <figref>image14</figref>. People say that<figref>image14</figref>and <figref>image14</figref>they are the phasor components of quadrature and in phase of <figref>image14</figref>with respect to the reference signal. It is further noted that the signals that correspond to<figref>image14</figref>and <figref>image14</figref> they are related to r (t) as I (t) = R (t) · cos (ϕ (t)) and Q (t) = R (t) · sen (ϕ (t)), respectively. In the time domain, the signal r (t) can also be written in terms of its quadrature components and in phase as follows:<figref>image15</figref> Note that, in the example of Figure 1, R (t) is illustrated at a particular instant of time. 2.2) Time-Variable Complex Envelope Signals Figure 2 illustrates a fasorial representation of a r (t) signal in two different moments of time t1 and t2. It is noted that both the magnitude of the phasor, which represents the magnitude of the signal envelope, and its relative phase shift, vary from instant t1 to instant t2. In Figure 2, this is illustrated by the variable magnitude of the phasors. <figref>image14</figref>1 and <figref>image14</figref>two and their corresponding phase shift angles ϕ1 and ϕ2. The signal r (t), therefore, is a complex envelope signal that varies over time. It is further noted, from Figure 2, that the real and imaginary fasorial components of the signal r (t) 30 are also variable in time in terms of their amplitude. Therefore, their corresponding time domain signals also have time-varying envelopes. Figures 3A-3C illustrate an exemplary modulation to generate a time-bound complex envelope signal. Figure 3A illustrates a view of a signal m (t). Figure 3B illustrates a view of a portion of a carrier signal c (t). Figure 3C illustrates a signal r (t) that results from the multiplication of the signals m (t) and c (t). In the example of Figure 3A, the signal m (t) is a signal of variable magnitude over time. In addition, m (t) experiences a zero crossing. The carrier signal c (t), in the example of Figure 3B, oscillates at some carrier frequency, typically higher than that of the signal m (t). From Figure 3C, it can be seen that the resulting signal r (t) has a time-varying envelope. In addition, it is observed, from Figure 3C, that r (t) undergoes a phase inversion at the moment in which the modulation signal m (t) passes through zero. Having both the phase and the envelope not constant, it is said that r (t) is a complex envelope signal that varies over time. 2.3) Constant Envelope Decomposition of Time-Variable Envelope Signals Any phase phasor and time-varying phasor can be obtained by adding two or more constant magnitude phasors that have appropriately specified phase shifts in 45 relationship with a reference phasor.<figref>image16</figref> Figure 3D illustrates a view of a time-varying phase and envelope signal by way of example S (t). For ease of illustration, it is assumed that the signal S (t) is a sinusoidal signal having a maximum envelope magnitude A. The 3D figure also shows an example of how the signal S (t) can be obtained, at any time , by adding two constant envelope signals S1 (t) and S2 (t). In general, 5 S1 (t) = A1sen (ωt + ϕ1 (t)) and S1 (t) = A2sen (ωt + ϕ2 (t)). For illustration purposes, three views are provided in Figure 3D that illustrate how, by appropriately phasing the signals S1 (t) and S2 (t) in relation to S (t), the signals S1 (t) and S2 (t) can be added in such a way that S (t) = K (S1 (t) + S2 (t)) in which K is a constant. In other words, the signal S (t) can be broken down, at any moment of time, into two or more signals. From the 3D figure, through the period 10 T1, both S1 (t) and S2 (t) are in phase in relation to the signal S (t) and, therefore, total the maximum envelope magnitude A of the signal S (t). Through period T3, however, the signals S1 (t) and S2 (t) are 180 degrees out of phase with respect to each other and, therefore, totalize a minimum envelope magnitude of the signal S (t). The example in Figure 3D illustrates the case of sinusoidal signals. A person skilled in the art, however, will understand that any time-varying envelope, which modulates a carrier signal that can be represented by a Fourier series or a Fourier transform, can similarly decompose into two or more signals of substantially constant envelope. Therefore, by controlling the phase of a plurality of substantially constant envelope signals, any complex time-varying envelope signal can be generated. 20 3. Vector Power Amplification Procedures and Systems Exemplary vector power amplification procedures and systems may be based on the ability to decompose any time-varying envelope signal into two or more substantially constant envelope constituent signals or to receive or generate such constituent signals, amplify the constituent signals and then sum the amplified signals to generate an amplified version of the complex envelope signal that varies over time. In sections 3.1-3.3, embodiments of vector power amplification (VPA) of the present invention are provided, including 4-branch and 2-branch embodiments. In the description, each embodiment of VPA is first presented conceptually using a mathematical calculation of the underlying concepts of the embodiment. An embodiment of an operation procedure of the VPA embodiment is presented below, followed by various system level embodiments of the VPA embodiment. Section 3.4 presents several embodiments of control modules in accordance with the embodiments of the present invention. The control modules according to the embodiments of the present invention can be used to enable certain VPA embodiments of the present invention. In some embodiments, the control modules are intermediates between an input phase of the VPA embodiment and a subsequent vector modulation phase of the VPA embodiment. Section 3.5 describes some output phase embodiments of VPA in accordance with the embodiments of the present invention. The output phase embodiments are directed to generate the output signal of an embodiment of VPA. Section 3.6 is directed to harmonic control in accordance with the embodiments of the present invention. The harmonic control can be implemented in certain embodiments of the present invention to manipulate the real and imaginary power in the harmonics of the VPA embodiment, thereby increasing the power present in the fundamental frequency at the output. Section 3.7 is directed to power control in accordance with the embodiments of the present invention. The power control can be implemented in certain embodiments of the present invention in order to satisfy the power level requirements of the applications in which the VPA embodiments of the present invention can be employed. 3.1) 4-Branch Cartesian Vector Power Amplifier In accordance with an example of the present invention which is referred to herein as VPA of 4 Cartesian Branches for ease of illustration and not as a limitation, a complex envelope variable signal in the Time 50 decomposes into 4 substantially constant envelope constituent signals. The constituent signals are amplified equally or substantially equally individually and then added to construct an amplified version of the complex envelope signal variable in the original time. It is noted that 4 branches are used in the present example for purposes of illustration, and not limitation. The scope of the disclosure covers the use of other numbers of branches, and the implementation of such variations will be apparent to those skilled in the art based on the teachings contained herein. <figref>image17</figref> In one example, a time-bound complex envelope signal is first broken down into its quadrature and phase vector components. In a fasorial representation, the quadrature and phase vector components correspond to the real and imaginary part phasors of the signal, respectively. 5 As described above, the magnitudes of the quadrature and phase vector components of a signal vary proportionally to the magnitude of the signal and, therefore, are non-constant envelope when the signal is a signal. of time-varying envelope. Therefore, the 4-Branch VPA example further decomposes each of the quadrature and phase vector components of the signal into four substantially constant envelope components, two for the phase signal components and two for the quadrature components. This concept is illustrated in Figure 4 using a fasorial signal representation. In the example in Figure 4, the phasors<figref>image14</figref>1 and <figref>image14</figref>two they correspond to the real part phasors of a complex envelope variable signal in the exemplary time in two instants of time t1 and t2, respectively. It is observed that the fasores<figref>image14</figref>1 and <figref>image14</figref>two They have different magnitudes. Referring again to figure 4, at time t1, the fasor<figref>image14</figref>1 can be obtained by adding the 15 upper and lower phasors <figref>image14</figref>and <figref>image14</figref>. Similarly, at time t2, the fasor<figref>image14</figref>two can be obtained by adding the upper and lower fasors <figref>image14</figref>and <figref>image14</figref>. It is noted that the phasors<figref>image14</figref>and <figref>image14</figref><figref>image14</figref>they have an equal or substantially equal magnitude. Similarly, the fasores e<figref>image14</figref>They have a substantially equal magnitude. Accordingly, the real part phasor of the time-varying envelope signal can be obtained at any instant of time by the sum of at least two substantially constant envelope components 20. Phase shifts of the phasors<figref>image14</figref>and <figref>image14</figref>regarding <figref>image14</figref>1, as well as phase shifts of the phasors <figref>image14</figref>and <figref>image14</figref>regarding <figref>image14</figref>2, adjust according to the desired magnitude of the phasors <figref>image14</figref>1 and <figref>image14</figref>2, respectively. In one case, when the upper and lower phasors are selected to have an equal magnitude, the upper and lower phasors move symmetrically in phase relative to the phasor. This is illustrated in the example of Figure 4, and corresponds to and all having an equal magnitude. In a second case, the phase displacement of the upper and lower phasors are displaced, substantially symmetrically, in phase relative to the phasor. Based on the description herein, any person skilled in the art will understand that the magnitude and phase shift of the upper and lower phasors do not have to be exactly the same in terms of their value. 30 As an example, it can also be verified that, for the case illustrated in Figure 4, the displacements of <figref>image18</figref> relative phase, which are illustrated as <figref>image14</figref>and <figref>image14</figref>in figure 4, they are related to the magnitudes of the normalized phasors <figref>image14</figref>1 and <figref>image14</figref>two as follows: in which <figref>image14</figref>1 and <figref>image14</figref>two represent the normalized magnitudes of the phasors <figref>image14</figref>1 and <figref>image14</figref>2, respectively, and in which the domains of I1 and I2 are appropriately restricted according to the domain through which equation (2) and (3) are valid. It is noted that equations (2) and (3) are a representation to relate the<figref>image19</figref><figref>image20</figref> 5 relative phase shifts with normalized magnitudes. Other solutions, equivalent representations, and / or simplified representations of equations (2) and (3) can also be used. Query tables that relate relative phase shifts to standardized quantities can also be used. The concept described above may be applied similarly to the imaginary phasor or the quadrature component part of a signal r (t) as illustrated in Figure 4. Therefore, at any time <figref>image14</figref> of time t, the imaginary phasor part of the signal r (t) can be obtained by adding the upper and lower fasorial components <figref>image14</figref><figref>image14</figref>U and <figref>image14</figref>L of a substantially equal and constant magnitude. In this example,<figref>image14</figref><figref>image14</figref>U and L move symmetrically in phase in relation to an angle adjusted according to the magnitude of <figref>image14</figref>in the instant t. The relationships of<figref>image14</figref>U and <figref>image14</figref>L with the desired fasor <figref>image14</figref>they are related as defined in equations 2 and 3 by substitution by Q1 and Q2 of I1 and I2, respectively. From the previous analysis it follows that, in a fasorial representation, any fasor<figref>image14</figref>of a variable magnitude and phase can be constructed by adding four fasorial components of substantially constant magnitude: <figref>image21</figref> 20 in which IU, IL, QU, and QL represent the magnitudes of the phasors <figref>image14</figref>OR,<figref>image14</figref>L, <figref>image14</figref>U and <figref>image14</figref>L, respectively. Correspondingly, in the time domain, a time-bound complex envelope sinusoidal signal r (t) = R (t) cost (ωt + ϕ) is constructed by adding four constant envelope signals as follows:<figref>image22</figref> in which sgn ( <figref>image23</figref>) = ± 1 depending on whether <figref>image14</figref>It is in phase or 180 degrees out of phase with the real positive axis. Similarly, sgn () = ± 1 depending on whether<figref>image14</figref>It is in phase or 180º out of phase with the imaginary axis. <figref>image14</figref>corresponds to the phase shift of <figref>image14</figref>U e <figref>image14</figref>L in relation to the real axis. Similarly,<figref>image14</figref><figref>image14</figref>corresponds to the phase shift of <figref>image14</figref>U and <figref>image14</figref>L in relation to the imaginary axis. <figref>image14</figref>and can be calculated using the equations given in (2) and (3). Equations (5) can be further simplified as:<figref>image24</figref> It can be understood by one skilled in the art that, while representations in the time domain in equations (5) and (6) have been provided for the case of a sine wave form, equivalent representations can be developed for the forms of non-sinusoidal wave using appropriate base functions. In addition, as one skilled in the art would understand based on the teachings herein, the two-dimensional decomposition described above in substantially constant envelope signals can be appropriately extended to give a multidimensional decomposition. Figure 5 is an exemplary block diagram of the 4-Branch Cartesian VPA. An output signal r (t) 578 of a power level, and of desired frequency characteristics, is generated from the quadrature and baseband phase components in accordance with the exemplary 4-Branch Cartesian VPA. <figref>image25</figref> In the example of Figure 5, a frequency generator such as a synthesizer 510 generates a reference signal A * cos (ωt) 511 that has the same frequency as that of the output signal r (t) 578. It can be understood by one skilled in the art that the choice of the reference signal is made in accordance with the desired output signal 5. For example, if the desired frequency of the desired output signal is 2.4 GHz, then the frequency of the reference signal is set to be 2.4 GHz. In this way, a high frequency conversion can be achieved. Referring to Figure 5, one or more phase dividers are used to generate signals 521, 531, 541 and 551 based on the reference signal 511. In the example of Figure 5, this is done using phase dividers 512, 10 514 and 516 and by applying 0 ° phase shifts in each of the phase dividers. One skilled in the art will appreciate, however, that various techniques can be used to generate signals 521, 531, 541 and 551 of reference signal 511. For example, a 1: 4 phase splitter can be used to generate the four replicas 521, 531, 541 and 551 in a single stage or in the example of Figure 5, signal 511 can be directly coupled to signals 521, 531 , 541, 551 Depending on the example, a variety of phase shifts 15 can also be applied to result in the desired signals 521, 531, 541 and 551. Referring again to Figure 5, each of the signals 521, 531, 541 and 551 is provided to a corresponding vector modulator 520, 530, 540 and 550, respectively. The vector modulators 520, 530, 540 and 550, in conjunction with their appropriate input signals, generate four constant envelope constituents of the signal r (t) according to the equations provided in (6). In the example of Figure 5, the 20 vector modulators 520 and 530 generate the components of IU (t) and IL (t), respectively, of the signal r (t). Similarly, vector modulators 540 and 550 generate the components of QU (t) and QL (t), respectively, of the signal r (t). The actual implementation of each of the 520, 530, 540 and 550 vector modulators may vary. It will be understood by one skilled in the art, for example, that there are several techniques for generating the constant envelope constituents according to the equations in (6). In the example of Figure 5, each of the vector modulators 520, 530, 540, 550 includes an input phase divider 522, 532, 542, 552 to phase shift the signals 522, 531, 541, 551. Accordingly, the input phase dividers 522, 532, 542, 552 are used to generate quadrature and phase components or their respective input signals. In each vector modulator 520, 530, 540, 550, the quadrature and phase components are multiplied with the amplitude information. In Figure 5, for example, multiplier 524 multiplies the quadrature component of signal 521 with the quadrature amplitude information IUY of Iu (t). In parallel, multiplier 526 multiplies the phase replica signal with the amplitude information in phase sgn (I) × IUX of IU (t). To generate the constant envelope constituent signals of IU (t) 525 and 527 are added using the 528 phase splitter or alternative sum techniques. The resulting signal 529 corresponds to the IU component (t) of the signal r (t). In a manner similar to what has been described above, the vector modulators 530, 540 and 550, respectively, generate the components of IL (t), QU (t) and QL (t) of the signal r ( t). IL (t), QU (t) and QL (t), respectively, correspond to signals 539, 549 and 559 in Figure 5. 40 In addition, as described above, signals 529, 539 , 549 and 559 are characterized by having substantially equal and constant envelopes. Therefore, when the corresponding signals 529, 539, 549 and 559 are introduced into the corresponding power amplifiers (PA) 562, 564, 566 and 568, the corresponding amplified signals 563, 565, 567 and 569 are substantially constant envelope signals . The power amplifiers 562, 564, 566 and 568 amplify each of the signals 529, 539, 549, 559, 45 respectively. In one example, a substantially equal power amplification is applied to each of signals 529, 539, 549 and 559. In one example, the power amplification level of PAs 562, 564, 566 and 568 is adjusted accordingly with the desired power level of the output signal r (t). Referring again to Figure 5, amplified signals 563 and 565 are summed using adder 572 to generate an amplified version 573 of the components in phase<figref>image14</figref>(t) of the signal r (t). Similarly, the 50 amplified signals 567 and 569 are added using adder 574 to generate an amplified version 575 of the<figref>image14</figref> quadrature component (t) of the signal r (t). The signals 573 and 575 are summed using adder 576, as shown in Figure 5, the resulting signal corresponding to the desired output signal r (t).<figref>image26</figref> It is noted that, in the example of Figure 5, adders 572, 574 and 576 are being used for illustration purposes only. Various techniques can be used to sum the amplified signals 563, 565, 567 and 569. For example, all amplified signals 563, 565, 567 and 569 can be added in one step to result in signal 578. In fact, According to several examples of VPA, it is sufficient that the sum is done after amplification. Certain examples of VPA, as will be described further in the following, use addition techniques with minimal losses such as direct coupling through wire. Alternatively, certain examples of VPA use conventional power combination techniques. In other examples, as will be described further below, the power amplifiers 562, 564, 566 and 568 can be implemented as a power amplifier with multiple inputs and a single output. 10 The operation of the exemplary 4-Cartesian Branches VPA will be further described below with reference to the process flow diagram of Figure 6. The procedure begins in step 610, which includes receiving the baseband representation of the desired output signal. This involves receiving the components in phase (I) and quadrature (Q) of the desired output signal. In another example, this involves receiving the magnitude and phase of the desired output signal. In the example of 4-Branch Cartesian VPA, the I and Q are baseband components 15. In another example, the I and Q are RF components and a reductive conversion is applied to the baseband. Step 620 includes receiving a clock signal set according to a desired output signal frequency of the desired output signal. In the example of Figure 5, step 620 is achieved by receiving the reference signal 511. twenty Step 630 includes the processing of the I component to generate first and second signals that have the output signal frequency. The first and second signals have envelopes of substantially constant and equal magnitude and a sum equal to the component of I. The first and second signals correspond to the constant envelope constituents of IU (t) and IL (t) that are They have described above. In the example of Figure 5, step 630 is achieved by vector modulators 520 and 530, in conjunction with their appropriate input signals. Step 640 includes the processing of the Q component to generate third and fourth signals that have the output signal frequency. The third and fourth signals have envelopes of substantially constant and equal magnitude and a sum equal to the component of Q. The third and fourth signals correspond to the constant envelope constituents of QU (t) and QL (t) which have been described above. In the example of Figure 5, step 630 is achieved by means of vector modulators 540 and 550, in conjunction with their appropriate input signals. Step 650 includes amplifying each of the first, second, third and fourth signals individually, and adding the amplified signals to generate the desired output signal. In one example, the amplification of the first, second, third and fourth signals is substantially equal and according to a desired power level of the desired output signal. In the example of Figure 5, step 650 is achieved by the power amplifiers 562, 564, 566 and 568 that amplify the respective signals 529, 539, 549 and 559, and by the summers 572, 574 and 576 which sum the amplified signals 563, 565, 567 and 569 to generate the output signal 578. Figure 7A is a block diagram illustrating an exemplary embodiment of a vector power amplifier 700 that implements the process flow diagram 600 of Figure 6. In the example of Figure 7A, the optional components are illustrated with Discontinue lines. In other embodiments, additional components may be optional. The vector power amplifier 700 includes a phase branch (I) 703 and a quadrature branch (Q) 705. Each of the branches of I and Q further comprises a first branch and a second branch. The information signal in phase (I) 702 is received by a data transfer function module of I 710. In one embodiment, the information signal of I 702 includes a digital baseband signal. In one embodiment, the data transfer function module of I 710 samples the information signal of I 702 according to a sampling clock 706. In another embodiment, the I 702 information signal includes an analog baseband signal, which is converted to digital using an analog to digital converter (ADC) (not shown in Figure 7A) before being introduced into the I 710 data transfer function module. In another embodiment, the I 702 information signal includes an analogue baseband signal that is input analogically into the I 710 data transfer function module, which also includes analog circuitry. In another embodiment, the I 702 information signal includes an RF signal to which a reductive conversion is applied to the baseband before being introduced into the I 710 data transfer function module using any of the embodiments that have been described above. 55 The data transfer function module of I 710 processes the information signal of I 702, and determines the quadrature and phase amplitude information of at least two constant envelope constituent signals of the information signal of I 702 As described above with reference to Figure 5, the amplitude information of quadrature and phase vector modulator corresponds to sgn (I) × IUX and IUY, respectively. The operation of the I 710 data transfer function module is further described in the following in section 3.4. <figref>image27</figref> The data transfer function module of I 710 issues the information signals 722 and 724 that are used to control the quadrature and phase amplitude components of the vector modulators 760 and 762. In one embodiment, the signals 722 and 724 are digital signals. Accordingly, each of the signals 722 and 724 is respectively supplied to a corresponding digital-to-analog converter (DAC) 730 and 732. The resolution and sampling rate of DAC 730 and 732 is selected to achieve the desired I component of output signal 782. DAC 730 and 732 are controlled by DAC clock signals 723 and 725, respectively. The clock signals of DAC 723 and 725 can be calculated from the same clock signal or can be independent. In another embodiment, signals 722 and 724 are analog signals, and DAC 730 and 732 are not required. In the exemplary embodiment of Figure 7A, DAC 730 and 732 convert the digital information signals 722 and 724 into the corresponding analog signals, and introduce these analog signals into the optional interpolation filters 731 and 733, respectively. The interpolation filters 731 and 733, which also serve as filters 15, form the outputs of the DACs to produce the desired output waveform. Interpolation filters 731 and 733 generate signals 740 and 742, respectively. Signal 741 represents the inverse of signal 740. Signals 740-742 are introduced into vector modulators 760 and 762. Vector modulators 760 and 762 multiply signals 740-742 with clock signals shifted in phase as appropriate. to generate a constant envelope constituents of the 20 I 702 information signal. The clock signals are calculated from a channel clock signal 708 which has a rate according to a desired output signal frequency. A plurality of phase dividers, such as 750 and 752, for example, and the phasors associated with the vector modulator multipliers, can be used to generate the phase shifted clock signals in the appropriate manner. In the embodiment of Figure 7A, for example, the vector modulator 760 modulates a channel clock signal 25 displaced 90 ° with the quadrature amplitude information signal 740. In parallel, the vector modulator 760 modulates a channel clock signal in phase with the amplitude information signal in phase 742. The vector modulator 760 combines the two modulated signals to generate a first modulated constant envelope constituent 761 of the information signal of I 702. Similarly, the vector modulator 762 generates a second modulated constant envelope constituent 763 of the information signal of I 702, using signals 741 and 30742. Signals 761 and 763 correspond, respectively, to the constant envelope components of IU (t) and IL (t) described with reference to Figure 5. In parallel and in a similar way, the Q branch of the vector power amplifier 700 generates at least two constant envelope constituent signals from the quadrature information signal (Q) 704. In the embodiment of Figure 7A, by For example, vector modulator 764 generates a first constituent of constant envelope 765 of the information signal of Q 704, using signals 744 and 746. Similarly, the vector modulator 766 generates a second constant envelope constituent 767 of the information signal of Q 704, using signals 745 and 746. As described above with respect to Figure 5, the signals of Constituent 761, 763, 765 and 767 have substantially equal and constant envelopes. In the exemplary embodiment of Figure 7A, signals 40 761, 763, 765 and 767 are introduced, respectively, into the corresponding power amplifiers (PA) 770, 772, 774 and 776. The PA 770, 772, 774 and 776 can be linear or non-linear power amplifiers. In one embodiment, PA 770, 772, 774 and 776 include switching power amplifiers. Circuitry 714 and 716 (referred to herein as "autopolarization circuitry" for ease of reference, and not as limitation) and in the present embodiment, control the polarization of PAs 45 770, 772, 774 and 776 according to the information signals of I and Q 702 and 704. In the embodiment of Figure 7A, the autopolarization circuitry 714 and 716 respectively provide the polarization signals 715 and 717 to the PA 770, 772 and the PA 774, 776. The autopolarization circuitry 714 and 716 are further described in what follows in section 3.5. The embodiments of PA 770, 772, 774 and 776 are also discussed in the following in section 3.5. fifty In one embodiment, PA 770, 772, 774 and 776 apply substantially equal power amplification to the substantially constant envelope signals 761, 763, 765 and 767. In other embodiments, the PA excitation circuits are additionally employed to provide additional power amplification. In the embodiment of Figure 7A, the excitation circuits of PA 794, 795, 796 and 797 are optionally added between the respective vector modulators 760, 762, 764 766 and the respective PA 770, 772, 774 and 776, in every 55 branch of the vector power amplifier 700. The outputs of the PA 770, 772, 774 and 776 are coupled together to generate the output signal 782 of the vector power amplifier 700. In one embodiment, the outputs of the PA 770, 772, 774 and 776 are directly coupled <figref>image28</figref> each other using a thread. Direct coupling in this way means that there is no resistive, inductive or capacitive insulation, or there is a minimum one, between the outputs of the PA 770, 772, 774 and 776. In other words, the outputs of the PA 770, 772, 774 and 776 are coupled together without intermediate components. Alternatively, in one embodiment, the outputs of the PAs 770, 772, 774 and 776 are indirectly coupled to each other through about 5 inductances and / or capacities that result in low or minimum impedance connections, and / or connections that result in minimal insulation and minimal power loss. Alternatively, the outputs of PA 770, 772, 774 and 776 are coupled using well known combination techniques, such as Wilkinson circuits, hybrid circuits, transformers, or known active combiner circuits. In one embodiment, PA 770, 772, 774 and 776 provide a combination of power and amplification integrated in a single operation. In one embodiment, one or more of the power amplifiers and / or the excitation circuits described herein are implemented using multi-input and single-output power amplification techniques, examples of which are shown. in figures 7B and 51A -H. The output signal 782 includes the characteristics of I and Q of the information signals of I and Q 702 and 704. In addition, the output signal 782 is of the same frequency as that of its constituents and, therefore, is of the output frequency with high conversion. In embodiments of the vector power amplifier 700, a polarization impedance 780 is coupled between the output of the vector amplifier 700 and a power supply. Output phase embodiments in accordance with the power amplification procedures and systems disclosed herein will be further described in the following in section 3.5. In other embodiments of the vector power amplifier 700, process detectors are used to compensate for any process variation in the amplifier circuitry. In the embodiment of Figure 7A, for example, process detectors 791-793 are optionally added to monitor variations in the excitation circuits of PA 794-797 and phase divider 750. In additional embodiments, the 799 frequency compensation circuitry can be used to compensate for frequency variations. Figure 7B is a block diagram illustrating another exemplary embodiment of the vector power amplifier 25 700. The optional components are illustrated with broken lines, although other embodiments may have more or less optional components. The embodiment illustrates an implementation of multiple inputs and a single output (MISO) of the amplifier of Figure 7A. In the embodiment of Figure 7B, the constant envelope signals 761, 763, 765 and 767, which are emitted from the vector modulators 760, 762, 764 and 766, are introduced into the PAs of MISO 784 and 786. The PAs of 30 MISO 784 and 786 are two-input and single-output power amplifiers. In one embodiment, the PAs of MISO 784 and 786 include elements 770, 772, 774, 776, 794-797 as shown in the embodiment of Figure 7A or a functional equivalence thereof. In another embodiment, the MISO PAs 784 and 786 may include other elements, such as optional pre-excitation circuits and an optional process detection circuitry. In addition, MISO PAs 784 and 786 are not limited to being two-input PAs as shown in Figure 7B. In other embodiments, as will be described further below with reference to Figures 51A-H, PAs 784 and 786 may have any number of inputs and outputs. Figure 8A is a block diagram illustrating another exemplary embodiment 800A of a vector power amplifier according to the 4-Branch Cartesian VPA procedure shown in Figure 6. The optional components are illustrated with broken lines, a Although other embodiments may have 40 or so optional components. In the embodiment of Figure 8A, a DAC 830 of sufficient resolution and sampling rate replaces DAC 730, 732, 734 and 736 of the embodiment of Figure 7A. The sampling rate of DAC 830 is controlled by a clock signal of DAC 826. The DAC 830 receives quadrature and phase 810 and 820 information signals from the data transfer function module of I 710 and the data transfer function module of Q 712, respectively, as described in the foregoing. In one embodiment, an input selector 822 selects the order of signals 810 and 820 that are input into DAC 830. The DAC 830 can emit a single analog signal at a time. In one embodiment, a sampling and retention architecture can be used to ensure proper signal synchronism for the four branches of the amplifier, as shown in Figure 8A. The DAC 830 sequentially outputs analog signals 832, 834, 836, 838 to a first set of sampling and retention circuits 842, 844, 846 and 848. In one embodiment, DAC 830 is timed at a rate sufficient to emulate the operation of DAC 730, 732, 734 and 736 of the embodiment of Figure 7A. An output selector 824 determines which of the output signals 832, 834, 836 and 838 should be selected for the output. 55 The DAC clock signal 826 of the DAC 830, the output selector signal 824, the input selector 822 and the sampling and retention clocks 840A -D and 850 are controlled by a control module that can be independent or integrated in transfer function modules 710 and / or 712. <figref>image29</figref> In one embodiment, the sampling and retention (S / H) circuits 842, 844, 846 and 848 sample and retain the analog values ​​received from the DAC 830 in accordance with an 840A-D clock signal. Sampling and retention circuits 852, 854, 856 and 858 sample and retain analog values ​​from sampling and retention circuits 842, 844, 846 and 848 respectively. In turn, sampling and retention circuits 852, 854, 5 856 and 858 retain the analog values ​​received, and simultaneously release the values ​​for vector modulators 760, 762, 764 and 766 according to a common clock signal 850. In another embodiment, sampling and retention circuits 852, 854, 856 and 858 release the values ​​for optional interpolation filters 731, 733, 735 and 737 which are also anti-lap filters. In one embodiment, a common clock signal 850 is used in order to ensure that the outputs of S / H 852, 854, 856 and 858 are aligned in time. 10 Other aspects of the vector power amplifier 800A correspond substantially to those described above with respect to the vector power amplifier 700. Figure 8B is a block diagram illustrating another exemplary embodiment 800B of a vector power amplifier according to the 4-Branch Cartesian VPA procedure shown in Figure 6. The optional components are illustrated with broken lines, to Although other embodiments may have 15 or so optional components. Embodiment 800B illustrates another single DAC implementation of the vector power amplifier. However, in contrast to the embodiment of Figure 8A, the sampling and retention architecture includes a single set of sampling and retention (S / H) circuits. As shown in Figure 8B, S / H 842, 844, 846 and 848 receive analog values ​​from DAC 830, which is illustrated as signals 832, 834, 836 and 838. Each of the 20 circuits of S / H 842, 844, 846 and 848 release their received value according to a different 840A-D watch, as shown. The time difference between the analog samples used to generate the signals 740, 741, 742, 744, 745 and 746 can be compensated in the transfer functions 710 and 712. According to the embodiment of Figure 8B, a level of S / H circuitry can be eliminated in relation to the embodiment of Figure 8A, thereby reducing the size and complexity of the amplifier. 25 Other aspects of the 800B vector power amplifier correspond substantially to those described above with respect to the 700 and 800A vector power amplifiers. Figure 8C is a block diagram illustrating another exemplary embodiment 800C of the vector power amplifier 700. The optional components are illustrated with broken lines, although other embodiments may have more or less optional components. The embodiment of Figure 8C illustrates an implementation of multiple inputs and a single output (MISO) of the amplifier of Figure 8A. In the embodiment of Figure 8C, the constant envelope signals 761, 763, 765 and 767, which are emitted from the vector modulators 760, 762, 764 and 766, are introduced into the PAs of MISO 860 and 862. PA of MISO 860 and 862 are two-input and single-output power amplifiers. In one embodiment, the PAs of MISO 860 and 862 include elements 770, 772, 774, 776, 794-797 as shown in the embodiment of Figure 7A or a functional equivalence thereof. In another embodiment, the MISO PAs 860 and 862 may include other elements, such as optional pre-excitation circuits and an optional process detection circuitry. In another embodiment, the MISO PAs 860 and 862 may include other elements, such as pre-excitation circuits, which are not shown in the embodiment of Figure 7A. In addition, the MISO 860 and 862 PAs are not limited to being two-input PAs as shown in Figure 8C. In other embodiments, as will be described further in 40 below with reference to Figures 51A-H, PA 860 and 862 may have any number of inputs and outputs. Other aspects of the 800C vector power amplifier correspond substantially to those described above with respect to the 700 and 800A vector power amplifiers. Figure 8D is a block diagram illustrating another exemplary embodiment 800D of vector power amplifier 455. The optional components are illustrated with broken lines, although other embodiments may have more or less optional components. The embodiment of Figure 8D illustrates an implementation of multiple inputs and a single output (MISO) of the amplifier of Figure 8B. In the embodiment of Figure 8D, the constant envelope signals 761, 763, 765 and 767, which are emitted from the vector modulators 760, 762, 764 and 766, are introduced into the PAs of MISO 870 and 872. PA of MISO 870 and 872 are about 50 power amplifiers with two inputs and a single output. In one embodiment, the PAs of MISO 870 and 872 include elements 770, 772, 774, 776, 794-797 as shown in the embodiment of Figure 7A or a functional equivalence thereof. In another embodiment, the MISO 870 and 872 APs may include other elements, such as optional pre-excitation circuits and an optional process detection circuitry. In another embodiment, the MISO PAs 870 and 872 may include other elements, such as pre-excitation circuits, which are not shown in the embodiment of Figure 7A. In addition, the MISO 870 and 872 PAs are not limited to being two-input PAs as shown in Figure 8D. In other embodiments, as will be described further in the following with reference to Figures 51A-H, PAs 870 and 872 may have any number of inputs and outputs.<figref>image30</figref> Other aspects of the 800D vector power amplifier correspond substantially to those described above with respect to the 700 and 800B vector power amplifiers. 3.2) Vector 2-Cartesian -Polar -Cartesian -Polar Vector Power Amplifier An exemplary 2-Cartesian -Polar -Cartesian -Polar VPA (CPCP) VPA will be described below. 5 According to the 2-Branch Cartesian-Polar -Cartesian -Polar (CPCP) VPA procedure, a time-bound complex envelope signal is broken down into 2 substantially constant envelope constituent signals. The constituent signals are amplified individually and then added to construct an amplified version of the complex envelope signal variable in the original time. In addition, the phase angle of the time-bound complex envelope signal is determined and the sum 10 resulting from the constituent signals is shifted in phase to the appropriate angle. In an example of the CPPA 2-Branch VPA procedure, a magnitude and a phase angle of a complex envelope signal variable in time are calculated from the quadrature and phase components of a signal. Given the magnitude information, two substantially constant envelope constituents are calculated from a standardized version of the variable envelope signal in the desired time, in which the normalization includes a specific manipulation of the phase and / or amplitude implementation . The two substantially constant envelope constituents then phase in an appropriate angle in relation to the phase shift of the variable envelope signal in the desired time. The substantially constant envelope constituents are then amplified individually substantially equally, and added together to generate an amplified version of the variable envelope signal in the original desired time. Figures 9A and 9B conceptually illustrate the VPA of 2 exemplary CPCP Branches using a phasor signal representation. In figure 9A, the fasor<figref>image14</figref>input represents a complex envelope input signal variable at time r (t). At any instant of time,<figref>image31</figref>input reflects a magnitude and phase shift angle of the signal r (t). In the example shown in Figure 9A,<figref>image14</figref>input is characterized by a magnitude R and a phase shift angle 25 θ. As described above, the phase shift angle is measured in relation to a reference signal. Referring to Figure 9A,<figref>image14</figref>represents the relative amplitude component of <figref>image14</figref>input that is generated by <figref>image14</figref>' and <figref>image14</figref>'. Referring again to Figure 9A, it is observed that, at any time,<figref>image14</figref><figref>image14</figref><figref>image14</figref><figref>image14</figref><figref>image14</figref>30 can be obtained by the sum of an upper fasor and a lower fasor. In addition, and can be maintained to have a substantially constant magnitude. The fasores<figref>image14</figref>and <figref>image14</figref>therefore represent two substantially constant envelope signals. In this way r '(t) can be obtained, at any time,<figref>image14</figref> by the sum of two substantially constant envelope signals that correspond to the phasors and. <figref>image14</figref> 35 Phase shifts of the phasors <figref>image14</figref>and <figref>image14</figref>regarding <figref>image14</figref>are adjusted according to the desired magnitude R of <figref>image14</figref>. In the simplest case, when the upper and lower phasors<figref>image14</figref>and <figref>image14</figref>are selected to have an equal magnitude, the upper and lower phasors <figref>image14</figref>and <figref>image14</figref>they move, substantially symmetrically, in phase in relation to <figref>image14</figref>. This is illustrated in the example of Figure 9A. It is noted that the expressions and phrases that indicate or suggest an orientation, such as but not limited to "upper and lower" are used herein for ease of reference and are not functionally or structurally limiting. It can be verified that, for the case illustrated in Figure 9A, the phase shift of<figref>image14</figref>and <figref>image14</figref>regarding <figref>image14</figref>which is illustrated as the angle <figref>image14</figref>in figure 9A, it is related to the magnitude of <figref>image14</figref>as follows: <figref>image32</figref><figref>image33</figref> in which R represents a normalized magnitude of the phasor Equation (7) can be further reduced to <figref>image34</figref><figref>image33</figref> in which R represents a standardized magnitude of the phasors Alternatively, any substantially equivalent mathematical equation, or other substantially equivalent mathematical techniques such as query tables can be used. From the previous analysis it follows that, in a fasorial representation, any fasor<figref>image14</figref>of a variable magnitude and phase can be constructed by adding two fasorial components of constant magnitude: <figref>image35</figref> Correspondingly, in the time domain, a sinusoidal signal of time-varying envelope r '(t) = R (t) × cos (ωt) is constructed by adding two constant envelope signals as follows: <figref>image36</figref> in which A is a constant and <figref>image14</figref>It is as shown in equation (7). 15 From Figure 9A, it can also be verified that equations (9) can be rewritten as:<figref>image37</figref> in which C indicates the real part component of the phasors <figref>image14</figref>and <figref>image14</figref>and is equal to A × cos ( <figref>image14</figref>). It is noted that<figref>image14</figref> C is a common component of <figref>image14</figref>and<figref>image14</figref>. α and β indicate the components of the imaginary part of the phasors<figref>image14</figref>and ' <figref>image38</figref> respectively. α = β = A × sen (<figref>image14</figref>). Therefore, from equations (12), r '(t) = 2C × cos (ωt) = 2A × cos (<figref>image14</figref>) × cos (ωt). As one skilled in the art would understand based on the teachings herein, other equivalent and / or simplified representations of the above representations of the amounts A, B and C, including query tables, for example, may also be used. It is noted that<figref>image14</figref>input shifts θ degrees relative to <figref>image14</figref>'. Therefore, using equations (8), it can be deduced that:<figref>image39</figref> Equations (11) imply that a representation of <figref>image14</figref>entry can be obtained by adding the phasors <figref>image14</figref>' and <figref>image14</figref>', which have been described above, displaced θ degrees. In addition, an amplified output version 10 can be obtained,<figref>image14</figref>output of <figref>image14</figref>input by substantially equal separate amplification of each of the shifted versions θ degrees of the phasors <figref>image14</figref>and <figref>image14</figref>, and by adding them. Figure 9B illustrates this concept. In figure 9B, the phasors<figref>image14</figref><figref>image14</figref><figref>image14</figref>and <figref>image14</figref>they represent displaced versions <figref>image14</figref><figref>image14</figref>θ degrees and amplified <figref>image14</figref>of the fasors' and. It is noted that, because they are fasors of constant magnitude, and they are also fasors of constant magnitude. The fasores<figref>image14</figref>and <figref>image14</figref>total, as shown in Figure 9B, the 15 fasor <figref>image14</figref>output which is a power amplified version of the input signal <figref>image14</figref>entry. Equivalently, in the time domain, it can be shown that:<figref>image40</figref> in which rsalida (t) corresponds to the signal in the time domain that is represented by the phasor <figref>image14</figref>output ', U (t) and L (t) correspond to the signals in the time domain that are represented by the phasors <figref>image14</figref>and 20 <figref>image14</figref>, and K is the power amplification factor. One skilled in the art will appreciate that, while representations in the time domain in equations (9) and (10) have been provided for the case of a sine waveform, equivalent representations can be developed for non-waveforms. sinusoidal using appropriate base functions. 25 Figure 10 is a block diagram that conceptually illustrates an example 1000 of the 2-Branch CPCP VPA. An output signal r (t) of a power level, and of desired frequency characteristics, is generated from the quadrature components and in phase according to the exemplary 2-Branch CPCP VPA. In the example of Figure 10, a clock signal 1010 represents a reference signal to generate the output signal r (t). The clock signal 1010 is of the same frequency as that of the desired output signal r (t). 30 Referring to FIG. 10, an Ifase clock 1012 signal and a Q clock phase 1014 signal represent analog values ​​in amplitude that are multiplied by the quadrature and phase components of the Clock 1010 signal and are calculated from the signals I and baseband Q. Referring again to Fig. 10, the clock signal 1010 is multiplied with the Ifase clock signal 1012. In parallel, a 90 degree offset version of the clock signal 1010 is multiplied with the Qfase_reclock signal 1014. 35 The two multiplied signals are combined to generate the clock signal 1016. The clock signal 1016 is of the same frequency as the clock signal 1010. In addition, the clock signal 1016 is characterized by a phase shift angle according to the ratio of Q (t) and I (t). The magnitude of the 1016 clock signal is such that<figref>image41</figref> R2watch = I2phase_refix + Q2fase_ref. Accordingly, the clock signal 1016 represents a substantially constant envelope signal having the phase characteristics of the desired output signal r (t). Referring again to Figure 10, the clock signal 1016 is introduced, in parallel, in two vector modulators 1060 and 1062. Vector modulators 1060 and 1062 generate the substantially constant envelope constituents 5 of U (t) and L (t), respectively, of the desired output signal r (t) as described in (12). In the 1060 vector modulator, a 1020 phase clock signal, which is multiplied with the 1028 Common signal, is combined with a 90 degree offset version 1018 of the clock signal, which is multiplied with the first 1026 signal. In parallel, in the vector modulator 1062, a phase clock signal 1022, which is multiplied with the common signal 1028, is combined with a 90 degree offset version 1024 of the clock signal, which is multiplied 10 with the second signal 1030 The Common signal 1028, the first signal 1026 and the second signal 1030 correspond, respectively, to the real part C and the imaginary parts α and β described in equation (12). The output signals 1040 and 1042 of the respective vector modulators 1060 and 1062 correspond, respectively, to the constant envelope constituents of U (t) and L (t) of the input signal r (t). As described above, signals 1040 and 1042 are characterized by having substantially equal and constant envelopes 15. Therefore, when signals 1040 and 1042 are introduced into the corresponding power amplifiers (PA) 1044 and 1046, the corresponding amplified signals 1048 and 1050 are substantially constant envelope signals. Power amplifiers 1044 and 1046 apply a power amplification substantially equal to signals 1040 and 1042, respectively. In one example, the power amplification level of the PA 1044 and 1046 20 is adjusted according to the desired power level of the output signal r (t). In addition, amplified signals 1048 and 1050 are in phase relative to each other. Therefore, when added together, as shown in Figure 10, the resulting signal 1052 corresponds to the desired output signal r (t). Figure 10A is another example 1000A of the CPPA 2-Branch VPA. Example 1000A represents an implementation of Multiple Inputs and a Single Output (MISO) of Example 1000 of Figure 10. 25 In Example 1000A, the constant envelope signals 1040 and 1042, which are emitted from vector modulators 1060 and 1062, are introduced into the MISO 1054 PA. The MISO 1054 PA is a two-input and single-output power amplifier. In one example, the MISO 1054 PA may include several elements, such as pre-excitation circuits, excitation circuits, power amplifiers and process detectors (not shown in Figure 10A), for example. In addition, the MISO 1054 PA is not limited to being a two-input PA such as shown in Figure 10A. In other examples, as will be described further in the following with reference to Figures 51A-H, the PA 1054 may have any number of inputs. The operation of the exemplary 2-Branch CPCP VPA is depicted in the process flow diagram 1100 of Figure 11. The procedure begins at step 1110, which includes receiving a baseband representation of the desired output signal 35. In one example, this involves receiving the phase (I) and quadrature (Q) components of the desired output signal. In another example, this involves receiving the magnitude and phase of the desired output signal. Step 1120 includes receiving a clock signal set in accordance with a desired output signal frequency of the desired output signal. In the example of figure 10, step 1120 is achieved by receiving the clock signal 1010. 40 Step 1130 includes the processing of the clock signal to generate a normalized clock signal having a phase shift angle according to the received I and Q components. In one example, the normalized clock signal is a constant envelope signal that has a phase shift angle according to a ratio of the components of I and Q. The phase shift angle of the standardized clock is relative to the original clock signal. In the example of Fig. 10, step 1130 is achieved by multiplying the quadrature and phase components of the clock signal 1010 with the signals of Ifase_reloj 1012 and Qfase_reloj 1014 and then, by the sum of the multiplied signal to generate the 1016 clock signal. Step 1140 includes the processing of the components of I and Q to generate the amplitude information that is required to produce first and second substantially constant envelope constituent signals. Step 1150 includes the processing of the amplitude information of step 1140 and the standard clock signal Rreloj to generate the first and second constant envelope constituents of the desired output signal. In one example, step 1150 involves the phase shift of the first and second constant envelope constituents of the desired output signal the phase shift angle of the standardized clock signal 55. In the example of figure 10, step 1150 is achieved by means of vector modulators 1060 and 1062 that modulate the clock signal 1016 with the first signal 1026, the second signal 1030 and the common signal 1028<figref>image42</figref> to generate signals 1040 and 1042. Step 1160 includes amplifying the first and second constant envelope constituents individually, and adding the amplified signals to generate the desired output signal. In one example, the amplification of the first and second constant envelope constituents is substantially equal and conforms to a desired power level of the desired output signal. In the example of Figure 10, step 1160 is achieved by PAs 1044 and 1046 that amplify signals 1040 and 1042 to generate the amplified signals 1048 and 1050. Figure 12 is a block diagram illustrating an exemplary embodiment of a 1200 vector power amplifier that implements the process flow diagram 1100. The optional components are illustrated with dashed lines, although, in other embodiments, more or less components may be optional. 10 Referring to Figure 12, the phase (I) and quadrature (Q) 1210 information signal is received by a data transfer function module of I and Q 1216. In one embodiment, the transfer function of data from I and Q 1216 samples signal 1210 according to a sampling clock 1212. The information signal of I and Q 1210 includes a baseband information of I and Q of a desired output signal r (t). In one embodiment, the data transfer function module of I and Q 1216 processes the information signal 15 1210 to generate the information signals 1220, 1222, 1224 and 1226. The operation of the data transfer function module of I and Q 1216 are described further in the following in section 3.4. Referring to Figure 12, the information signal 1220 includes the quadrature amplitude information of a first and second constant envelope constituents of a baseband version of the desired output signal r (t). With reference to Figure 9A, for example, information signal 1220 includes quadrature components 20 α and β. Referring again to Figure 12, the information signal 1226 includes a phase amplitude information of the first and second constant envelope constituents of the baseband version of the signal r (t). With reference to Figure 9A, for example, information signal 1226 includes the common phase C component. Referring again to FIG. 12, the information signals 1222 and 1224 include signals in phase 25 Ifase_reloj and quadrature Qfase_re normalized, respectively. Ifase_reloj and Qfase_reloj are standardized versions of the I and Q information signals included in the 1210 signal. In one embodiment, Ifase_reloj and Qfase_reloj are normalized in such a way that (I2phase_refix + Q2phase_refix = constant). It is noted that the phase of signal 1250 corresponds to the phase of the desired output signal and is created from Ifase_reloj and Qfase_reloj. Referring to Figure 9B, Ifase_reloj and Qfase_reloj are related to I and Q as follows:<figref>image43</figref> in which θ represents the phase of the desired output signal, which are represented by the phasor <figref>image14</figref>output in figure 9B. The sign information of the baseband information of I and Q must be taken into account to calculate θ for all four quadrants. In the exemplary embodiment of Figure 12, the information signals 1220, 1222, 1224 and 1226 are digital signals. 35 Accordingly, each of the signals 1220, 1222, 1224 and 1226 is supplied to a corresponding digital-to-analog converter (DAC) 1230, 1232, 1234 and 1236. The resolution and sampling rate of DACs 1230, 1232, 1234 and 1236 are selected according to specific signaling schemes. DAC 1230, 1232, 1234 and 1236 are controlled by DAC clock signals 1221, 1223, 1225 and 1227, respectively. The clock signals of DAC 1221, 1223, 1225 and 1227 can be calculated from the same clock signal or can be independent. In other embodiments, information signals 1220, 1222, 1224 and 1226 are generated in analog format and no DAC is required. Referring to Figure 12, DACs 1230, 1232, 1234 and 1236 convert the digital information signals 1220, 1222, 1224 and 1226 into the corresponding analog signals, and introduce these analog signals into the 45 optional interpolation filters 1231, 1233 , 1235 and 1237, respectively. Interpolation filters 1231, 1233, 1235 and 1237, which also serve as anti-slap filters, form the output signals of the DACs to produce the desired output waveform. Interpolation filters 1231, 1233, 1235 and 1237 generate signals 1240, 1244, 1246 and 1248, respectively. Signal 1242 represents the inverse of signal 1240. Referring again to Figure 12, signals 1244 and 1246, which include information from Ifase_reloj and 50 from Qfase_reloj, are introduced into a vector modulator 1238. Vector modulator 1238 multiplies signal 1244 with a channel clock signal 1214 The channel clock signal 1214 is selected according to a desired output signal frequency. In parallel, the vector modulator 1238 multiplies the signal 1246 with a 90 ° offset version of the channel clock signal 1214. In other words, the vector modulator 1238 generates a phase component that has the amplitude of Ifase_reloj and a quadrature component. which has the amplitude of Qfase_reloj. <figref>image44</figref> The vector modulator 1238 combines the two modulated signals to generate the Clock 1250 signal. The 5 Clock 1250 signal is a substantially constant envelope signal having the desired output frequency and a phase shift angle according to the data of I and Q included in signal 1210. Referring again to Figure 12, signals 1240, 1242 and 1248 include the amplitude components U, L and Common C, respectively, of the complex envelope of the signal r (t). The 1240, 1242 and 1248 signals together with the 1250 Clock signal are introduced into the 1260 and 1262 vector modulators. 10 The vector modulator 1260 combines the signal 1240, which is multiplied with a 90 ° offset version of the 1250 clock signal and the 1248 signal, which is multiplied with a 0 ° offset version of the 1250 clock signal; to generate the output signal 1264. In parallel, the vector modulator 1262 combines the signal 1242, which is multiplied with a 90º offset version of the 1250 clock signal and the 1248 signal, modulated with a 0º offset version of the 1250 clock signal, to generate the output signal 1266. 15 Output signals 1264 and 1266 represent substantially constant envelope signals. In addition, the phase shifts of the output signals 1264 and 1266 in relation to the 1250 Clock signal are determined by the angle relationships associated with the α / C and β / C ratios, respectively. In one embodiment, α = β and, therefore, the output signals 1264 and 1266 are phase shifted symmetrically in relation to the clock signal 1250. With reference to Figure 9B, for example, the output signals 1264 and 1266 correspond,<figref>image14</figref><figref>image14</figref> 20 respectively, with the phasors of constant magnitude of yde. A sum of the output signals 1264 and 1266 results in a channel clock modulated signal having the characteristics of I and Q of the baseband signal r (t). To achieve a desired power level at the output of the vector power amplifier 1200, however, signals 1264 and 1266 are amplified to generate an amplified output signal. In the embodiment of Figure 12, signals 1264 and 1266 are introduced, respectively, into power amplifiers (PA) 1270 and 1272 and amplified. In one embodiment, PA 1270 and 1272 include switching power amplifiers. Autopolarization circuitry 1218 controls the polarization of PAs 1270 and 1272 as further described in the following in section 3.5.2. In the embodiment of Figure 12, for example, the autopolarization circuitry 1218 provides a bias voltage 1228 to the PAs 1270 and 1272. In one embodiment, the PAs 1270 and 1272 apply a power amplification substantially equal to the signals of constant envelope 1264 -1266 respectively. In one embodiment, the power amplification is adjusted according to the desired output power level. In other embodiments of the vector power amplifier 1200, excitation circuits and / or PA pre-excitation circuits are additionally employed to provide additional power amplification capability to the amplifier. In the embodiment of Figure 12, for example, the 35 excitation circuits of PA 1284 and 1286 are optionally added, respectively, between vector modulators 1260 and 1262 and subsequent PAs 1270 and 1272. The respective output signals 1274 and 1276 of the PA 1270 and 1272 are substantially constant envelope signals. In addition, when the output signals 1274 and 1276 are added together, the resulting signal has minimal nonlinear distortion. In the embodiment of Figure 12, the output signals 1274 and 1276 are coupled between each other to generate the output signal 1280 of the vector power amplifier 1200. In one embodiment, no insulation is used in the coupling of the outputs of PAs 1270 and 1272. Accordingly, the coupling incurs a minimum loss of power. In one embodiment, the outputs of PAs 1270 and 1272 are directly coupled to each other using a wire. Direct coupling in this way means that there is no resistive, inductive or capacitive insulation, or there is a minimum one, between the outputs of PA 1270 and 1272. In other words, the outputs of the PAs 1270 and 1272 are coupled together without intermediate components. As an alternative, in one embodiment, the outputs of the PAs 1270 and 1272 are coupled to each other indirectly through inductances and / or capacities that result in low or minimum impedance connections, and / or connections that result in minimal insulation and minimal power loss. Alternatively, the outputs of PA 1270 and 1272 are coupled using well known combination techniques, such as Wilkinson circuits, 50 hybrid combiner circuits, transformers, or known active combiner circuits. In one embodiment, PA 1270 and 1272 provide a combination of power and amplification integrated in a single operation. In one embodiment, one or more of the power amplifiers and / or the excitation circuits described herein are implemented using multi-input and single-output power amplification techniques, examples of which are shown. in figures 12A, 12B and 51A -H. 55 The output signal 1280 represents a signal having the characteristics of I and Q of the baseband signal r (t) and the desired output power frequency and level. In embodiments of the vector power amplifier 1200, a bias impedance 1288 is coupled between the output of the vector power amplifier 1200 and a power supply. In other embodiments, an impedance matching network 1290 is coupled to the output of the vector power amplifier 1200. The output phase embodiments according to the power amplification procedures and systems disclosed herein will be further described. in what follows in section 3.5. <figref>image45</figref> In other embodiments of the vector power amplifier 1200, process detectors are used to compensate for any process variation in the amplifier circuitry. In the exemplary embodiment of Figure 5 12, for example, process detector 1282 is optionally added to monitor variations in the excitation circuits of PA 1284 and 1286. Fig. 12A is a block diagram illustrating another exemplary embodiment of a vector power amplifier 1200A that implements the process flow diagram 1100. The optional components are illustrated with broken lines, although, in other embodiments, more or less components may be optional. 10 Embodiment 1200A illustrates an implementation of multiple inputs and a single output (MISO) of embodiment 1200. In embodiment 1200A, the constant envelope signals 1261 and 1263, which are output from vector modulators 1260 and 1262, are input into the MISO 1292 PA. The MISO 1292 PA is a two-input power amplifier and One way out. In one embodiment, the PA of MISO 1292 includes elements 1270, 1272, 1282, 1284 and 1286 as shown in the embodiment of Figure 12. In another embodiment, the MISO 1292 PA may include other elements, such as pre-excitation circuits, which are not shown in the embodiment of Figure 12. In addition, the MISO 1292 PA is not limited to being a PA of two inputs as shown in figure 12A. In other embodiments, as will be described further in the following with reference to Figures 51A-H, the PA 1292 may have any number of inputs and outputs. Referring again to Figure 12A, embodiment 1200A illustrates an implementation for delivering the 20 autopolarization signals to the PA of MISO 1292. In the embodiment of Figure 12A, the autopolarization signal 1228 that is generated by the autopolarization circuitry 1218 , has one or more signals that are calculated from this to polarize different phases of the PA of MISO 1292. As shown in the example of Figure 12A, three polarization control signals Polarization A, Polarization B and Polarization C are calculated from the autopolarization signal 1228 and then introduced into different phases of the PA of MISO 1292 For example, Polarization C may be the polarization signal for the pre-excitation circuit phase of the PA of MISO 1292. Similarly, Polarization B and Polarization A may be the polarization signals for the excitation and PA circuit phases of the PA of MISO 1292. In another implementation, shown in embodiment 1200B of Figure 12B, the Autopolarization circuitry 1218 generates the separate autopolarization signals 1295, 1296 and 1295, which correspond to Polarization A, Polarization B and Polarization C, respectively. Signals 1295, 1296 and 1297 may or may not be generated separately within the autopolarization circuitry 1218, but are issued separately, as shown. In addition, signals 1295, 1296 and 1297 may or may not be related as determined by polarization of the different phases of the PA of MISO 1294. Other aspects of the vector power amplifiers 1200A and 1200B correspond substantially to those described above with respect to the vector power amplifier 1200. Figure 13 is a block diagram illustrating another exemplary embodiment 1300 of a vector power amplifier in accordance with the realization of CPPA 2-Branch VPA. The optional components are illustrated with dashed lines, although, in other embodiments, more or less components may be optional. In the exemplary embodiment of Figure 13, a DAC of sufficient resolution and sampling rate 1320 40 replaces DAC 1230, 1232, 1234 and 1236 of the embodiment of Figure 12. DAC 1320 is controlled by a DAC clock 1324 The DAC 1320 receives the information signal 1310 from the data transfer function module of I and Q 1216. The information signal 1310 includes identical information content for signals 1220, 1222, 1224 and 1226 in the embodiment of Figure 12. 45 The DAC 1320 can emit a single analog signal at a time. Therefore, a sampling and retention architecture can be used as shown in Figure 13. The DAC 1320 sequentially outputs analog signals 1332, 1334, 1336, 1336 to a first set of sampling and retention circuits 1342, 1344, 1346 and 1348. In one embodiment, DAC 1230 is timed at a rate sufficient to replace DACs 1230, 1232, 1234 and 1236 of the embodiment of Figure 12. An output selector 50 1322 determines which of the output signals 1332, 1334, 1336 and 1338 should be selected for the output. The DAC clock signal 1324 of the DAC 1320, the output selector signal 1322 and the sampling and retention clocks 1340A -D and 1350 are controlled by a control module that can be independent or integrated in the function module of transfer 1216. In one embodiment, sampling and retention circuits (S / H) 1342, 1344, 1346 and 1348 retain the analog values ​​received and, in accordance with a clock signal 1340A-D, release the values ​​for a second set of circuits of sampling and retention 1352, 1354, 1356 and 1358. For example, S / H 1342 releases its value for S / H 1352 according to a received 1340A clock signal. In turn, sampling and retention circuits 1352, 1354, 1356 and 1358 retain the received analog values, and simultaneously release the values ​​for interpolation filters 1231, 1233, 1235 and 1237 according to a common clock signal 1350. A common clock signal <figref>image46</figref> 5 1350 is used to ensure that the outputs of S / H 1352, 1354, 1356 and 1358 are aligned in time. In another embodiment, a single S / H circuitry layer may be employed that includes S / H 1342, 1344, 1346 and 1348. Accordingly, S / H circuits 1342, 1344, 1346 and 1348 receive analog values ​​at from DAC 1320, and each releases its received value according to a clock independent of the others. For example, the S / H 1342 is controlled by the 1340A clock, which may not be synchronized with the 1340B clock that controls the S / H 10 1344. To ensure that the outputs of the S / H circuits 1342, 1344, 1346 and 1348 are aligned in time, the delays between the 1340A-D clocks are previously compensated in the previous phases of the amplifier. For example, the DAC 1320 emits the signal 1332, 1334, 1336 and 1338 with the delays appropriately selected to the S / H circuits 1342, 1344, 1346 and 1348 in order to compensate for the time differences between the clocks 1340A -D. Other aspects of the vector power amplifier 1300 are substantially equivalent to those described above with respect to the vector power amplifier 1200. Figure 13A is a block diagram illustrating another exemplary embodiment 1300A of a vector power amplifier in accordance with the CPPA 2-Branch VPA embodiment. The optional components are illustrated with dashed lines, although, in other embodiments, more or less components may be optional. 20 Embodiment 1300A is a MISO implementation of embodiment 1300 of Figure 13. In the embodiment of Figure 13A, the constant envelope signals 1261 and 1263 that are emitted from the vector modulators 1260 and 1262 are input into the MISO 1360 PA. The MISO 1360 PA is a two-input power amplifier. and of a single exit. In one embodiment, the MISO PA 1360 includes elements 1270, 1272, 1282, 1284 and 1286 as shown in the embodiment of Figure 13. In another embodiment, the PA of MISO 1360 may include other elements, such as pre-excitation circuits, which are not shown in the embodiment of Figure 13, or functional equivalents thereof. In addition, the PA of MISO 1360 is not limited to being a PA of two inputs as shown in Figure 13A. In other embodiments, as will be described further below with reference to Figures 51A-H, the PA 1360 may have any number of inputs. The embodiment of Figure 13A further illustrates two different sampling and retention architectures with a single or two two levels of S / H circuitry, as shown. The two implementations have been described above with respect to Figure 13. Embodiment 1300A also illustrates the optional polarization control circuitry 1218 and associated polarization control signals 1325, 1326 and 1327. The signals 1325, 1326 and 1327 can be used to polarize different phases of the MISO 1360 PA in certain embodiments. 35 Other aspects of the 1300A vector power amplifier are equivalent to those described above with respect to the 1200 and 1300 vector power amplifiers. 3.3) Direct 2-Branch Vector Power Amplifier A 2-Cartesian Branches VPA Direct copy. According to the exemplary Direct Cartesian 2 Branches VPA, a time-varying envelope signal is broken down into two signals of constant envelope constituent. The constituent signals are amplified individually equally or substantially equally and then added to construct an amplified version of the variable envelope signal at the original time. In an example of the Direct Cartesian 2 Branches VPA, a magnitude and a phase angle of a time-varying envelope signal are calculated from the quadrature and phase components of an input signal. Using the magnitude and phase information, the quadrature and phase amplitude components are calculated for two constant envelope constituents of the time varying envelope signal. Next, the two constant envelope constituents are generated, amplified equally or substantially equally, and added together to generate an amplified version of the variable envelope signal in the original Rentrada time. 50 The concept of the Direct Cartesian 2 Branch VPA will be described below with reference to Figures 9A and 14. As described above and verified with respect to Figure 9A, the phasor<figref>image14</figref>can be obtained by adding a higher phasor <figref>image14</figref>and a lower fasor <figref>image14</figref>phase shifted appropriately to <figref>image47</figref> produce <figref>image14</figref>’. <figref>image14</figref>'is calculated to be proportional to the Rentrada magnitude. Further,<figref>image14</figref>and <figref>image14</figref>they can be maintained so that they have a substantially constant magnitude. In the domain of time,<figref>image14</figref>' and <figref>image14</figref>'represent two substantially constant envelope signals. The equivalent in the time domain r '(t) of<figref>image14</figref>'can be obtained in this way, at any time, by adding two substantially constant envelope signals. 5 For the case illustrated in Figure 9A, the phase shift of<figref>image14</figref>' and <figref>image14</figref>' regarding <figref>image14</figref>'illustrated as the angle <figref>image14</figref>in figure 9A, it is related to the magnitude of <figref>image14</figref>'as follows: <figref>image48</figref><figref>image49</figref> in which R represents the normalized magnitude of the phasor In the time domain, it was shown that a time-varying envelope signal, r '(t) = R (t) cos (ωt) for example, can be constructed by sum of two constant envelope signals as follows: <figref>image50</figref> in which C indicates the phase amplitude component of the phasors <figref>image14</figref>' and <figref>image14</figref>'and is equal to or substantially equal to A × cos ( <figref>image14</figref>) (being A constant). α and β indicate the quadrature amplitude components of the phasors<figref>image14</figref>' and <figref>image14</figref>', respectively. α = β = A × sen (<figref>image14</figref>). It is noted that equations (14) can be modified for the 15 non-sinusoidal signals by changing the base function, from sinusoidal to the desired function. Figure 14 illustrates the fasor<figref>image14</figref><figref>image14</figref>and its two constituent fasores of constant magnitude <figref>image14</figref>and<figref>image14</figref>. <figref>image14</figref>moves θ degrees relative to 'in Figure 9A. Therefore, it can be verified that:<figref>image51</figref> From equations (15), it can be further shown that: <figref>image52</figref> Similarly, it can be shown that: <figref>image53</figref> Equations (16) and (17) can be rewritten as: <figref>image54</figref> Equivalently, in the time domain: <figref>image55</figref> in which ϕ1 (t) and ϕ2 (t) represent an appropriately selected orthogonal base function. From equations (18) and (19), it is observed that it is sufficient to calculate the values ​​of α, β, C and sin (Θ) and cos (Θ) in order to determine the two constant envelope constituents of a variable envelope signal at time r (t). In addition, α, β and C can be determined in their entirety from the magnitude and phase information, equivalently the components of I and Q, of the signal r (t). Figure 15 is a block diagram that conceptually illustrates an example 1500 of the Direct Cartesian 2 Branch VPA. An output signal r (t) of a power level, and of desired frequency characteristics, is generated from the quadrature components and in phase according to the example of Direct Cartesian 2 Branches VPA. In the example of Figure 15, a clock signal 1510 represents a reference signal to generate the output signal r (t). The clock signal 1510 is of the same frequency as that of the desired output signal r (t). Referring to Figure 15, example 1500 includes a first branch 1572 and a second branch 1574. The first branch 1572 includes a vector modulator 1520 and a power amplifier (PA) 1550. Similarly, the second branch 1574 includes a vector modulator 1530 and a power amplifier (PA) 1560. 20 Referring again to Figure 15, the clock signal 1510 is introduced, in parallel, into the vector modulators 1520 and 1530. In the vector modulator 1520, a 1522 phase version of the clock signal 1510, which is multiplied with the signal Ux 1526, is added with a 90 degree offset version 1524 of the clock signal 1510, which is multiplied with the signal Uy 1528. In parallel, in the vector modulator 1530, a 1532 phase version of the clock signal 1510, which is multiplied with the signal Lx 1536, is added with a 90 degree offset version 1534 of the clock signal 1510, which It is multiplied with the Ly 1538 signal. The signal Ux 1526 and the signal Uy 1528 correspond, respectively, to the quadrature amplitude and phase components of the constant envelope constituent of U (t) of the signal r (t) provided in equation (19 ). Similarly, the signal Lx 1536 and the signal Ly 1538 correspond, respectively, with the quadrature amplitude and phase components of the constant envelope constituent of L (t) of the signal r (t) provided in the equation (19). 30 Accordingly, the respective output signals 1540 and 1542 of the vector modulators 1520 and 1530 correspond, respectively, to the constant envelope constituents of U (t) and L (t) of the signal r (t) as described above in equations (19). As described above, signals 1540 and 1542 are characterized by having equal and constant or substantially equal and constant envelopes. 35 Referring to Figure 15, to generate the desired power level of the output signal r (t), signals 1540 and 1542 are input into the corresponding power amplifiers 1550 and 1560. In one example, power amplifiers 1550 and 1560 apply a power amplification equal to or substantially equal to signals 1540 and 1542, respectively. In one example, the power amplification level of PA 1550 and 1560 is adjusted according to the desired power level of the output signal r (t). 40 The amplified output signals 1562 and 1564 are substantially constant envelope signals. Therefore, when added together, as shown in Figure 15, the resulting signal 1570 corresponds to the desired output signal r (t).<figref>image56</figref> Figure 15A is another 1500A example of the Direct Cartesian 2 Branch VPA. Example 1500A represents an implementation of Multiple Inputs and a Single Output (MISO) of embodiment 1500 of Figure 15. In example 1500A, the constant envelope signals 1540 and 1542, which are emitted from vector modulators 1520 and 1530, are introduced into the MISO 1580 PA. The MISO 1580 PA is a power amplifier 5 with two inputs and a single output. In one example, the MISO 1580 PA may include several elements, such as pre-excitation circuits, excitation circuits, power amplifiers and process detectors (not shown in Figure 15A), for example. In addition, the MISO 1580 PA is not limited to being a two-input PA as shown in Figure 15A. In other examples, as will be described further in the following with reference to Figures 51A-H, the PA 1580 may have any number of inputs. 10 The operation of the exemplary Direct Cartesian 2 Branch VPA is depicted in the process flow diagram 1600 of Figure 16. The procedure begins in step 1610, which includes receiving a baseband representation of a desired output signal. In one example, the baseband representation includes the components of I and Q. In another example, the I and Q components are RF components to which a reductive conversion is applied to the baseband. 15 Step 1620 includes receiving a clock signal set in accordance with a desired output signal frequency of the desired output signal. In the example of Figure 15, step 1620 is achieved by receiving the clock signal 1510. Step 1630 includes the processing of the I and Q components to generate the quadrature amplitude and phase information of the first and second constant envelope constituent signals of the desired output signal. In the example of Figure 15, the quadrature and phase amplitude information is illustrated by Ux, Uy, Lx, and Ly. Step 1640 includes the processing of the amplitude information and the clock signal to generate the first and second constant envelope constituent signals of the desired output signal. In one example, the first and second constant envelope constituent signals are modulated according to the desired output signal frequency. In the example of Fig. 15, step 1640 is achieved by vector modulators 1520 and 1530, clock signal 1510, and amplitude information signals 1526, 1528, 1536 and 1538 to generate signals 1540 and 1542. Step 1650 includes amplifying the first and second constant envelope constituents, and adding the amplified signals to generate the desired output signal. In one example, the amplification of the first and second constant envelope constituents is in accordance with a desired power level of the desired output signal. In the example of FIG. 15, step 1650 is achieved by means of PA 1550 and 1560 that amplify the respective signals 1540 and 1542 and, subsequently, by adding the amplified signals 1562 and 1564 to generate the output signal 1574 . Figure 17 is a block diagram illustrating an exemplary embodiment of a vector power amplifier 35 1700 that implements the process flow diagram 1600. The optional components are illustrated with broken lines, although other embodiments may have more or less optional components. Referring to Figure 17, the phase (I) and quadrature (Q) 1710 information signal is received by a data transfer function module of I and Q 1716. In one embodiment, the function module of data transfer of I and Q 1716 samples signal 1710 according to a sampling clock 1212. Information signal 40 of I and Q 1710 includes a base band information of I and Q. In one embodiment, the data transfer function module of I and Q 1716 processes the information signal 1710 to generate the information signals 1720, 1722, 1724 and 1726. The operation of the data transfer function module of I and of Q 1716 is described further in the following in section 3.4. Referring to Figure 17, the information signal 1720 includes the quadrature amplitude information of the vector modulator 1750 that is processed through the DAC 1730 to generate the signal 1740. The information signal 1722 includes the amplitude information in phase of the vector modulator 1750 that is processed through the DAC 1732 to generate the signal 1742. The signals 1740 and 1742 are calculated to generate a substantially constant envelope signal 1754. With reference to Figure 14, for example, information signals 1720 and 1722 include the upper quadrature and phase components Uy and Ux, respectively. 50 Referring again to Figure 17, the information signal 1726 includes the quadrature amplitude information of the vector modulator 1752 that is processed through the DAC 1736 to generate the signal 1746. The information signal 1724 includes the phase amplitude information of the vector modulator 1752 that is processed through the DAC 1734 to generate the signal 1744. The signals 1744 and 1746 are calculated to generate a substantially constant envelope signal 1756. With reference to Figure 14, for example, information signals 55 1724 and 1726 include the quadrature and lower phase components Lx and Ly, respectively. <figref>image57</figref> In the exemplary embodiment of Figure 17, the information signals 1720, 1722, 1724 and 1726 are digital signals. Accordingly, each of the signals 1720, 1722, 1724 and 1726 is supplied to a corresponding digital-to-analog converter (DAC) 1730, 1732, 1734 and 1736. The resolution and sampling rates of DACs 1730, 1732, 1734 and 1736 are selected according to the specific desired signaling schemes. DAC 5 1730, 1732, 1734 and 1736 are controlled by DAC clock signals 1721, 1723, 1725 and 1727, respectively. The clock signals of DAC 1721, 1723, 1725 and 1727 can be calculated from the same clock or can be independent of each other. In other embodiments, information signals 1720, 1722, 1724 and 1726 are generated in analog format and no DAC is required. 10 Referring to Figure 17, DACs 1730, 1732, 1734 and 1736 convert the digital information signals 1720, 1722, 1724 and 1726 into the corresponding analog signals, and introduce these analog signals into the optional interpolation filters 1731, 1733, 1735 and 1737, respectively. The interpolation filters 1731, 1733, 1735 and 1737, which also serve as anti-lap filters, form the output signals of the DACs to produce the desired output waveform. Interpolation filters 1731, 1733, 1735 and 1737 generate signals 1740, 15 1742, 1744 and 1746, respectively. Referring again to Figure 17, signals 1740, 1742, 1744 and 1746 are introduced into vector modulators 1750 and 1752. Vector modulators 1750 and 1752 generate first and second constant envelope constituents. In the embodiment of Figure 17, the channel clock 1714 is adjusted according to a desired output signal frequency to thereby establish the frequency of the output signal 1770. twenty Referring to Figure 17, the vector modulator 1750 combines signal 1740, which is multiplied with a 90 ° offset version of the channel clock signal 1714 and signal 1742, which is multiplied with a 0 ° offset version of the clock signal. of channel 1714, to generate the output signal 1754. In parallel, the vector modulator 1752 combines the signal 1746, which is multiplied with a 90 ° offset version of the channel clock signal 1714 and the signal 1744, which is multiplied with a 0 ° offset version of the channel clock signal 1714, to generate the output signal 1756. The output signals 1754 and 1756 represent constant envelope signals. A sum of the output signals 1754 and 1756 results in a carrier signal having the characteristics of I and Q of the original baseband signal. In embodiments, to generate a desired power level at the output of the vector power amplifier 1700, signals 1754 and 1756 are amplified and then added. In the embodiment of Figure 17, for example, signals 1754 and 1756 are introduced, respectively, into the corresponding power amplifiers (PA) 1760 and 1762. In one embodiment, PA 1760 and 1762 include switching power amplifiers. Autopolarization circuitry 1718 controls the polarization of PAs 1760 and 1762. In the embodiment of Figure 17, for example, the autopolarization circuitry 1718 provides a bias voltage 1728 to the PA 1760 and 1762. In one embodiment, the PA 1760 and 1762 apply a power amplification equal to or substantially equal to the respective envelope signals 1754 and 1756 respectively. In one embodiment, the power amplification is adjusted according to the desired output power level. In other embodiments of the vector power amplifier 1700, the PA excitation circuits are additionally employed to provide additional power amplification capability to the amplifier. In the embodiment of Figure 17, for example, the PA excitation circuits 1774 and 1776 are optionally added, respectively, between the vector modulators 1750 and 1752 and the subsequent PA 1760 and 1762. The respective output signals 1764 and 1766 of the PA 1760 and 1762 are substantially constant envelope signals. In the embodiment of Figure 17, the output signals 1764 and 1766 are coupled to each other to generate the output signal 1770 of the vector power amplifier 1700. In the embodiments, it is noted that the outputs of the PAs 1760 and 1762 they fit directly. Direct coupling in this way means that there is no resistive, inductive or capacitive insulation, or there is a minimum one, between the outputs of the PA 1760 and 1762. In other words, the outputs of the PA 1760 and 1762 are coupled between Yes without intermediate components. As an alternative, in one embodiment, the outputs of the PA 1760 and 1762 are indirectly coupled to each other through inductances and / or capacities that result in low or minimum impedance connections, 50 and / or connections that result in Minimum insulation and minimum power loss result. As an alternative, the outputs of the PA 1760 and 1762 are coupled using well known combination techniques, such as Wilkinson circuits, hybrid couplers, transformers, or known active combiner circuits. In one embodiment, PA 1760 and 1762 provide a combination of power and amplification integrated in a single operation. In one embodiment, one or more of the power amplifiers and / or the excitation circuits 55 described herein are implemented using multi-input and single-output power amplification techniques (MISO), examples of which are shown in Figures 17A, 17B and 51A-H. The output signal 1770 represents a signal that has the desired I and Q characteristics of the baseband signal and the desired output power frequency and level. In embodiments of the vector power amplifier 1700, a bias impedance 1778 is coupled between the output of the vector power amplifier 1700 and a power supply. In other embodiments, an impedance matching network 1780 is coupled to the output of the vector power amplifier 1700. The output phase embodiments according to the power amplification procedures and systems disclosed herein are <figref>image58</figref> 5 will further describe in what follows in section 3.5. In other embodiments of the vector power amplifier 1700, process detectors are used to compensate for any variation in process and / or temperature in the amplifier circuitry. In the exemplary embodiment of Figure 17, for example, the process detector 1772 is optionally added to monitor variations in the excitation circuits of PA 1774 and 1776. 10 Figure 17A is a block diagram illustrating another exemplary embodiment 1700A of a vector power amplifier that implements the process flow diagram 1600. The optional components are illustrated with broken lines, although other embodiments may have more or more Less optional components. Embodiment 1700A illustrates an implementation of multiple inputs and a single output (MISO) of the amplifier of Figure 17. In the embodiment of Figure 17A, the constant envelope signals 1754 and 1756, which are emitted from the vector modulators 1750 and 1760, are introduced into the MISO 1790 PA. The MISO 1790 PA is a power amplifier of two entrances and a single exit. In one embodiment, the MISO PA 1790 includes elements 1760, 1762, 1772, 1774 and 1776 as shown in the embodiment of Figure 17, or functional equivalents thereof. In another embodiment, the MISO PA 1790 may include other elements, such as pre-excitation circuits, which are not shown in the embodiment of Figure 17. In addition, the PA of MISO 1790 is not limited to 20 being a PA of two inputs as shown in figure 17A. In other embodiments, as will be described further in the following with reference to Figures 51A-H, the PA 1790 may have any number of inputs. In another embodiment of embodiment 1700, shown as embodiment 1700B of Figure 17B, the optional autopolarization circuitry 1218 generates separate polarization control signals 1715, 1717 and 1719, 25 corresponding to Polarization A, the Polarization B and Polarization C, respectively. Signals 1715, 1717 and 1719 may or may not be generated separately within the autopolarization circuitry 1718, but are issued separately, as shown. In addition, signals 1715, 1717 and 1719 may or may not be related as determined by the polarization that is required for the different phases of the PA of MISO 1790. 30 Figure 18 is a block diagram illustrating another exemplary embodiment 1800 of a vector power amplifier according to the Direct Cartesian 2-Branch VPA embodiment of Figure 16. The optional components are illustrated with dashed lines, despite that other embodiments may have more or less optional components. In the exemplary embodiment of Figure 18, a DAC 1820 of sufficient resolution and sampling rate 35 replaces DAC 1730, 1732, 1734 and 1736 of the embodiment of Figure 17. DAC 1820 is controlled by a DAC clock. 1814. DAC 1820 receives information signal 1810 from the data transfer function module of I and Q 1716. The information signal 1810 includes an identical information content for signals 1720, 1722, 1724 and 1726 in the embodiment of Figure 17. 40 The DAC 1820 can emit a single analog signal at a time. Therefore, a sampling and retention architecture can be used as shown in Figure 18. In the embodiment of Figure 18, DAC 1820 sequentially outputs analog signals 1822, 1824, 1826 and 1828 to sampling and retention circuits 1832, 1834, 1836 and 1838, respectively. In one embodiment, DAC 1820 is of sufficient resolution and sampling rate to replace DAC 1720, 1722, 1724 and 1726 of the embodiment of Figure 17. An output selector 1812 determines which of the output signals 1822 , 1824, 1826 and 1828 are selected for departure. The DAC clock signal 1814 of the DAC 1820, the output selector signal 1812 and the sampling and retention clocks 1830A -D and 1840 are controlled by a control module that can be independent or integrated in the function module of transfer 1716. fifty In one embodiment, sampling and retention circuits 1832, 1834, 1836 and 1838 sample and retain their respective values ​​and, in accordance with a clock signal 1830A-D, release the values ​​for a second set of sampling and retention circuits 1842 , 1844, 1846 and 1848. For example, S / H 1832 releases its value for S / H 1842 according to a received 1830A clock signal. In turn, the sampling and retention circuits 1842, 1844, 1846 and 1848 retain the analog values ​​received, and simultaneously release the values ​​for the interpolation filters 1852, 1854, 1856 and 1858 according to a clock signal common 1840. In another embodiment, a single S / H circuitry assembly may be employed that includes S / H 1832, 1834, 1836 and 1838. Accordingly, the S / H circuits 1832, 1834, 1836 and 1838 receive analog values ​​from DAC 1820, and each sample and retain its received value in accordance with the independent clocks 1830A -D. For example, the S / H 1832 is controlled by the clock 1830A, which may not be synchronized with the clock 1830B that controls the S / H 1834. For example, DAC 1820 emits signals 1822, 1824, 1826 and 1828 with appropriately selected analog values ​​that are calculated by the function module of <figref>image59</figref> 5 transfer 1716 to the circuits of S / H 1832, 1834, 1836 and 1838 in order to compensate for the time differences between the 1830A-D clocks. Other aspects of the vector power amplifier 1800 correspond substantially to those described above with respect to the vector power amplifier 1700. Figure 18A is a block diagram illustrating another exemplary embodiment 1800A of a vector power amplifier 10 in accordance with the realization of Direct Cartesian 2 Branch VPA. The optional components are illustrated with dashed lines, although, in other embodiments, more or less components may be optional. Embodiment 1800A is an implementation of Multiple Inputs and a Single Output (MISO) of embodiment 1800 of Figure 18. In the embodiment of Figure 18A, the constant envelope signals 1754 and 1756, which are emitted from the 15 vector modulators 1750 and 1752, are introduced into the MISO 1860 PA. The MISO 1860 PA is a power amplifier of two entrances and a single exit. In one embodiment, the MISO PA 1860 includes elements 1744, 1746, 1760, 1762 and 1772 as shown in the embodiment of Figure 18, or functional equivalents thereof. In another embodiment, the MISO 1860 PA may include other elements, such as pre-excitation circuits, which are not shown in the embodiment of Figure 17. In addition, the MISO 1860 PA is not limited to 20 being a PA of two inputs as shown in figure 18A. In other embodiments, as will be described further below with reference to Figures 51A-H, the PA 1860 may have any number of inputs. The embodiment of Figure 18A further illustrates two different sampling and retention architectures with a single or two levels of S / H circuitry, as shown. The two implementations have been described above in relation to Figure 18. Other aspects of the 1800A vector power amplifier are substantially equivalent to those described above with respect to the 1700 and 1800 vector power amplifiers. . 3.4) Data Transfer Functions of I and Q to Vector Modulator In some of the embodiments described above, data transfer functions 30 of I and Q are provided to transform the data of I and of Q received in amplitude information inputs for subsequent amplification and vector modulation phases. For example, in the embodiment of Figure 17, the data transfer function module of I and Q 1716 processes the information signal of I and Q 1710 to generate the quadrature amplitude and phase 1720 information signals , 1722, 1724 and 1726 of a first and second constant envelope constituents 1754 and 1756 of the signal r (t). Subsequently, vector modulators 1750 and 1752 use the amplitude information signals generated 1720, 1722, 1724 and 1726 to create the first and second constant envelope constituent signals 1754 and 1756. Other examples include modules 710, 712 and 1216 in Figures 7, 8, 12 and 13. These modules implement transfer functions to transform the I and / or Q data into amplitude information inputs for subsequent amplification and vector modulation phases. 40 In accordance with the disclosure herein, the I and Q data transfer function modules can be implemented using digital circuitry, analog circuitry, software, firmware or any combination thereof. Various factors affect the actual implementation of a transfer function, and vary from realization to realization. In one aspect, the realization of selected VPA regulates the output of amplitude information of the transfer function and the associated module. It is obvious, for example, that the data transfer function module of I and Q 1216 of the 2-Branch VPA realization CPCP 1200 differs, in terms of output, from the data transfer function module of I and of Q 1716 of the 1700 Direct Cartesian 2 Branch VPA realization. In another aspect, the complexity of the transfer function varies according to the desired 50 modulation scheme or schemes that are required to be supported by the VPA implementation. For example, the sampling clock, the DAC sampling rate and the DAC resolution are selected according to the appropriate transfer function to construct the desired output waveform or shapes. The embodiments of the transfer function can be designed to support one or more embodiments of VPA with the ability to switch between supported embodiments as desired. In addition, embodiments of the transfer function and associated modules can be designed to facilitate a plurality of modulation schemes. One skilled in the art will appreciate, for example, that the embodiments of the present invention can be designed to support a plurality of modulation schemes (individually or in combination)<figref>image60</figref> including, but not limited to, BPSK, QPSK, OQPSK, DPSK, CDMA, WCDMA, W -CDMA, GSM, EDGE, MPSK, MQAM, MSK, CPSK, PM, FM, OFDM, and multi-tone signals. In one embodiment, the modulation scheme or schemes may be configurable and / or programmable through the transfer function module. 3.4.1) 4-Branch Cartesian VPA Transfer Function 5 Figure 19 is a 1900 process flow diagram illustrating an exemplary I and Q transfer function according to the exemplary 4-Cartesian Branches VPA . The procedure begins in step 1910, which includes receiving a phase data component and a quadrature data component. In the 4-Branch Cartesian VPA embodiment of Figure 7A, for example, this is illustrated by the data transfer function module of I 710 that receives the information signal of I 702, and the transfer function module 10 of data from Q 712 receiving the information signal from Q 704. It is noted that, in the embodiment of Figure 7A, the data transfer function modules of I and Q 710 and 712 are illustrated as independent components . In the implementation, however, the data transfer function modules of I and Q 710 and 712 can be independent or combined into a single module. Step 1920 includes the calculation of a phase offset angle between the substantially equal and constant first and second envelope constituents of the component of I. In parallel, step 1920 also includes the calculation of a phase offset angle between the substantially equal and constant first and second envelope constituents of the Q component. As described above, the first constant envelope constituents and second of the components of I move in phase appropriately in relation to the component of I. Similarly, the first and second constant envelope constituents of the Q components are phase shifted appropriately in relation to the Q component. In the embodiment of Figure 7A, for example, step 1920 is performed by the data transfer function modules of I and Q 710 and 712. Stage 1930 includes the calculation of the quadrature and phase amplitude information associated with the first and second constant envelope constituents of the I component. In parallel, step 1930 includes the calculation of the quadrature amplitude information and in phase associated with the first and second constant envelope constituents of the Q component. In the embodiment of Figure 7A, for example, step 1930 is performed by the data transfer function modules of I and Q 710 and 712. Step 1940 includes issuing the calculated amplitude information to a vector modulation phase. subsequent. In the embodiment of Figure 7A, for example, the transfer function modules of I and Q 710 and 712 emit the amplitude information signals 722, 724, 726 and 728 to the vector modulators 760, 762, 764 and 766 through DAC 730, 732, 734 and 736. Figure 20 is a block diagram illustrating an example 2000 of a transfer function module, such as transfer function modules 710 and 712 of Figure 7A, which implements the process flow diagram 1900. In the example in Figure 20, the transfer function module 2000 receives data signals 35 from I and Q 2010 and 2012. In one example, the data signals of I and Q 2010 and 2012 represent the data components of I and Q of a baseband signal, such as signals 702 and 704 in Figure 7A. Referring to Figure 20, in one example, the transfer function module 2000 samples the data signals of I and Q 2010 and 2012 according to a 2014 sampling clock. The sampled I and Q data signals are received by the 2020 and 2022 components, respectively, of the 2000 transfer function module 2000. The 2020 and 2022 components respectively measure the magnitudes of the I and the data signals. Q sampled. In one example, components 2020 and 2022 are magnitude detectors. Components 2020 and 2022 issue the information of magnitude of I and Q measured to components 2030 and 2032, respectively, of the transfer function module 2000. In one example, the information of magnitude of I and Q measured is found in Shape of digital signals. Based on the information of magnitude of I, component 2030 calculates a phase shift angle ϕI between envelope constituents equal and constant or substantially equal and first and second constant of the sampled I signal. Similarly, based on the information of magnitude of Q, component 2032 calculates the phase shift angle ϕQ between equal and constant or substantially equal envelope constituents and first and second constant of the sampled Q signal. This operation will be described further below. 50 In the example in Figure 20, ϕI and ϕQ are illustrated as the functions f (|<figref>image14</figref>|) and f (| <figref>image14</figref>|) of the signals of magnitude of I and Q. In one example, the functions f (| <figref>image14</figref>|) and f (| <figref>image14</figref>|) are adjusted according to the relative magnitudes of the baseband I and Q signals respectively. They will be described further in the following, in section 3.4.4, f (|<figref>image14</figref>|) and f (| <figref>image14</figref>|). Referring to Figure 20, components 2030 and 2032 issue the phase shift information 55 calculated to components 2040 and 2042, respectively. Based on the phase shift angle ϕI, component 2040 calculates the quadrature and phase amplitude information of the first and second constant envelope constituents of the sampled I signal. Similarly, based on the phase shift angle ϕQ, component 2042 calculates the quadrature and phase amplitude information of the first and second constant envelope constituents of the sampled Q signal. Because of the symmetry, in one example, it<figref>image61</figref> 5 requires calculation only for 4 values. In the example of Figure 20, the values ​​are illustrated as sgn (I) × IUX, IUY, QUX, and sgn (Q) × QUY, as provided in Figure 5. Components 2040 and 2042 issue the information calculated amplitude to subsequent phases of the vector power amplifier. In one example, each of the four calculated values ​​is output separately to a digital to analog converter. As shown in the embodiment of Figure 7A for example, signals 10 722, 724, 726 and 728 are output separately to DACs 730, 732, 734 and 736, respectively. In other embodiments, signals 722, 724, 726 and 728 are output to a single DAC as shown in Figures 8A and 8B. 3.4.2) VCP Transfer Function of 2 CPCP Branches

Figure 21 is a process flow diagram 2100 illustrating an example I and Q transfer function in accordance with the exemplary 2-Branch CPCP VPA. The procedure begins in step 2110, which includes receiving data components in phase (I) and quadrature (Q) of a baseband signal. In the exemplary 2-Branch CPCP VPA of Figure 12, for example, this is illustrated by the data transfer function module of I and Q 1216 that receives the information signal from I and Q 1210. Step 2120 includes the determination of the quantities | I | and | Q | of the data components of I and Q 20 received. Step 2130 includes the calculation of a magnitude | R | of the baseband signal based on the magnitudes of | I | and of | Q | measurements. In an example, | R | it is such that | R | 2 = | I | 2 + | Q | 2. In the embodiment of Figure 12, for example, steps 2120 and 2130 are performed by the data transfer function module of I and Q 1216 based on the received information signal 1210. 25 Step 2140 includes the normalization of the quantities of | I | and of | Q | measurements. In an example, | I | and | Q | they are normalized to generate Ifase_reloj and Qfase_reloj (as shown in Figure 10) signals so that | Ifase_reloj | 2 + | Qfase_reloj | 2 = constant. In the embodiment of Figure 12, for example, step 2140 is performed by the data transfer function module of I and Q 1216 based on the received information signal 1210. 30 Step 2150 includes the calculation of the quadrature and phase amplitude information associated with first and second constant envelope constituents. In the embodiment of Figure 12, for example, step 2150 is performed by the data transfer function module of I and Q 1216 based on the magnitude of envelope | R |. Step 2160 includes issuing the generated Ifase_reloj and the Qfase_reloj (from step 2140) and the calculated amplitude information (from step 2150) to the appropriate vector modulators. In the embodiment of Figure 12, for example, the data transfer function module of I and Q 1216 issues the information signals 1220, 1222, 1224 and 1226 to the vector modulators 1238, 1260 and 1262 through the DAC 1230, 1232, 1234 and 1236. Figure 22 is a block diagram illustrating an example 2200 of a transfer function module (such as module 1216 of Figure 12) that implements the process flow diagram 2100. In the example of Figure 22, The transfer function module 2200 receives the data signal from I and Q 2210. In one example, the data signal of I and Q 2210 includes the components of I and Q of a baseband signal, such as signal 1210 in the embodiment of Figure 12, for example. In one example, the transfer function module 2200 samples the data signal of I and Q 2210 according to a sampling clock 2212. The sampled I and Q data signals are received by the component<figref>image14</figref><figref>image14</figref> 2220 of the 2200 transfer function module. The 2220 component measures the quantities | | and | | of the sampled I and Q data signals. Based on the magnitudes of |<figref>image14</figref>| and of |<figref>image14</figref>| measured, component 2230 calculates the magnitude | R | of the baseband signal. Example, |<figref>image14</figref>| burst | <figref>image14</figref>|2=| <figref>image14</figref>|2+| <figref>image14</figref>| 2. 50 In parallel, component 2240 normalizes the magnitudes of |<figref>image14</figref>| and of |<figref>image14</figref>| measurements. In an example, |<figref>image14</figref>| and |<figref>image14</figref>| are normalized to generate the Ifase_reloj and Qfase_reloj signals in such a way that | Ifase_reloj |<figref>image14</figref>two + | Qfase_reloj | 2 = constant, in which | Ifase_reloj | and | Qfase_reloj | represent the normalized quantities of | | and<figref>image62</figref> | <figref>image14</figref>| Typically, since the constant has an A value, both of the magnitudes |<figref>image14</figref>| and |<figref>image14</figref>| measures are divided by the quantity<figref>image63</figref> The 2250 component receives the magnitude | <figref>image14</figref>| calculated from component 2230, and based on it calculates a phase shift angle ϕ between first and second constant envelope constituents. 5 Using the calculated phase shift angle ϕ, component 2050 then calculates the quadrature and phase amplitude information associated with the first and second constant envelope constituents. In the example of Figure 22, the phase shift angle ϕ is illustrated as a function f (| <figref>image14</figref>|) of the magnitude | <figref>image14</figref>| calculated Referring to Figure 22, components 2240 and 2250 issue the magnitude information of | Ifase_reloj | 10 and of | Qfase_reloj | standardized and amplitude information calculated to DACs for introduction into appropriate vector modulators. In one example, the output values ​​are output separately to digital to analog converters. As shown in the embodiment of Figure 12, for example, signals 1220, 1222, 1224 and 1226 are output separately to DACs 1230, 1232, 1234 and 1236, respectively. In other embodiments, signals 1220, 1222, 1224 and 1226 are emitted to a single DAC as shown in Figures 13 15 and 13A. 3.4.3) Direct Cartesian 2 Branch Transfer Function Figure 23 is a process flow diagram 2300 illustrating an exemplary I and Q transfer function according to the exemplary Direct Cartesian 2 Branch VPA. The procedure begins in step 2310, which includes receiving data components in phase (I) and quadrature (Q) of a 20 baseband signal. In the realization of the Direct Cartesian 2-Branch VPA of Figure 17, for example, this is illustrated by the data transfer function module of I and Q 1716 that receives the information signal from I and Q 1710. step 2320 includes the determination of the quantities | I | and | Q | of the data components of I and Q received. Step 2330 includes the calculation of a magnitude | R | of the baseband signal based on the magnitudes of | I | and 25 of | Q | measurements. In an example, | R | it is such that | R | 2 = | I | 2 + | Q | 2. In the embodiment of Figure 17, for example, steps 2320 and 2330 are performed by the data transfer function module of I and Q 1716 based on the received information signal 1710. Step 2340 includes the calculation of a phase shift angle θ of the baseband signal based on the magnitudes of | I | and of | Q | measurements. In an example, θ burst <figref>image64</figref>, and in which the IQ Q 30 determines the quadrant of θ. In the embodiment of Figure 17, for example, step 2340 is performed by the data transfer function module of I and Q 1216 based on the data components of I and Q received in the information signal 1210 Step 2350 includes the calculation of quadrature and phase amplitude information associated with first and second constant envelope constituents of the baseband signal. In the embodiment of Figure 17, for example, step 2350 is performed by the data transfer function module of I and Q 1716 based on the magnitude | R | previously calculated and the phase shift angle θ. Step 2360 includes issuing the calculated amplitude information to the DACs for introduction into the appropriate vector modulators. In the embodiment of Figure 17, for example, the data transfer function module of I and Q 1716 issues the information signals 1720, 1722, 1724 and 1726 to the 40 vector modulators 1750 and 1752 through the DACs 1730, 1732, 1734 and 1736. In other embodiments, signals 1720, 1722, 1724 and 1726 are output to a single DAC as shown in Figures 18 and 18A. Figure 24 is a block diagram illustrating an example 2400 of a transfer function module implementing the process flow diagram 2300. In the example of Figure 24, the transfer function module 2400 (such as the module of transfer function 1716) receives the data signal from I and Q 2410, 45 such as signal 1710 in Figure 17. In one example, the data signal of I and Q 2410 includes the data components of I and Q of a baseband signal. In one example, the transfer function module 2400 samples the I and Q 2410 data signal according to a 2412 sampling clock. The sampled I and Q data signals are received by the component<figref>image65</figref> 2420 of the 2200 transfer function module. The 2420 component measures the quantities | <figref>image14</figref>| and |<figref>image14</figref>| of the sampled I and Q data signals. Based on the magnitudes of |<figref>image14</figref>| and of |<figref>image14</figref>| measured, component 2430 calculates the magnitude |<figref>image14</figref>| In an example, |<figref>image14</figref>| burst<figref>image14</figref>|2=| <figref>image14</figref>|2+| <figref>image14</figref>| 2. In parallel, component 2240 calculates the phase shift angle θ of the baseband signal. In an example, θ is such that <figref>image66</figref>, in which the sign of I and Q determine the quadrant of θ. The 2450 component receives the magnitude |<figref>image14</figref>| calculated from component 2430, and based on this calculates a phase shift angle ϕ between the first and second constant envelope constituent signals. In the example of Figure 24, the phase shift angle ϕ is illustrated as a function f3 |<figref>image14</figref>|) of 10 magnitude | <figref>image14</figref>| calculated This is further described in section 3.4.4. In parallel, component 2450 receives the phase shift angle calculated θ from component 2440. As functions of ϕ and θ, component 2450 then calculates the quadrature and phase amplitude information for the vector modulator inputs that generate the first and second constant envelope constituents. In one example, the quadrature and phase amplitude information that is supplied to the vector modulators is in accordance with the equations provided in (18). Component 2450 issues the calculated amplitude information to subsequent phases of the vector power amplifier. In one example, the output values ​​are output separately to digital to analog converters. As shown in the embodiment of Figure 17, for example, signals 1720, 1722, 1724 and 1726 are issued separately to DACs 1730, 1732, 1734 and 1736, respectively. In other embodiments, signals 1720, 20 1722, 1724 and 1726 are output to a single DAC as shown in Figures 18 and 18A. 3.4.4) Magnitude for Phase Shift Transformation The examples of f (| I |), f (| Q |) of Figure 20 and F (| R |) of Figures 22 and 24 will be described further below. In accordance with the disclosure herein, any periodic waveform that can be represented by a Fourier series and a Fourier transform can be broken down into two or more constant envelope signals. In the following two examples are provided for the sine and square waveforms. 3.4.4.1) Magnitude for Transformed Phase Shift for Sinusoidal Signals: Consider a complex envelope sinusoidal signal variable at time r (t). In the time domain, this can be represented as:<figref>image67</figref> where R (t) represents the envelope of the magnitude of the signal at time t, δ (t) represents the phase shift angle of the signal at time t, and ω represents the frequency of the signal in radians per second. 35 It can be verified that, at any moment of time t, the signal r (t) can be obtained by adding two envelope signals equal and constant or substantially equal and constant phase shifted in an appropriate manner. In other words, it can be shown that: <figref>image68</figref> for a phase shift angle ϕ (t) appropriately chosen between the two constant envelope signals 40. The phase shift angle ϕ (t) will be calculated as a function of R (t) in the description below. This is equivalent to the phase shift magnitude transform for sinusoidal signals.<figref>image69</figref> Using a sinusoidal trigonometric identity, equation (21) can be rewritten as: <figref>image70</figref> It is noted, from equation (22), that the signal r (t) is written as a sum of a phase component and a quadrature component. Therefore, the magnitude of envelope R (t) can be written as:<figref>image71</figref> Equation (23) relates the magnitude of envelope R (t) of the signal r (t) with the phase shift angle ϕ (t) between two constant envelope constituents of the signal r (t). The constant envelope constituents have an envelope magnitude equal to or substantially equal to A, which is typically normalized to 1. Conversely, from equation (23), the phase shift angle ϕ (t) can be written as a 10 function of R (t) as follows:<figref>image72</figref> Equation (24) represents the phase shift magnitude transform for the case of sinusoidal signals, and is illustrated in Figure 26. 3.4.4.2) Magnitude for Transformed Phase Shift for Square Wave Signals: 15 γ &lt; 1), and envelope magnitudes A1 and A2, respectively. Signal 2830 results from combination signals 2810 and 2820. According to the examples, signal 2830 will have a magnitude equal to or substantially equal to the product of signals 2810 and 2820. In other words, signal 2830 will have a magnitude of zero as long as any of signals 2810 or 2820 has a magnitude of zero, and a magnitude other than zero when both signals 2810 and 2820 have non-zero magnitudes. In addition, signal 2830 represents a pulse width modulated signal. In other words, the envelope magnitude of the signal 2830 is determined according to the pulse width of the signal 2830 over a period of the signal. More specifically, the envelope magnitude of signal 2830 is equal to or substantially equal to the area below the curve of signal 2830. Referring to Figure 28, signals 2810 and 2820 are shown displaced over time by in relation to another by a time shift t '. Equivalently, signals 2810 and 2820 are phase shifted relative to each other by a phase shift angle. <figref>image73</figref>radians Referring again to Figure 28, it is noted that the magnitude of envelope R of signal 2830, in Figure 28, is given by:<figref>image74</figref> Therefore, it can be deduced that ϕ is related to R according to: <figref>image75</figref><figref>image76</figref> It is noted, from equation (26), that R is at a maximum of γA1A2 when ϕ = 0. In other words, the envelope magnitude is at a maximum when the two constant envelope signals meet in phase with each other. In typical implementations, signals 2810 and 2820 are normalized and have an envelope magnitude equal to or substantially equal to 1. In addition, signals 2810 and 2820 typically have a service coefficient of 0.5. Therefore, equation (28) is reduced to: <figref>image77</figref> Equation (27) illustrates the phase shift magnitude transform for the case of square wave signals of normalized envelope magnitude equal or substantially equal. Equation (27) is illustrated in Figure 26. 3.4.5) Waveform Distortion Compensation In certain examples, phase shift magnitude transforms may not be implemented exactly as desired in theory or in the practice. In fact, there may be various factors that require adjustment or tuning of the calculated quantity for the phase shift transform for optimal (or, at least, improved) operation. In practice, amplitude and phase errors may exist in the vector modulation circuitry, gain and phase imbalances may occur in the branches of vector power amplifier, and there may be a distortion in the MISO amplifier itself that includes but not limited to errors that are introduced by direct combination, in a single circuit node, of the transistor outputs inside the MISO amplifier described in this document. Each of these factors will contribute, either individually or in combination, to emit the waveform distortions that result in deviations from the desired output signal r (t). When the output waveform distortion exceeds the system design requirements, a waveform distortion compensation may be required. Figure 25 illustrates the effect of a waveform distortion on a signal using a representation of a fasorial signal. In Figure 25, it represents a fasorial representation of a desired signal r (t). In the example of Figure 25, a waveform distortion may result in the actual output phasor varying with respect to ar (t)<figref>image14</figref> anywhere inside the region of fasorial error. An exemplary fasorial error region is illustrated in Figure 25 and is equal to or substantially equal to the maximum error vector magnitude. The fasores<figref>image14</figref>1 and <figref>image14</figref>two they represent examples of potential output phasors that deviate from the desired r (t). 30 According to some examples, waveform distortions can be measured, calculated or estimated during system manufacturing and / or in real time operation or not in real time. Figure 54A and Figure 55 are examples of procedures that can be used for correction and measurement of fasorial errors. These waveform distortions can be compensated or reduced at various points in the system. For example, a phase error between branch amplifiers can be adjusted by applying an analog voltage displacement to the vector modulation circuitry, within the transfer function, and / or using time feedback techniques. real or not in real time as shown in the system as an example illustrated in Figures 58, 59 and 60. Similarly, branch amplification imbalances can be adjusted by applying an analog voltage shift to the vector modulation circuitry, within the transfer function, and / or using real-time or non-real-time feedback techniques. in real time 40 as shown in figures 58, 59 and 60. In the system illustrated in Figures 58, 59 and 60, for example, a waveform distortion adjustment is performed, as illustrated in Figure 60, using the differential branch amplitude measurement circuitry 6024 and the differential branch phase measurement circuitry 6026, which provide a differential branch amplitude signal 5950 and a differential branch phase signal 5948, respectively. These signals are input into an A / D converter 5732 by means of the input signal selector 5946, with the values ​​generated by the A / D converter 5732 being entered into the digital control module 5602. The digital control module 5602 uses the values ​​generated by the 5732 A / D converter to calculate adjusted or offset values ​​to provide control voltages for the phase settings for the vector modulation circuitry 5922, 5924, 5926 and 5928 and control voltages for the amplitude settings for the gain balance control circuitry 6016. In Figure 58, these control voltages are illustrated using the gain balance control signal 5749 and the phase balance control signal 5751. The feedback approach described above also compensates for variations in process, temperature variations, IC packaging variations and circuit board variations by ensuring that phase and system amplitude errors remain with a specified tolerance. In section 4.1.2, additional measurement and error compensation techniques of additional feedback and feed in advance are described by way of example. <figref>image78</figref> In other examples, the measured, calculated or estimated waveform distortions are compensated in the transfer function phase of the power amplifier. In this approach, the transfer function is designed to take into account and correct measured, calculated and / or estimated waveform distortions. Figure 78 illustrates a mathematical deduction of the magnitude transform in phase shift in the presence of 5-phase and amplitude errors in the branches of the VPA. Equation (28) in Figure 78 takes into account both amplitude and phase errors in an exemplary embodiment. It is noted that R * sen (6) * t + δ) in Figure 78 may be representative of either<figref>image14</figref>1 O well <figref>image14</figref>two in figure 25, for example. Equation (28) assumes that the amplitudes A1 and A2 of the VPA branches may be different and that each branch may contain a phase error (ϕe1 (t) and ϕe2 (t)). For reference purposes, in a system theoretically perfect, A1 = A2 and ϕe1 (t) = ϕe2 (t) = 0. δ (t) is adjusted per quadrant based on the sign value of the input vectors I (t) and Q (t). In that sense, without any phase or amplitude error, the phasor corresponding to R * sen (ω * t + δ) is aligned with the phasor <figref>image14</figref>desired in Figure 25. In some examples, in practice, the amplitude and phase components of the phasor corresponding to R * sen (ω * t + δ) are compared with the phasor <figref>image14</figref>desired to generate phase error and system amplitude 15 deviations. These phase error and amplitude deviations from the phasor<figref>image14</figref>desired, as shown in figure 25, can be counted in the system transfer function. In an, A1 and A2 they can be substantially equalized and ϕe1 (t) and ϕe2 (t) can be minimized by properly adjusting the control inputs to the vector modulation circuitry. In one example, as illustrated in Figure 57, this is done by the digital control module, which provides, using digital to analog converters DAC_01, DAC_02, DAC_03 and 20 DAC_04, control inputs to the modulation circuitry vector. Therefore, given the fact that equations such as equation (28) can be used to calculate the resulting phasor at any time in time based on the values ​​of A1 and A2 and ϕe1 (t) and ϕe2 (t), it can make a modification or modifications of transfer function to compensate for system errors, and such modification or transfer function modifications will be apparent to those skilled in the relevant subject or subjects 25 based on the teachings contained herein. Section 4.1.2 describes exemplary procedures for generating error tables and / or mathematical functions to compensate for system errors. It will be apparent to those skilled in the relevant subject or field that these waveform distortion correction and compensation techniques can be implemented in the domains either digital or analog, and the implementation of such techniques will be apparent to those skilled in the art. relevant subject or subjects based on the teachings contained in this document. 3.5) Output phase One aspect of the disclosure herein is the sum of constituent signals in the output phase of a vector power amplifier (VPA). This is shown, for example, in Figure 7 in which the outputs of the PAs 770, 772, 774 and 776 are added together. This is similarly shown in Figures 8, 12, 13, 35, 17 and 18, for example. Several embodiments to combine the outputs of the VPAs are described herein. Although the following is described in the context of the VPAs, it should be understood that the following teachings apply, in general, to the coupling or sum of the outputs of any active device in any application. Figure 29 illustrates an example of a vector power amplifier output phase 2900. The output phase 2900 40 includes a plurality of vector modulator signals 2910 - {1, ... , n} which are introduced into a plurality of corresponding power amplifiers (PA) 2920 - {1, ..., n}. As described above, signals 2910 - {1, ..., n} represent constituent signals of a desired output signal of the vector power amplifier. In the example of Figure 29, the PA 2910 - {1, ..., n} amplify equally or substantially amplify the 45 input signals 2910 - {1, ... , n} to generate the amplified output signals 2930 - {1, ..., n}. The amplified output signals 2930 - {1, ..., n} are coupled to each other directly at the summation node 2940. According to the present example, the summation node 2940 does not include any coupling or isolation element, such as a power combiner circuit, for example. In the example of Figure 29, the sum node 2940 is a zero impedance (or almost zero impedance) lead wire. Therefore, unlike conventional systems 50 employing combination elements, the combination of the output signals according to the present example incurs a minimum loss of power. In another aspect, the output phase examples can be implemented using multi-input and single-output power amplifiers (MISO). In another aspect, the output phase examples can be controlled to increase the energy efficiency of the amplifier by controlling the output phase intensity according to the desired output power level. In the following, various output phase embodiments in accordance with the VPA embodiments of the present invention are provided in section 3.5.1. In section 3.5.2, the embodiments of output phase intensity shaping functions are presented, to increase the energy efficiency of certain VPA embodiments of the present invention. Section 3.5.3 describes embodiments of functions of output phase protection techniques that can be used for certain output phase embodiments of the present invention.<figref>image79</figref> 5 3.5.1) Output phase embodiments Figure 30 is a block diagram illustrating an example of the power amplifier (PA) output phase 3000. The output phase example 3000 includes a plurality of branches of PA 3005 - {1, ..., n}. The signals 3010 {1, .., n} that come from the respective vector modulators represent inputs for the output phase 3000. According to the present example, the signals 3010 - {1, ... , n} represent signals of envelope constituent 10 equal and constant or substantially equal and constant of a desired output signal of the power amplifier. The branches of PA 3005 - {1, ..., n} apply an amplification of equal or substantially equal power to the respective signals 3010 - {1, ..., n}. In one example, the level of power amplification through the branches of PA 3005 {1, ... , n} is adjusted according to a power level requirement of the desired output signal. In the example of Figure 30, each of the branches of PA 3005 - {1, ..., n} includes a power amplifier 3040 - {1, ..., n}. In other examples, excitation circuits 3030 - {1, ..., n} and pre-excitation circuits 3020 - {1, ..., n}, as illustrated in Figure 30, can also be added on a branch of PA before the power amplifier element. In the examples, the excitation circuits and the pre-excitation circuits are used as long as a required output power level cannot be achieved in a single amplification phase. 20 To generate the desired output signal, the outputs of the branches of PA 3005 - {1, ..., n} are coupled directly to the sum node 3050. The sum node 3050 provides little or no isolation between the outputs. coupled. In addition, the sum node 3050 represents a sum node relatively lossless. Consequently, a minimum power loss is incurred in the sum of the outputs of the PA 3040 - {1, .., n}. The output signal 3060 represents the desired output signal of the output phase 3000. In the example of Figure 25 30, the output signal 3060 is measured through a load impedance 3070. Figure 31 is a block diagram illustrating another output phase of power amplifier (PA) 3100. Similar to the example of Figure 30, output phase 3100 includes a plurality of branches of PA 3105 - {1, ..., n}. Each of the branches of PA 3105 - {1, ..., n} can include multiple power amplification phases that are represented by a pre-excitation circuit 3020 - {1, ..., n}, a circuit excitation 3030 - {1, ... , n} and the 3040 power amplifier - {1, ..., n}. The example of output phase 3100 further includes polarization impedances that are coupled at the output of each power amplification phase to provide polarization of that phase. For example, polarization impedances 3125 - {1, ..., n} and 3135 - {1, ... , n}, respectively, couple the pre-excitation circuit and excitation circuit phase outputs with the power supply or the independent polarization power supplies. Similarly, polarization impedance 3545 couples the PA phase outputs with the power supply or an independent polarization power supply. In accordance with the present example of the present invention, the polarization impedances represent optional components that can affect the efficiency but not necessarily the operation of the output phase example. Figure 32 is a block diagram illustrating another example of a power amplifier (PA) output phase 40 3200 according to the present invention. Similar to the example in Figure 30, the output phase 3200 includes a plurality of branches of PA 3205 - {1, ..., n}. Each of the branches of PA 3205 - {1, ..., n} can include multiple phases of power amplification that are represented by a pre-excitation circuit 3020 - {1, ..., n}, a circuit 3030 - {1, ..., n} and power amplifier 3040 - {1, ..., n}. The example of output phase 3200 also includes polarization impedances that are coupled at the output of each phase of power amplification to achieve proper polarization of that phase. In addition, the example of output phase 3200 includes the adaptation impedances that are coupled at the outputs of each power amplification phase to maximize power transfer from that phase. For example, adaptation impedances 3210 - {1, ... , n} and 3220 - {1, ..., n} are coupled, respectively, with the pre-excitation circuit and excitation circuit phase outputs. Similarly, the adaptive impedance 3240 is coupled at the PA phase output 50. It is noted that the adaptation impedance 3240 is coupled with the subsequent PA output phase to the sum node 3250. In the examples described above in Figures 30-32, the PA phase outputs are combined by direct coupling in a summation node. For example, in the example of Figure 30, the outputs of the branches of PA 3005 - {1, ..., n} are coupled together in the sum node 3050. The sum node 3050 is 55 a conducting wire. of almost zero impedance that provides minimal isolation between the coupled outputs. A similar output phase coupling is shown in Figures 31 and 32. It is noted that, in certain examples, the output coupling, as shown in the examples of Figures 30-32 or the examples described in Subsequently, in the following, you can use certain phase protection measures <figref>image80</figref> exit. These protection measures can be implemented in different phases of the PA branch. In addition, the type of protection measures required may be specific to the implementation of PA. An additional analysis of the output phase protection is provided in section 3.5.3. Figure 33 is a block diagram illustrating another output phase of power amplifier (PA) 3300 of 5 in accordance with an embodiment of the present invention. Similar to the example in Figure 30, the output phase 3300 includes a plurality of branches of PA 3305 - {1, ..., n}. Each of the branches of PA 3305 - {1, ..., n} can include multiple phases of power amplification that are represented by a pre-excitation circuit 3020 {1, ..., n}, a circuit of excitation 3030 - {1, ..., n} and the power amplifier 3040 - {1, ..., n}. The output phase embodiment 3300 may also include the polarization impedances 3125 - {1, ..., n}, 3135 - {1, ..., n} and 3145 10 that are coupled at the output of each phase of power amplification to achieve proper polarization of that phase. Additionally, the output phase embodiment 3300 may include adaptation impedances 3210 - {1, ..., n}, 3220 - {1, ... , n} and 3240 that are coupled at the output of each power amplification phase to maximize power transfer from that phase. In addition, the output phase embodiment 3300 receives an autopolarization signal 3310, from an autopolarization module 3340, which is coupled to the PA phase input of each branch of PA 3305 - {1, ..., n}. The selfpolarization module 3340 controls the polarization of the PA 3040 - {1, ..., n}. In one embodiment, the autopolarization signal 3340 controls the amount of intensity flow through the PA phase according to a desired output power level, and a signal envelope, of the output waveform. A further description of the operation of the autopolarization signal and the autopolarization module is provided in the following in section 3.5.2. twenty Figure 34 is a block diagram illustrating another exemplary power amplifier (PA) output phase 3400. Similar to the example in Figure 30, the output phase 3400 includes a plurality of branches of PA 3405 - {1, ..., n}. Each of the branches of PA 3405 - {1, ..., n} can include multiple power amplification phases that are represented by a pre-excitation circuit 3020 - {1, ..., n}, a circuit excitation 3030 {1, ... , n} and the power amplifier 3040 - {1, ..., n}. The output phase 3400 may also include the 25 polarization impedances 3125 - {1, ..., n}, 3135 - {1, ..., n} and 3145 that are coupled at the output of each amplification phase of power to achieve the desired polarization of that phase. Additionally, output phase 3400 may include adaptation impedances 3210 - {1, ..., n}, 3220 - {1, ... , n} and 3240 that are coupled at the output of each power amplification phase to maximize power transfer from that phase. In addition, the output phase 3400 includes a plurality of harmonic control circuit networks 3410 - {1, ..., n} 30 that are coupled to the PA phase input of each branch of PA {1, .. ., n}. The harmonic control circuit networks 3410 - {1, ... , n} may include a plurality of resistance, capacitive and / or inductive elements and / or active devices that are coupled in series or in parallel. According to an example, harmonic control circuit networks 3410 - {1, ..., n} provide harmonic control functions to control the output frequency spectrum of the power amplifier. In one example, the harmonic control circuit networks 3410 - {1, ... , n} are selected such that the transfer of energy to the fundamental harmonic in the summed output spectrum is increased while the harmonic content of the output waveform is decreased. An additional description of harmonic control is provided in the following in section 3.6. Figure 35 is a block diagram illustrating another exemplary power amplifier (PA) output phase 3500. The output phase 3500 represents a differential output equivalent of the output phase 3200 of Figure 32. In example 3500, the phase outputs of PA 3510 - {1, ..., n} are successively combined to result in two aggregate signals. The two aggregate signals are then combined through a load impedance, thereby making the output of the power amplifier represent the difference between the two aggregate signals. Referring to Figure 35, aggregate signals 3510 and 3520 are coupled to 45 through load impedance 3530. The output of the power amplifier is measured through load impedance 3530 as the voltage difference between nodes 3540 and 3550. According to example 3500, the maximum output of the power amplifier is obtained when the two aggregate signals are 180 degrees out of phase with respect to each other. Conversely, the minimum output power is obtained when the two aggregate signals are in phase in relation to each other. 50 Figure 36 is a block diagram illustrating another exemplary output phase 3600. Similar to the example in Figure 30, the output phase 3600 includes a plurality of branches of PA 3605 - {1, ..., n}. Each of the branches of PA {1, ... , n} may include multiple phases of power amplification that are represented by a pre-excitation circuit 3020 - {1, ..., n}, an excitation circuit 3030 - {1, ..., n}, and a power amplifier (PA) 3620 - {1, ..., n}. According to example 3600, the PA 3620 - {1, .., n} include switching power amplifiers. In the example of Figure 36, the power amplifiers 3620 - {1, ... , n} include the bipolar junction transistor (BJT) elements npn Q1, ..., Qn. The elements of BJT Q1, ..., Qn have common collector nodes. Referring to Figure 36, the collector terminals of the BJT elements Q1, ..., Qn are coupled together to provide the summation node 3640. The emitter terminals of the BJT elements Q1, ..., Qn is coupled with a ground node, while the base terminals of the elements of BJT Q1, ... , Qn provide input terminals to the PA phase. <figref>image81</figref> Figure 37 is an example (in relation to Figure 36) illustrating an output signal of the PA phase of Example 3600 in response to square wave input signals. For ease of illustration, a two-phase PA phase is considered. In the example of Figure 37, the square wave signals 3730 and 3740 are introduced, respectively, in the BJT elements 3710 and 3720. It is noted that, when any of the elements of 5 BJT 3710 or 3720 goes into conduction state, the sum node 3750 is shorted to ground. Therefore, when any of the input signals 3730 or 3740 is high, the output signal 3780 will be zero. In addition, the output signal 3780 will be high only when both input signals 3730 and 3740 are zero. According to this arrangement, the phase of PA 3700 performs a pulse width modulation, whereby the magnitude of the output signal is a function of the phase shift angle between the input signals. 10 The examples are not limited to implementations of BJT npn as described herein. One skilled in the art will appreciate, for example, that the embodiments of the present invention can be implemented using BJT pnp, CMOS, NMOS, PMOS, or other transistors. In addition, the embodiments can be implemented using GaAs and / or SiGe transistors, the transistor switching speed being a factor to be taken into account. 15 Referring again to Figure 36, it can be seen that while each of the PA 3620 - {1, ... , n) is illustrated using a single BJT notation, each PA 3620 - {1, ..., n} may include a plurality of transistors coupled in series. In the examples, the number of transistors included within each PA is adjusted according to a required maximum output power level of the power amplifier. In other examples, the number of transistors in the PA is such that the numbers of transistors in the pre-excitation circuit, the excitation circuit and the PA phases are adjusted to a geometric progression. Figure 38 illustrates an embodiment of exemplary PA 3800 in accordance with an embodiment of the present invention. The embodiment of PA 3800 includes a BJT 3870 element, a 3860 LC network and a 3850 bias impedance. The BJT 3870 element includes a plurality of BJT transistors Q1, ..., Q8 coupled in series. As illustrated in Figure 38, transistors BJT Q1, ..., Q8 are coupled to each other at their base, collector and emitter terminals. The collector terminal 3880 of the BJT 3870 element provides an output terminal for the PA 3800. The emitter terminal 3890 of the BJT element 3870 can be coupled with the substrate or with an emitter terminal of a preceding amplifier phase. For example, transmitter terminal 3890 is coupled with a transmitter terminal of a preceding excitation circuit phase. Referring to Figure 38, the LC 3860 network is coupled between the PA 3810 input terminal and the 3820 input terminal 30 of the BJT 3870 element. The LC 3860 network includes a plurality of capacitive and inductive elements. Optionally, a Harmonic Control Circuit network 3830 is also coupled to the input terminal 3820 of the BJT 3870 element. As described above, the HCC network 3830 provides a harmonic control function for control the output frequency spectrum of the power amplifier. 35 Referring again to Figure 38, the bias impedance 3850 couples the Iref 3840 signal with the input terminal 3820 of the BJT 3870 element. The Iref 3840 signal represents an autopolarization signal that controls the polarization of the BJT 3870 element according to a desired output power level, and signal envelope characteristics. It is noted that, in the embodiment of Figure 38, it is illustrated that the BJT 3870 element includes 8 transistors. 40 One skilled in the art can appreciate, however, that the BJT 3870 element may include any number of transistors as required to achieve the desired output power level of the power amplifier. In another aspect, the output phase embodiments can be implemented using multi-input and single-output power amplifiers (MISO). Figure 51A is a block diagram illustrating an exemplary MISO output phase embodiment 5100A. The output phase embodiment 5100A includes a plurality of vector modulator signals 5110 - {1, ..., n} that are input into the power amplifier (PA) of MISO 5120. As described above, signals 5110 - {1, ..., n} represent constant envelope constituents of output signal 5130 of the power amplifier. The MISO 5120 PA is a power amplifier with multiple inputs and a single output. The MISO 5120 PA receives and amplifies the 50 signals 5110 - {1, ..., n} providing a distributed multi-signal amplification process to generate the 5130 output signal. It is noted that MISO implementations, similar to that shown in Figure 51A, may extend similarly to any of the output phase embodiments described above. More specifically, any of the output phase embodiments of Figures 29-37 can be implemented using a MISO approach. Additional MISO embodiments will be provided in the following with reference to Figures 51B-I. It is noted that any of the embodiments described above may be implemented using any of the MISO embodiments that will be provided in the following. <figref>image82</figref> Referring to Figure 51A, the MISO 5120 PA may have any number of inputs as required by the substantially constant envelope decomposition of the complex envelope input signal. For example, in a two-dimensional decomposition, a two-input power amplifier can be used. In accordance with the embodiments of the present invention, building blocks are provided to create the MISO PAs for any number of entries. Figure 51B illustrates various MISO building blocks in accordance with an embodiment of the present invention. The PA of MISO 5110B represents a block of PA with two inputs and a single output. In one embodiment, the PA of MISO 5110B includes two branches of PA. The PA branches of the PA of MISO 5110B may be equivalent to any PA branch described above with reference to Figures 29-37, for example. The PA of MISO 5120B represents a PA block of 10 three inputs and a single output. In one embodiment, the PA of MISO 5120B includes three branches of PA. The PA branches of the PA of MISO 5120B can be equivalent to any AP branch described above with reference to Figures 29-37, for example. Referring again to Figure 51B, the MISO PAs 5110B and 5120B represent basic building blocks for any power amplifier with multiple inputs and a single output in accordance with the embodiments of the present invention. For example, the PA of MISO 5130B is a PA of four inputs and a single output, which can be created by coupling together the outputs of two PA blocks of two inputs and a single output, such as the PA of MISO 5110B, for example. This is illustrated in Figure 51C. Similarly, it can be verified that the MISO PA 5140B, a PA of n inputs and a single output, can be created from the basic building blocks 5110B and 5120B. twenty Figure 51D illustrates several embodiments of the two-input and single-output PA building block in accordance with the embodiments of the present invention. Embodiment 5110D represents an npn implementation of the two-input and single-output PA building block. Embodiment 5110D includes two npn transistors that are coupled to each other using a common collector node, which provides the output of the PA. A bias impedance (not shown) can be coupled between the common collector node and a supply node (not shown). Embodiment 5130D represents a pnp equivalent of embodiment 5110D. Embodiment 5130D includes two pnp transistors that are coupled to a common collector node, which provides the output of the PA. A mass impedance (not shown) can be coupled between the common collector node and a mass node (not shown). 30 Embodiment 5140D represents a complementary npn / pnp implementation of the two-input and single-output PA building block. Embodiment 5140D includes an npn transistor and a pnp transistor that are coupled to a common collector node, which provides the output of the PA. Referring again to Figure 51D, embodiment 5120D represents an NMOS implementation of the two-input and single-output PA building block. Embodiment 5120D includes two 35 NMOS transistors that are coupled to a common drain node, which provides the output of the PA. Embodiment 5160D represents a PMOS equivalent of embodiment 5120D. Embodiment 5120D includes two PMOS transistors that are coupled to a common drain node, which provides the output of the PA. Embodiment 5150D represents a complementary MOS implementation of the PA building block with two inputs and a single output. Embodiment 5150D includes a PMOS transistor and an NMOS transistor that are coupled to a common drain node, which provides the output of the PA. The two-input and single-output embodiments of Figure 51D can also be extended to create multi-input and single-output embodiments. Figure 51E illustrates several embodiments of multi-input and single-output PAs in accordance with the embodiments of the present invention. Embodiment 5150E represents an npn implementation of a multi-input and single-output PA. The embodiment 5150E includes a plurality of npn transistors that are coupled to each other using a common collector node, which provides the output of the PA. A bias impedance (not shown) can be coupled between the common collector node and a supply voltage (not shown). It is noted that a PA of n inputs and a single output according to embodiment 5150E can be obtained by coupling additional npn transistors to the realization of a PA building block of two inputs 50 and a single output 5110D. Embodiment 5170E represents a pnp equivalent of embodiment 5150E. Embodiment 5170E includes a plurality of pnp transistors that are coupled to each other using a common collector node, which provides the output of the PA. A mass impedance (not shown) can be coupled between the common collector node and a mass node (not shown). It is noted that a PA of n inputs and a single output in accordance with embodiment 5170E can be obtained by coupling additional pnp transistors to the construction of a two-input PA building block and a single output 5130D. <figref>image83</figref> Embodiments 5110E and 5130E represent complementary npn / pnp implementations of a multi-input and single-output PA. Embodiments 5110E and 5130E may include a plurality of npn and / or pnp transistors that are coupled to each other using a common collector node, which provides the output of the PA. It is noted that a PA of n inputs and a single output in accordance with embodiment 5110E 5 can be obtained by coupling additional npn and / or pnp transistors to the construction of a two-input PA building block and one only output 5140D. Similarly, a PA of n inputs and a single output according to embodiment 5130E can be obtained by coupling additional npn and / or pnp transistors to the realization of a two-input and single-unit PA building block exit 5130D. 10 Embodiment 5180E represents a PMOS implementation of a multi-input and single-output AP. Embodiment 5180E includes a plurality of PMOS transistors that are coupled to each other using a common drain node, which provides the output of the PA. It is noted that a PA of n inputs and a single output according to embodiment 5180E can be obtained by coupling additional NMOS transistors to the realization of a two-input PA building block and a single output 5160D. fifteen Embodiment 5160E represents an NMOS implementation of a multi-input and single-output AP. Embodiment 5160E includes a plurality of NMOS transistors that are coupled to each other using a common drain node, which provides the output of the PA. It is noted that a PA of n inputs and a single output according to embodiment 5160E can be obtained by coupling additional PMOS transistors to the realization of a two-input PA building block and a single 5120D output. 20 Achievements 5120E and 5140E, complementary MOS implementations of a multi-input and single-output PA. Embodiments 5120E and 5140E include a plurality of npn and pnp transistors that are coupled to each other using a common drain node, which provides the output of the PA. It is noted that a PA of n inputs and a single output in accordance with embodiment 5120E can be obtained by coupling additional NMOS and / or PMOS transistors with the two-input PA building block and a single output 5150D Similarly, a PA of n inputs and a single output according to embodiment 5140E can be obtained by coupling additional NMOS and / or PMOS transistors with the two-input PA building block and a single output 5160D . Figure 51F illustrates additional multi-input and single-output embodiments in accordance with the embodiments of the present invention. Embodiment 511F represents a complementary npn / pnp 30 implementation of a multi-input and single-output PA. Embodiment 5110f can be obtained by iteratively coupling the embodiments of the PA 5140D building block together. Similarly, embodiment 5120F represents a complementary implementation of NMOS / PMOS equivalent of a multi-input and single-output AP. Embodiment 5120F can be obtained by iteratively coupling each other with the embodiments of the PA 5150D building block. 35 It is noted that each of the embodiments of multiple inputs and a single output that have been described above may correspond to a single or multiple branches of a PA. For example, with reference to Figure 29, any of the examples of multiple inputs and a single output can be used to replace a single or multiple PA 2920 - {1, ..., n}. In other words, each of the PA 2920 - {1, ..., n} can be implemented using any of the examples of multiple inputs and a single PA output that have been described above or with a PA of a single input and a single output as shown in Figure 29. It is further noted that each of the transistors shown in the embodiments of Figures 51D, 51E and 51F can be implemented using a series of transistors as shown in the exemplary embodiment of Figure 38, for example. Figure 51G illustrates additional embodiments of the multi-input and single-output PA building blocks. Embodiment 5110G illustrates an embodiment of the two-input and single-output PA building block. Embodiment 5110G includes two branches of PA, each of which can be implemented in accordance with embodiments of a single-input and single-output or multi-input PA and a single output as described in what has been described. precedes. In addition, embodiment 5110G illustrates an optional 5112G polarization control signal that is coupled with the two branches of the PA embodiment. The polarization control signal 5112G is optionally employed in embodiment 5110G based on the specific implementation of the PA branches. In certain implementations, a polarization control will be required for proper operation of the AP. In other implementations, a polarization control is not required for proper operation of the PA, but can provide improved PA energy efficiency, an output circuit protection or an ignition current protection. Referring again to Figure 51G, embodiment 5120G illustrates an embodiment of the three-input and single-output PA building block. Embodiment 5120G includes three branches of PA, each of which can be implemented according to embodiments of a single-input and single-output or multi-input PA and a single output as described in what has been described. precedes. In addition, embodiment 5120G illustrates an optional 5114G polarization control signal that is coupled with the branches of the PA embodiment. The 5114G polarization control signal is optionally employed in embodiment 5120G based on the specific implementation of the PA branches. In certain implementations, a polarization control will be required for proper operation of the AP. In other implementations, a control of<figref>image84</figref> 5 polarization is not required for proper operation of the PA, but it can provide improved PA energy efficiency. Figure 51H illustrates an additional exemplary embodiment 5100H of the two-input and single-output PA building block. Embodiment 5100H includes two branches of PA, each of which can be implemented according to embodiments of a single-input and single-input or multi-input PA and 10 of a single output as described herein. foregoing. Embodiment 5100H further includes optional elements, which are illustrated using dashed lines in Figure 51H, which can be further employed in embodiments of embodiment 5100H. In one embodiment, the PA 5100H building block may include an excitation circuit phase and / or a pre-excitation circuit phase in each of the PA branches as shown in Figure 51H. Process detectors can also be optionally used to detect process and temperature variations in the excitation circuit and / or pre-excitation circuit phases of the PA. In addition, an optional polarization control can be provided to each of the pre-excitation circuit, excitation circuit and / or PA phases of each branch of the PA embodiment. A polarization control can be provided to one or more of the phases based on the specific implementation of that phase. In addition, a polarization control may be required for certain implementations, while this may optionally be used in others. Figure 51I illustrates a further exemplary embodiment 5100I of a multi-input and single-output PA. Embodiment 5100I includes at least two branches of PA, each of which can be implemented in accordance with embodiments of a single-input and single-output or multi-input PA and a single output as described. in the foregoing. Embodiment 5100I further includes optional elements 25 that can be further employed in embodiments of embodiment 5100I. In one embodiment, the PA may include excitation circuit and / or pre-excitation circuit phases in each of the PA branches as shown in Figure 51I. Process detectors can also optionally be used to detect process and temperature variations in the excitation circuit and / or pre-excitation circuit phases of the PA. In addition, an optional polarization control can be provided to each of the phases of pre-excitation circuit, excitation circuit and / or PA of each branch of the PA embodiment. A polarization control can be provided to one or more of the phases based on the specific implementation of that phase. In addition, a polarization control may be required for certain implementations, while this may optionally be used in others. 3.5.2) Output Phase Intensity Control - Autopolarization Module 35 The following describes an output phase and current control and polarization phase control techniques for optional pre-excitation circuit and excitation circuit . In certain examples, the output phase intensity control functions are used to increase the output power phase efficiency of an exemplary vector power amplifier (VPA). In other examples, the output phase intensity control is used to provide output phase protection with respect to excessive voltages and intensities that is further described in section 3.5.3. In the embodiments, the output phase intensity control functions are performed using the autopolarization module described above with reference to Figure 33. A description of the operation of the autopolarization module in performing these intensity control functions is also presented in the following in accordance with an embodiment of the present invention. The energy efficiency of the output phase of a VPA can be increased by controlling the output phase intensity of the VPA as a function of the output power and the envelope of the output waveform. Figure 37 illustrates a partial schematic diagram of a Multi Input amplifier and a Single Output that is composed of two NPN transistors with input signals S1 and S2. When S1 and S2 are designed to be substantially constant envelope signals and substantially similar waveforms, any time-varying complex envelope output signal can be created in circuit node 3750 by changing the phase phase relationship. S1 and S2. Figure 39 illustrates an example time-varying complex envelope output signal 3910 and its corresponding envelope signal 3920. It is noted that signal 3910 undergoes an inversion of the phase in an instant of time to. Correspondingly, the envelope signal 3920 experiences a zero crossing at the instant to. The output signal 3910 exemplifies the output signals according to typical wireless signaling schemes such as W -CDMA, QPSK, and OFDM, for example. Figure 40 illustrates the output phase intensity of diagram figure 37 by way of example in response to output signal 3910. The Isalida 4010 signal represents the output phase intensity without an autopolarization control and the Isalida 4020 signal represents the output phase intensity with an autopolarization control. <figref>image85</figref> Without an autopolarization control, as the phase shift between S1 and S2 changes from 0 to 180 degrees, the Isalida output intensity increases. With an autopolarization control, the Isalida output intensity decreases and can be minimized when it is at, or near, that of Figure 39. It is noted that the Isalida 4020 signal varies as a function of the envelope signal 3920. Therefore, the output 4020 is at the maximum when a maximum output power is required, but decreases as the required output power drops. In particular, the Isalida 4020 signal approaches zero as the associated output power tends to zero. Accordingly, one skilled in the art will appreciate that the output phase intensity control results in significant power savings and increases the energy efficiency of the power amplifier. 10 The output phase intensity control can be implemented according to a variety of functions. The output phase intensity can be shaped to match the desired output power of the amplifier. In such an example, the output phase intensity is a function that is calculated from the envelope of the desired output signal, and the energy efficiency will increase. Figure 41 illustrates exemplary self-polarization output phase intensity control functions 4110 and 4120. Function 4110 may represent a function of the output power and the signal envelope as described above. On the other hand, function 4120 may represent a simple shaping function that tends to a minimum value for a predetermined amount of time when the output power is below a threshold value. Accordingly, functions 4110 and 4120 represent two cases of the autopolarization output phase intensity control functions with the autopolarization control signal 2010 which results in the Isalide response 4130 and the autopolarization control signal 4120. which results in the response of Isalida 4140. The disclosure in this document, however, is not limited to those two examples. The output phase autopolarization intensity control functions can be designed and implemented to facilitate the efficiency and intensity consumption requirements of a particular vector power amplifier design. 25 In the implementation, there are several approaches to perform the output phase intensity control. In some examples, the output phase intensity shaping is performed using the autopolarization module. The autopolarization module is illustrated as the autopolarization circuitry 714 and 716 in the embodiments of Figures 7 and 8. Similarly, the autopolarization module is illustrated as the autopolarization circuitry 1218 in the embodiments of Figures 12 and 13, and as the autopolarization circuitry 1718 in the embodiments of 30 figures 17 and 18. The output phase intensity control using autopolarization is depicted in the process flow diagram 4800 of the example of Figure 48. The procedure begins at step 4810, which includes receiving an output power and signal envelope information. output of a desired output signal from a vector power amplifier (VPA). In some examples, implementing the output phase intensity control using autopolarization requires a priori knowledge of the desired output power of the amplifier. The output power information can be found in the form of phase and envelope information. For example, in the embodiments of Figures 7, 8, 12, 13, 17 and 18, the output power information is included in the data components of I and Q that are received by performing VPA. In other embodiments, the output power information can be received or calculated using other means. 40 Step 4820 includes the calculation of a signal according to the output envelope signal information. In the examples, an autopolarization signal is calculated as a function of some measure of the desired output power. For example, the autopolarization signal can be calculated as a function of the envelope magnitude of the desired output signal. Referring to the embodiments of figures 7, 8, 12, 13, 17 and 18, for example, it is noted that the autopolarization signal (signals 715 and 717 in figures 7 and 8, signal 45 1228 in figures 12 and 13, and signals 1728 in Figures 17 and 18) are calculated according to the data components of I and Q received from a desired output signal. In certain embodiments, such as those described in Figures 7, 8, 12, 13, 17 and 18, the autopolarization signal is calculated by an autopolarization module, providing output power information. In other examples, the autopolarization signal can be calculated by means of the I or Q 50 data transfer function module or modules of the VPA. In such examples, an autopolarization module may not be required in the implementation. In the examples, the data transfer function module of I and Q calculates a signal, emits the signal to a DAC whose output signal represents the autopolarization signal. Step 4830 includes the application of the signal calculated in an output phase of the VPA, thereby controlling an intensity of the output phase in accordance with the output power of the desired output signal. In the 55 examples, step 4830 includes the coupling of the autopolarization signal at the PA phase input of the VPA. This is illustrated, for example, in the embodiments of Figures 33 and 42 in which the autopolarization signal 3310 is coupled to the PA phase input of the VPA embodiment. In these embodiments, the autopolarization signal 3310 controls the polarization of the PA phase transistors according to the output power of the desired output signal of the VPA embodiment. For example, the autopolarization signal 3310 may result in the PA phase transistors operating in a cut-off state when the desired output power is<figref>image86</figref> minimum or almost zero, thereby extracting little or no output phase intensity. Similarly, when a maximum output power is desired, the autopolarization signal 3310 can polarize the PA phase transistors to operate in the switching mode class C, D, E, etc., the autopolarization signal 3310 also it may result in the PA phase transistors or the FETs operating in the direct or reverse polarized states according to the output power, and the desired signal envelope characteristics. In other examples, step 4830 includes coupling the autopolarization signal using polarization impedances at the PA phase input and, optionally, the inputs of the excitation circuit and / or pre-circuit phases. VPA excitation. Figures 38 and 43 illustrate such embodiments. For example, in the embodiment of Figure 38, the bias impedance 3850 couples the self-polarizing signal Iref 3840 with the input terminal 3820 of the BJT element 3870. The BJT element 3870 represents the PA phase of a branch of PA of an exemplary embodiment of VPA. Similarly, in the example of Figure 43, the autopolarization signal 4310 is coupled with transistors Q1, ..., Q8 through the corresponding polarization impedances Z1, ..., Z8. Transistors Q1, ..., Q8 represent the PA phase of a branch of an exemplary VPA. The embodiments for implementing the autopolarization circuitry described above will be provided in the following. Figure 27 illustrates three embodiments 2700A, 2700B and 2700C for implementing the autopolarization circuitry. These embodiments are provided for illustrative purposes, and are not limiting. Other embodiments will be apparent to those skilled in the art or subjects based on the teachings contained herein. In embodiment 2700A, the autopolarization circuitry 2700A includes a transfer function module of 20 autopolarization 2712, a DAC 2714, and an optional interpolation filter 2718. The autopolarization circuitry 2700A receives a data signal of I and Q 2710 . The autopolarization transfer function module 2712 processes a received I and Q 2710 data signal to generate an appropriate polarization signal 2713. The autopolarization transfer function module 2712 issues the polarization signal 2713 to the DAC 2714. The DAC 2714 is controlled by a DAC 2716 clock that can be generated in the 2712 autopolarization transfer module. The DAC 2714 converts the polarization signal 2713 into an analog signal, and outputs the analog signal to the interpolation filter 2718. The interpolation filter 2718, which also serves as an antisolape filter, forms the output of the DAC to generate the autopolarization signal. 2720, which is illustrated as Polarization A in embodiment 5112G. The autopolarization signal 2720 can be used to polarize the PA phase and / or the excitation circuit phase, and / or the pre-excitation circuit phase of the amplifier. In one embodiment, the autopolarization signal 2720 may have various other autopolarization signals calculated therefrom to polarize different phases within the PA phase. This can be done using an additional circuitry not included in embodiment 2700A. In contrast, embodiment 2700B illustrates an embodiment of the autopolarization circuitry in which multiple autopolarization signals are calculated within the autopolarization circuitry. As shown in embodiment 2700B, circuit networks 2722, 2726 and 2730, which are illustrated as circuit networks A, B and C in embodiment 2700B, are used to obtain autopolarization signals 2724 and 2728 from of the 2720 autopolarization signal. Autopolarization signals 2720, 2724 and 2728 are used to polarize different amplification phases. Embodiment 2700C illustrates another embodiment of the autopolarization circuitry in which multiple autopolarization signals are generated independently within the 2712 autopolarization transfer function module. In embodiment 2700C, the autopolarization transfer function module 2712 generates multiple polarization signals according to a data signal of I and Q 2710 received. Polarization signals may or may not be related. The autopolarization transfer function module 2712 emits the polarization signals generated to subsequent DACs 2732, 2734 and 2736. DAC 2732, 2734 45 and 2736 are controlled by DAC clock signals 2733, 2735 and 2737, respectively. DAC 2732, 2734 and 2736 convert the received polarization signals into analog signals, and emit the analog signals to the optional interpolation filters 2742, 2744 and 2746. The interpolation filters 2742, 2744 and 2746, which also serve as filters antisolape, they conform the outputs of the DACs to generate the autopolarization signals 2720, 2724 and 2728. Similar to embodiment 2700B, the autopolarization signals 2720, 2724 and 2728 are used to polarize different amplification phases such as the pre-excitation circuit, the excitation circuit and the PA. As noted above, the embodiments of the autopolarization circuitry according to the present invention are not limited to those described in embodiments 2700A, 2700B and 2700C. One skilled in the art will appreciate, for example, that the autopolarization circuitry can be expanded to generate any number of polarization control signals as required to control the polarization of several amplification phases, and not just three as shown in embodiments 5200B and 5200C, for example. 3.5.3) Output Phase Protection As described above, the examples of the output phase are of maximum energy efficiency as a result of being able to directly couple the outputs in the PA phase without using a combination element. or of any isolation. Certain examples of output phase in certain circumstances and / or applications, however, may require additional special output phase protection measures in order to support such direct coupling approach. This may be the case, for example, for the output phase embodiments such as 5110D, 5120D, 5130D, 5160D, 5150E, 5160E, 5170E and 5180E which are illustrated in the figures<figref>image87</figref> 5 51D and 51E. It is noted that, in general, the complementary output phase examples, such as embodiments 5140D, 5150D, 5110E, 5120E, 5130E and 5140E of Figures 51D and 51E, do not require (but may optionally use) same output phase protection measures that will be described in this document in this section. In the following, output phase protection measures and examples to support such measures are provided. 10 In one aspect, transistors of different branches of a PA phase in general should not be simultaneously in opposite operating states for prolonged periods of time. Following a restart or ignition without any input being supplied to the final PA phases, the transients within the PA branches may result in this mode taking place resulting in the PA phase transistors being damaged. , potentially, to each other, or to damage the circuit elements that are connected to the output. Accordingly, the examples of the present invention further restrict the autopolarization module to limit the output intensity in the PA phase. In another aspect, it may be desired to ensure that the autopolarization module limits the output voltages below the breakdown voltage specification of the PA phase transistors. Accordingly, in the embodiments of the present invention, such as that illustrated in Figure 42 for example, a feedback element 4210 is coupled between the common collector node of the PA phase and the autopolarization module. The feedback element 4210 monitors the collector voltage based on the PA phase transistors, and can restrict the autopolarization signal as necessary to protect the transistors and / or circuit elements. One skilled in the art will appreciate that other output phase protection techniques can also be implemented. In addition, exit phase protection techniques may be implementation specific. For example, depending on the type of PA phase transistors (npn, pnp, NMOS, PMOS, npn / pnp, NMOS / PMOS), different protection functions may be required. 3.6) Harmonic Control An underlying principle for each branch AP is to maximize the transfer of power to a fundamental harmonic of the output spectrum. Typically, each branch AP can be multi-phase, resulting in a harmonically rich output spectrum. In one aspect, the transfer of real power is maximized for the fundamental harmonic. In another aspect, for non-fundamental harmonics, the real power transfer is minimized while the imaginary power transfer can be tolerated. Harmonic control can be performed in a variety of ways. In one example, the real power transfer over the fundamental harmonic is maximized by means of the wave formation of the PA phase input signals. In practice, various factors play a role in determining the optimal waveform that results in a maximum real power transfer over the fundamental harmonic. Example 3400, described above, represents an example that uses the wave formation of the PA phase input signals. In example 3400, a plurality of harmonic control circuitry networks (HCC) 3410 - {1, ... , n} are coupled to the PA phase input of each branch of 40 PA {1, ..., n}. HCC 3410 networks - {1, ..., n} have the effect of the wave formation of the PA phase inputs, and are typically selected in order to maximize the transfer of real power to the fundamental harmonic of the spectrum of added output. According to the examples disclosed herein, the wave formation can be used to generate variations of various waveforms in terms of harmonics. In other examples, as may be apparent to one skilled in the art, wave formation 45 may be performed in the pre-excitation circuit and / or excitation circuit phase. In another example, harmonic control is achieved by means of the wave formation of the PA phase output. Figure 43 illustrates an exemplary phase of PA 4300. In example 4300, the autopolarization signal 4310 is coupled with transistors Q1, ..., Q8 through the corresponding polarization impedances Z1, ..., Z8. It is noted that, when the impedances Z1, ..., Z8 have different values, transistors Q1, ... , Q8 have different 50 polarization points and can go into a driving state at different times. This polarization approach of transistors Q1, ..., Q8 is referred to as a step polarization. It is noted that, using a stepped polarization, the PA output waveform can be shaped in a variety of ways depending on the values ​​assigned to polarize the impedances Z1, ..., Z8. Harmonic control using a stepped polarization is depicted in the process flow diagram 4900 55 of the example of Figure 49. The procedure begins in step 4910, which includes the coupling of an input signal into the first ports of a plurality. of transistors of a switching phase of power amplifier (PA). In the example of Figure 43, for example, step 4910 corresponds to the coupling of the PA_ENTRADA signal 4310 at the base terminals of the plurality of transistors Q1, ..., Q8. <figref>image30</figref> Step 4920 includes the coupling of a plurality of impedances between the first ports of the plurality of transistors and a polarization signal. In the example of Fig. 43, for example, step 4920 is achieved by coupling the impedances Z1, ..., Z8 between the base terminals of the respective transistors Q1, ..., Q8 and the Iref signal. In one example, the values ​​of the plurality of impedances are selected to give rise to a stepped switching in time of the input signal, thereby forming as for the harmonics an output signal of the PA phase. In the examples, a multi-stage stepped output can be generated by selecting multiple values ​​other than the plurality of impedances. In other examples, switching is achieved by selecting the plurality of impedances to have an equal or substantially equal value. 10 Figure 44 illustrates an exemplary waveform PA output using a stepwise polarization approach in two phases. In a two-phase step polarization approach, a first set of PA transistors goes into conduction state first before a second set enters conduction state. In other words, polarization impedances adopt two different values. Waveform 4410 represents an input waveform in the PA phase. Waveform 4420 represents the PA output with a waveform according to a two-phase step polarization. It is noted that the output waveform 4420 tilts twice as it transitions from 1 to 0, which corresponds to the first and second sets of transistors going into a conductive state in succession. In accordance with the examples disclosed herein, a variety of multi-step phased polarization approaches can be designed. The polarization impedance values ​​can be fixed 20 or variable. In addition, the polarization impedance values ​​can be the same or substantially the same, different, or adjusted according to a variety of permutations. For example, by referring to the example in Figure 43, an exemplary permutation could establish Z1 = Z2 = Z3 = Z4 and Z5 = Z6 -Z7 = Z8, which results in a two-stage step polarization. 3.7) Power Control 25 The examples of vector power amplification disclosed herein provide, intrinsically, a mechanism for performing output power control. Figure 45 illustrates an approach to exemplify power control. In figure 45, the fasores<figref>image14</figref> 1 and <figref>image14</figref>1 represent the upper and lower constituents of a first fasor <figref>image14</figref>1. <figref>image14</figref>1 and <figref>image14</figref>1 they are of constant magnitude and move symmetrically in phase in relation to <figref>image14</figref><figref>image14</figref><figref>image14</figref>1 a phase shift angle <figref>image14</figref><figref>image14</figref><figref>image14</figref><figref>image14</figref>. 30 Fasors 2 and 2 represent the upper and lower constituents of a second fasor 2. 2 and 2 are of constant magnitude and move symmetrically in phase in relation to<figref>image14</figref>two An angle of phase displacement. <figref>image88</figref> It is observed, from figure 45, that <figref>image14</figref><figref>image89</figref><figref>image14</figref>1 and <figref>image14</figref>two They are in phase one in relation to another and only differ in their magnitude. In addition, 2 and 2 move in phase equally or substantially equally in relation to<figref>image14</figref>1 and <figref>image14</figref>1, respectively. Accordingly, it can be deduced that, according to one example, the magnitude of a signal can be manipulated without varying its phase shift angle by equally or substantially equal displacement of its constituent signals. According to the previous observation, the output power control can be carried out by imposing restrictions on the phase shift angle of the constituent signals of a desired output signal 40. Referring to Figure 45, for example, by restricting the range of values ​​that the phase shift angle can adopt<figref>image14</figref>, restrictions of magnitude may be imposed on the phasor <figref>image14</figref>1. According to the examples disclosed herein, a maximum output power level can be achieved by imposing a minimum phase shift angle condition. For example, referring to Figure 45, by adjusting a condition such that<figref>image90</figref>, the magnitude of <figref>image91</figref> fasor <figref>image14</figref>1 It is restricted not to exceed a certain maximum level. Similarly, a maximum phase shift angle condition imposes a minimum magnitude level requirement. In another aspect of the power control, the output power resolution is defined in terms of a step size of increment or decrement of minimum power. According to an example disclosed in this document, the output power resolution can be implemented by defining a minimum step angle of step size. Accordingly, the phase offset angle values ​​are adjusted according to a range of discrete values ​​having a previously determined step size. Figure 46 illustrates an exemplary phase shift angle spectrum, whereby the phase shift angle <figref>image14</figref>it is adjusted according to a previously determined range of values ​​that has a minimum step escal step. One skilled in the art will appreciate that a variety of power control schemes can be implemented in a manner similar to that of the techniques described above. In other words, several power control algorithms can be designed, in accordance with the examples disclosed herein, by adjusting corresponding restrictions on the angle values ​​of phase shift. It is also evident, based on the above description of the data transfer functions, that power control schemes can naturally be incorporated into a transfer function implementation. 3.8) Exemplary vector power amplifier embodiment Figure 47 illustrates an example 4700 of a vector power amplifier according to the present invention. 20 Example 4700 is implemented according to the Direct Cartesian 2 Branch VPA procedure. Referring to Fig. 47, signals 4710 and 4712 represent the incoming signals from a transfer function phase. The transfer function phase is not shown in Figure 47. Block 4720 represents a quadrature generator that, optionally, can be implemented in accordance with the examples disclosed herein. Quadrature generator 4720 generates clock signals 4730 and 25 4732 to be used by vector modulators 4740 and 4742, respectively. Similarly, signals 4710 and 4712 are introduced into vector modulators 4740 and 4742. As described above, the vector modulators 4740 and 4742 generate constant envelope constituents that are subsequently processed by a PA phase. In example 4700, the PA phase is multi-phase, whereby each PA branch includes a pre-excitation circuit phase 4750-4752, an excitation circuit phase 4760-4762 and an amplifier phase of power 4770-4772. Figure 47 further illustrates the autopolarization signals 4774 and 4776 and terminals 4780 and 4782 for coupling networks and harmonic control circuitry. The terminal node 4780 represents the output terminal of the vector power amplifier, and is obtained by a direct coupling of the outputs of the two PA branches. 35 4. Exemplary Additional Implementations and Implementation 4.1) Overview This exemplary VPA implementations will be provided in this section. The advantages of these VPA implementations will be appreciated by those skilled in the art based on the teachings in this document. The inventors of the present invention will briefly describe in the following some of these advantages before presenting in more detail exemplary VPA implementations. 4.1.1) Output Power Control and Energy Efficiency Exemplary VPA implementations enable several layers of functionality to perform power control and / or to control energy efficiency using circuitry inside the VPA. Figure 52 illustrates this functionality at a high level using an embodiment of MISO 5200 VPA. The MISO 45 5200 VPA embodiment is a two-input and single-output VPA with optional excitation circuit and preexcitation circuit phases in each branch of the VPA. As in some previously described embodiments, the input bias current or voltage for each amplification phase (for example, the pre-excitation circuit phase, the excitation circuit phase, etc.) of the VPA it is controlled using a polarization signal (also referred to as autopolarization in other embodiments). In embodiment 5200, the separate polarization C, Polarization B and Polarization A 50 polarization signals are coupled with the pre-excitation circuit, excitation circuit and PA phases, respectively, of the VPA. Additionally, the implementation of VPA 5200 includes power supply signals (the VS excitation of the pre-excitation circuit, the VSUMINIST of the excitation circuit and the VSUMINIST of the output phase) that are used to power the respective phases of the VPA. In embodiments, these power supply signals are generated using some<figref>image92</figref> voltage controlled power supplies and can additionally be used to polarize their respective amplification phases, thereby providing additional functionality to control the overall energy efficiency of the VPA and to perform power control, as well as other functions of the VPA. For example, when controlled independently, the power supply signals and the polarization signals can be used to drive different amplification phases of the VPA at different power supply voltages and polarization points, enabling a wide dynamic range of output power for the VPA. In embodiments, voltage controlled power supplies can be implemented as continuously variable supplies such as voltage controlled switching supplies that provide variable voltage supplies at the appropriate amplification phase. In other embodiments, the voltage controlled power supply can be implemented by using switches to provide different power supply voltages. For example, a power supply of VPA output phase and / or optional excitation circuit phases and / or optional pre-excitation circuit phases could be switched between 3.3V, 1.8V and 0V depending on the desired operating parameters. 4.1.2) Compensation and / or Error Correction 15 Exemplary VPA implementations provide different approaches to monitor and / or compensate for errors in the VPA. These errors may be due, among other factors, to process and / or temperature variations in the VPA, to amplitude and phase errors in the vector modulation circuitry, to gain and phase imbalances in the branches of the VPA, and distortion in the MISO amplifier (see, for example, section 3.4.5 above). In the previously described VPA embodiments, part of this functionality was performed in the process detector circuitry (for example, the process detector 792 in Figure 7A, the process detector 1282 in Figure 12, the detector of process 1772 in figure 17). These approaches can be classified as forward feeding, feedback and forward feeding / hybrid feedback techniques, and can be implemented in a variety of ways as will be further analyzed in the following sections describing exemplary VPA implementations. A conceptual description of these supervisory and error compensation approaches will be provided below. Figures 54A and 54B are block diagrams that illustrate feed feeding techniques at a high level to compensate for errors in a VPA. Advance feeding techniques depend on a priori knowledge of the expected errors in the VPA in order to previously compensate for these errors within the VPA. Therefore, feed-in-advance techniques include an error measurement phase (which is usually performed in a test and characterization procedure) and a prior compensation phase that uses error measurements. Figure 54A illustrates a 5400A procedure for generating an error function or table describing the expected errors in the I data and the Q data at the output of the VPA (error measurement phase). Such errors are usually due to imperfections in the VPA. The 5400A procedure is usually performed in a test laboratory before finalizing the VPA design, and includes measuring at the output of a receiver values ​​of I and Q that correspond to a range of values ​​of I and Q at the entrance of the VPA. In general, the input I and Q values ​​are selected to generate a representative range of the polar space of 360 degrees (for example, the values ​​of I and Q can be selected with a uniform separation of 30 degrees). Subsequently, the error differences between the input I and Q values ​​and the output I and Q values ​​are calculated. For example, after measuring I and Q at the receiver output for a particular set of input values ​​of I and Q, a comparison circuitry calculates as Ierror and Qerror the differences in the I data and the Q data between the I and Q values ​​of input and the I and Q values ​​of receiver output. Ierror and Qerror represent the expected errors in I and Q at the VPA output for the particular set of input values ​​of IydeQ. In one example, the receiver is integrated with the VPA, or is provided by an external calibration and / or testing device. Alternatively, the receiver is the receiver module in the device that uses the VPA (for example, the receiver in a cell phone). In this alternative example, the VPA error table and / or feedback information can be generated by this receiver module in the device. The calculated Ierror and Terror values ​​are used to generate a function or error table representative of the expected I and Q errors for various I and Q input values. In embodiments, the Ierror and Qerror values calculated are additionally interpolated to generate error values ​​for an increased range of input values ​​of I and Q, based on which the function or error table is generated. Figure 54B illustrates a previous compensation of feed errors in advance (pre-compensation phase) exemplary. As illustrated, the input values ​​of I and Q are corrected for any expected Ierror and Qerror values ​​as determined by an error function or table, before amplification by the VPA. The previous compensation of I and Q errors can be carried out in different phases and / or at different temperatures and / or at different operating parameters inside the VPA. In the example of Figure 54B, error correction takes place before the amplification phase of the VPA. For example, error correction of I and Q can be performed by the transfer function module of the VPA, such as the transfer function modules 1216 and 1726 of Figures 12 and 17, for example. There are several procedures for implementing an I and Q error correction in the VPA transfer function module including using query tables and / or digital logic to implement an error function. In general, advanced feed techniques require data storage such as RAM or NVRAM, for example, to store the data generated in the <figref>image93</figref> 5 measurement phase In contrast to feed-in-advance techniques, feedback techniques do not previously compensate for errors but instead perform real-time measurements inside or at the VPA output to detect any errors or deviations due to process or process variations. temperature, for example. Figure 55 is a block diagram that conceptually illustrates an exemplary Cartesian feedback error correction technique. As will be described further below, Figure 55 illustrates a receiver-based feedback technique, in which the output of the VPA is received by a receiver, before it is fed back to the VPA. Other exemplary feedback techniques will be described further in the following. Feedback techniques may require additional circuitry to perform these measurements in real time, which can be done in different phases inside the VPA, but that require minimal or no data storage. 15 There are several implementations for correction of feedback errors as will be further described in the description of exemplary VPA implementations in the following. Hybrid advance feed / feedback techniques include precompensation and / or error correction components of both feed in advance and feedback. For example, a hybrid feed-in / feedback technique can previously compensate for errors but can also use periodic low-rate feedback mechanisms to complement the advance feed-in compensation. 4.1.3) Multi-Band and Multi-Mode VPA Operation Exemplary VPA implementations provide several VPA architectures to concurrently support multiple frequency bands (e.g., quad band) and / or multiple technology modes (per 25 example, tri mode) for data transmission. The advantages of these VPA architectures will be appreciated by one skilled in the art based on the teachings that will be provided herein. In some examples, VPA architectures provide for the use of a single branch of PA to support standards based on both TDD (time division duplex) and FDD (frequency division duplex). In other examples, VPA architectures allow the removal of expensive and energy-inefficient components in the output phase 30 (eg insulators), which are generally required for FDD-based standards. For purposes of illustration and not limitation, frequency band assignment in lower and upper spectrum bands for various communication standards is provided in Figure 53. It is noted that the bands of the DCS 1800 (digital cellular system 1800) and PCS 1900 (personal communications service 1900) can support different GSM-based implementations, which are also known as GSM -1800 and GSM -1900. The 35 3G TDD bands are allocated for third-generation time division duplex standards such as UMTS TDD (universal mobile phone system) and TD-SCDMA (multiple access by synchronous code division-division in the time), for example. 3G FDD bands are assigned for third-generation frequency division duplex standards such as WCDMA (broadband CDMA), for example. As will be appreciated by those skilled in the art based on the teachings herein, the advantages enabled by exemplary VPA implementations exist in various aspects in addition to those described above. In the following, a more detailed description of exemplary VPA implementations will be provided. This includes a description of different implementations of the VPA digital control circuitry followed by a description of different implementations of the VPA analog core. The embodiments of the present invention are not limited to the specific implementations described herein. As will be understood by those skilled in the art based on the teachings herein, several other VPA implementations can be obtained by combining features provided in exemplary VPA implementations. Therefore, the exemplary VPA implementations described in the following do not represent an exhaustive enumeration of the VPA implementations in accordance with the embodiments of the present invention, and other implementations based on the 50 teachings contained herein also are within the scope of the present invention. For example, certain digital control circuitry could be integrated or combined with a baseband processor. In addition, certain analog control circuitry, such as quadrature generators and vector modulators, can be implemented using a digital control circuitry. In one embodiment, the VPA system can be fully implemented using digital circuitry and can be fully integrated with a baseband processor. 4.2) Digital Control Module The VPA digital control module includes a digital circuitry that is used, among other functions, for signal generation, performance monitoring and operation control of VPA. In section 3, the signal generation functions of the digital control module (that is, generating constant envelope signals 60) were described in detail with reference to the transfer function module (state machine) of the digital control module , in embodiments 700, 1200, and 1700, for example. The performance monitoring functions of the digital control module include functions to monitor and correct errors in the operation of the VPA and / or functions to control the polarization of different phases of the VPA. The VPA operation control functions of the digital control module include a variety of 5 control functions in relation to the operation of the VPA (for example, turning on or programming the VPA modules). In certain embodiments, these control functions may be optional. In other embodiments, these control functions can be accessed through the digital control module by external processors that are connected to the VPA. In other embodiments, these functions are integrated with baseband processors or other digital circuitry. Other functions are also performed by the digital control module in addition to<figref>image94</figref> 10 those that have been described above. Next, digital control module functions and implementations will be provided with additional detail. Figure 56 is a high-level illustration of an example of the digital control module 5600. The embodiment of the digital control module 5600 includes an input interface 5602, an output interface 5604, a state machine 5606, a RAM ( Random Access Memory) 5608 and an NVRAM (nonvolatile RAM) 5610. In about 15 examples, Ram 5608 and / or NVRAM 5610 may be optional. The input interface 5602 provides a plurality of buses and / or ports for entering signals into the digital control module 5600. These buses and / or ports include, for example, buses and / or ports for entering data signals of I and of Q, control signals that are provided by an external processor and / or clock signals. In one example, the 5602 input interface includes an I / O bus. In another example, the input interface 5602 20 includes a data bus to receive the feedback signals from the analog core of the VPA. In another example, the input interface 5602 includes ports for extracting values ​​from the 5600 digital control module. In one example, the values ​​are extracted from the 5600 digital control module by an external processor (for example, a baseband processor ) which is connected to the 5600 digital control module. The output interface 5604 provides a plurality of buses and / or output ports to emit signals from the digital control module 5600. These buses and / or output ports include, for example, buses and / or ports for emitting amplitude information signals (which are used to generate constant envelope signals), polarization control signals (autopolarization signals) , voltage control signals (power supply signals) and output selection signals. The state machine 5606 performs various functions in relation to the signal generation and / or 30 performance monitoring functions of the digital control module 5600. In one example, the state machine 5606 includes a transfer function module, such as described in section 3, to perform signal generation functions. In another example, the state machine 5606 includes modules for generating, among other types of signals, polarization control signals, power control signals, gain control signals and phase control signals. In another example, the state machine 5606 includes modules to perform a prior error compensation in a feed error correction system in advance. The RAM 5608 and / or the NVRAM 5610 are optional components of the 5600 digital control module. In some examples, the RAM 5608 and the NVRAM 5610 reside externally to the 5600 digital control module and can be accessed by the digital control module 5600 via the data buses that are connected to the 5600 digital control module via the 5602 input interface, for example. RAM 5608 and / or NVRAM 5610 may or may not be required, depending on the specific VPA implementation. For example, an implementation of VPA that employs advanced feed techniques for prior error compensation may require that RAM 5608 or NVRAM 5610 store error functions or tables. On the other hand, a feedback technique for error correction may depend solely on digital logic modules in the state machine and may not require storage of RAM 5608 or NVRAM 45 5610. Similarly, the amount of storage RAM 5608 and NVRAM 5610 may depend on the specific VPA implementation. Generally, when used, the NVRAM 5610 is used to store data that is not generated in real time and / or that must be retained when the power is disconnected. This includes, for example, error tables and / or error values ​​such as scalar values ​​and angular values ​​that are generated in the test and characterization phase of the VPA system and / or query tables that are used by modules 50 of transfer functions. Figure 57 illustrates an exemplary 5700 digital control module implementation. The implementation of digital control module 5700 illustrates in particular an exemplary 5602 input interface and an exemplary 5604 output interface of an exemplary VPA 5700 digital control module. As will be described further below, the signals from the input and output interfaces 5602 and 5604 of the VPA 5700 digital control module are directly correlated with signals from the VPA analog core and / or signals to / from one or more external controllers / processors that are connected to the VPA. In the examples described in the sections above, the VPA analog core was represented by analog circuitry 186 together with the PA phase 190 - {1, ..., n} in Figure 1E, for example . It is noted that the bit widths of the data buses and / or the signals of the input and output interfaces in Figure 57 are provided for illustration purposes only and are not limiting.<figref>image95</figref> The input interface 5602 of the exemplary digital control module 5700 includes an A / D INPUT bus 5702, a digital I / O bus 5704, and a plurality of control signals 5706-5730. In other digital control module implementations, the 5602 input interface may include more or less data buses, programming buses and / or control signals. 5 The A / D IN 5702 bus carries feedback information from the VPA analog core to the 5700 digital control module. The feedback information can be used, among other functions, to monitor the output power of the VPA and / or the amplitude and / or phase variations in the branches of the VPA. As illustrated in Figure 57, an A / D converter 5732 converts the feedback information received from the VPA analog core from analog to digital (using the 5736 A / D INPUT signal) before sending this 10 via the 5702 A / D INPUT bus to the 5700 digital control module. In one example, the 5700 digital control module controls a 5734 CLOCK clock signal from the 5732 A / D converter. In another example, the digital control module 5700 controls an input selector for the A / D converter 5732 to select from multiple feedback signals at the input of the A / D converter 5732. In one example, this is done using the signals from A / D input selector 5738-5746. fifteen The 5704 digital I / O bus carries data and control signals inside and outside the 5700 digital control module from one or more processors or controllers that can be connected to the VPA. In one example, some of the control signals 5706 -5730 are used to inform the digital control module 5700 of the type of information to be expected on (or that is present in) the digital I / O bus 5704. For example, the PC / (I / Q) signal n 5724 indicates to the 5700 digital control module whether power control information or 20 I / Q data is being sent via the digital I / O bus 5704. Similarly, the 5720 I / Qn signal indicates to the 5700 digital control module whether I or Q data is being sent through the 5704 digital I / O bus. Other control signals from the 5602 input interface of the VPA 5700 digital control module include digital enable / disable 5706, PRGM / EXECUTE 5708, READ / WRITE 5710, OUTPUT_RELOJ 5712, enable / disable INPUT_RELOJ x2 5714 , the 25 enable / disable of ENTRADA_RELOJ x4 5716, the ENTRADA_RELOJ 5718, the TX / RXn 5726, the PRINT of SINT / EXECUTION of SINT 5728 and the SEL / INTERLOCK OF OUTPUT 5730. The digital enable / disable signal 5706 controls the power on, reset and power off of the VPA. The signals to turn on, reset or turn off the VPA usually come from a processor that is connected to the VPA. For example, when used in a cell phone, a cell phone base controller or processor may turn off the VPA in reception mode and enable it in transmission mode. The PRGM / EXECUTION 5708 signal indicates to the 5700 digital control module if it is in programming or execution mode. In programming mode, the 5700 digital control module can be programmed to enable the desired operation of the VPA. For example, the memory bits (RAM 5608, NVRAM 5610) of digital control module 5700 can be programmed to indicate the standard to be used (for example, 35 WCDMA, EDGE, GSM, etc.) for communication. The programming of the digital control module 5700 is performed using the digital I / O bus 5704. In one example, the VPA is programmed and / or reprogrammed (partially or completely) after it has been installed in (or integrated with) the final product or device used by the VPA. For example, when used in a cell phone, the VPA can be programmed after the cell phone has been manufactured to provide the cell phone with new, additional, modified or different features, such as features in relation to (1 ) supported waveforms, (2) power control, (3) enhanced efficiency and / or (4) on and off profiles. The VPA can also be programmed to eliminate waveforms or other features as desired by the network provider. VPA programming may be based on payment. For example, the VPA can be programmed to include about 45 features and enhancements selected and purchased by the end user. In one example, the VPA is programmed after the device has been manufactured using any well known method or technique, including but not limited to: (1) VPA programming using the programming interface of the device using the VPA; (2) VPA programming by storing programming data on a memory card readable by the device (a SIM card, for example, in the case of a cell phone); and / or (3) VPA programming by transferring programming data to the VPA wirelessly by the network provider or other source. The READ / WRITE 5710 signal tells the 5700 digital control module if data is to be read from, or written to, the digital control module storage (RAM 5608 or NVRAM 5610) via the E / bus S digital 5704. When data is being extracted from the 5700 digital control module, the 5712 CLOCK OUTPUT signal 5712 indicates synchronization information to read from the 5704 digital I / O bus. The CLOCK_ INPUT signal 5718 provides a reference clock signal to the module 5700 digital control. In general, the reference clock signal is selected according to the communication standards supported by the VPA. For example, in a dual mode WCDMA / GSM system, it is desirable that the reference clock signal be a multiple of the WCDMA encoded data rate (3.84 MHz) and the GSM channel scan (200 kHz ), with 19.2 MHz being a popular speed as the least common multiple of both. In addition, the signal of ENTRADA_RELOJ 5718 can be made a multiple of the reference clock signal. In one example, the enable / disable of ENTRADA_RELOJ x2 5714, the enable / disable of ENTRADA_RELOJ <figref>image96</figref> 5 x4 5716 can be used to indicate to the VPA 5700 digital control module that a multiple of the reference clock is being provided. The TX / RXn 5726 signal tells the 5700 digital control module when the system (for example, cell phone) that the VPA uses is entering the transmission or reception mode. In one example, the 5700 digital control module is notified shortly before the system enters transmission mode in order for it to turn on the VPA. In another example, the digital control module 5700 is notified when the system is entering the receive mode in order for it to enter a standby mode or to turn off the VPA. The SINT / RUN PRINT signal from SINT 5728 is used to program the synthesizer that provides the reference frequency to the VPA (such as synthesizers 5918 and 5920 shown in Figure 59). When the PRINT of SINT 5728 is high, the VPA 5700 digital control module can expect to receive 15 data to program the synthesizer on the 5704 digital I / O bus. Typically, synthesizer programming is needed when the VPA transmission frequency is selected. When the EXECUTION of SINT 5728 becomes high, the synthesizer is instructed to be put into operation. The synthesizer can be integrated with the VPA system or provided as an external subsystem or component. The SEL / INTERLOCK OUT signal 5730 is used to select the VPA output to be used for transmission. This may be needed, or not, depending on the number of VPA outputs. When the 5730 OUTPUT SEL goes high, the digital control module 5700 expects to receive data to select the output on the digital I / O bus 5704. When the INTERLOCK 5730 goes high, the 5700 digital control module guarantees that the VPA output used for transmission is maintained (cannot be changed) during the course of the current transmission sequence. 25 The output interface 5604 of the exemplary digital control module 5700 includes a plurality of data buses (5748, 5750, 5752, 5754, 5756, 5758, 5760, 5762, 5764 and 5766), a 5799 programming bus, and a plurality of control signals (5768, 5770, 5772, 5744, 5776, 5778, 5780, 5782, 5784, 5786, 5788, 5790, 5792, 5794, 5796 and 5798). In other examples of the digital control module 5700, the output interface 5604 may have more or less data buses, programming buses and / or control signals. 30 Data buses 5752, 5754, 5756 and 5758 carry digital information from the 5700 digital control module that is used to generate the substantially constant envelope signals in the VPA analog core. It is noted that the exemplary digital control module 5700 can be used in an exemplary 4-branch VPA (see section 3.1) or an exemplary 2-branch VPA (see section 3.3). For example, the digital information carried by the data buses 5752, 5754, 5756 and 5758 corresponds to signals 722, 724, 726 and 728 in the embodiment of Figure 7A or signals 1720, 1722, 1724, and 1726 in the embodiment of Figure 17, and can be generated by the digital control module 5700 according to equations (5) (for an exemplary 4-branch VPA) and (18) (for an exemplary 2-branch VPA) . The digital information that is carried by the data buses 5752, 5754, 5756 and 5758 is converted from digital to analog using digital to analog converters (DAC 01-04) to generate the analog signals 5753, 5755, 5757 and 5759, respectively. The analog signals 5753, 5755, 5757 and 5759 are introduced into vector modulators in the analog core of the VPA as will be further described in what follows with reference to the analog core implementations of VPA. In one example, DAC 01-04 is controlled and synchronized by a DAC CLOCK signal of vector mod 5770 that is provided by the digital control module. In addition, DAC 01-04 is provided with the same central reference voltage signal VREF_D 5743. 45 Data buses 5760 and 5762 carry digital information from digital control module 5700 that is used to generate voltage signals bias for the PA amplification phase and the VPA excitation circuit amplification phase (see Figure 52 for an illustration of different VPA amplification phases). In another example, additional control functions such as pre-excitation circuit phase polarization control are used. The digital information that is carried by data bus 5760 is converted from digital to analog 50 using DAC_05 to generate the output phase polarization signal 5761. Similarly, the digital information that is carried by the data bus 5762 is converted from digital to analog using DAC_06 to generate an excitation circuit phase polarization signal 5763. The output phase polarization signal 5761 and the phase polarization signal of excitation circuit 5763 corresponds, for example, to the polarization signals A and B illustrated in example 5100H. In one example, DAC 05 and 06 are controlled and synchronized using an autopolarization DAC CLOCK signal 5772, and are provided with the same central reference voltage signal VREF_E 5745. Data buses 5764 and 5766 carry a digital information from the 5700 digital control module that is used to generate voltage control signals for the output phase and the excitation circuit phase of the VPA. The digital information that is carried by the data bus 5764 is converted from digital to analog using DAC_07 to 60 generate the output phase voltage control signal 5765. Similarly, the digital information that is carried <figref>image97</figref> via data bus 5766 it is converted from digital to analog using DAC_08 to generate the excitation circuit phase voltage control signal 5767. The output phase voltage control signal 5765 and the excitation circuit phase voltage control 5767 are used to generate supply voltages for the output phase and the excitation circuit phase, providing an additional procedure for controlling the 5 phase output voltage and the excitation circuit phase of the VPA. In one example, DAC 07 and 08 are controlled and synchronized using a voltage control DAC CLOCK signal 5774, and they are provided with the same central reference voltage signal VREF_F 5747. Data buses 5748 and 5750 carry a digital information from the 5700 digital control module that is used to generate gain and phase balance control signals. In one example, the 10 gain and phase balance control signals are generated in response to the phase and feedback gain information that is received from the VPA analog core by the 5702 A / D INPUT bus. The digital information that is carried by data bus 5748 is converted from digital to analog using DAC_09 to generate the analog gain balance control signal 5749. Similarly, the digital information that is carried by the data bus 5750 is converted from digital to analog using DAC_10 to generate the analog phase 15 balance control 5751. The gain and phase balance control signals 5749 and 5751 provide a mechanism to regulate the gain and phase in the VPA analog core. In one example, DAC 09 and 10 are controlled and synchronized using an equilibrium DAC CLOCK signal 5768, and are provided with the same central reference voltage VREF_B 5739. Programming bus 5799 carries digital instructions from 5700 digital control module that is used to program the synthesizer or frequency synthesizers in the VPA analog core. In one example, the digital instructions that are carried by the 5799 programming bus are generated according to the data that is received on the digital I / O bus 5704, when the SINT 5728 PRGM signal is high. The digital instructions for programming the frequency synthesizers include instructions for setting the appropriate synthesizer (HIGH or low band) to generate a frequency in accordance with the selected communication standard. In one example, the 5799 programming bus is a 3-wire programming bus. In addition to the data and programming buses described above, the output interface 5604 includes a plurality of control signals. In conjunction with the 5799 programming bus, which is used to program the analog VPA core frequency synthesizers, the high band enable / disable control signals and the 5796 and 5798 low band enable / disable signals are generated to controlling which of a high band frequency synthesizer and a low band frequency synthesizer of the analog VPA core is enabled / disabled. Control signals 5738, 5740, 5742, 5744 and 5746 control an input selector to multiplex the feedback signals from the VPA analog core over the A / D INPUT input signal 5736 of the 5732 A / D converter. In one example, control signals 5738, 5740, 5744 and 5746 control the multiplexing of a power output feedback signal, a differential branch amplitude feedback signal and a differential branch phase feedback signal on the signal. of INPUT A / D 5736. Other feedback signals may be available in other examples. In one example, the feedback signals are multiplexed according to a previously determined multiplexing cycle. In another example, certain 40 feedback signals are carried periodically by the 5736 A / D INPUT signal, while others are requested upon request by the digital control module. The output selection control signals 5776, 5778, 5780, 5782 and 5784 are generated by the digital control module 5700 in order to select a VPA output, when the particular VPA implementation supports a plurality of outputs for different bands of frequency and / or technology modes. In one example, the output selection control signals 5776, 5778, 5780, 5782 and 5782 are generated in accordance with the digital control module input signal 5730. In the exemplary implementation of Figure 57, digital control module 5700 provides five output selection control signals to select one of five different VPA outputs. In one example, the output selection control signals 5776, 5778, 5780, 5782 and 5784 control the circuitry inside the VPA analog core in order to turn on the circuitry corresponding to the selected VPA output and to turn off the circuitry that corresponds to the remaining unselected VPA outputs. In some examples, at any time, the output selection control signals 5776, 5778, 5780, 5782 and 5784 ensure that the circuitry corresponding to a single VPA output is on, when the VPA is in transmission mode . An example of a different digital control module may have more or less output selection control signals depending on the particular number of VPA outputs supported by the particular analog core implementation. The band or high band control signal of vector MOD / band or low band of vector MOD 5786 is generated by the digital control module 5700 to indicate whether a high band frequency modulation set or a modulation set is to be used Low band frequency vector modulators in the VPA analog core. In one example, high band and low band vector modulators have about 60 different characteristics, allowing each set to be more suitable for a frequency range of <figref>image98</figref> modulation. The control signal 5786 is generated according to the selected VPA output. In one example, control signal 5786 controls the circuitry inside the VPA analog core in order to ensure that the selected set of vector modulators is on and that the other set or sets of vector modulators are turned off. In another example, the control signal 5786 controls the circuitry inside the analog core of the VPA in order to couple a set of interpolation filters with the selected set of vector modulators. The 3G 5788 high / normal band control signal is an optional control signal that can be used, if necessary, to enable the VPA to support the wide range high frequency band. In one example, control signal 5788 can force more intensity through the output phase circuitry of the analog core and / or modify the output impedance characteristics of the VPA. The filter response control signal 1 / filter response 2n 5790 is an optional control signal that can be used to dynamically change the response of the interpolation filters in the analog core of the VPA. This may be necessary because interpolation filters have different optimal responses for different communication standards. For example, the optimal filter response has an elbow frequency of 3 dB around 5 MHz for WCDMA or EDGE, while this frequency is approximately 400 kHz for GSM. Therefore, the control signal 5790 allows to optimize the interpolation filters according to the communication standard used. The attenuator control signals 5792 and 5794 are optional control signals that can be used, if necessary, to provide additional output power control features and functions. For example, the attenuator control signals 5792 and 5794 could be configured to enable / disable the RF attenuators at the VPA output. These attenuators may be required based on the implementation of specific VPA, which could be manufactured using silicon, GaAs or CMOS procedures. Figure 58 illustrates another exemplary 5800 digital control module. The exemplary 5800 digital control module is similar in many ways to the 5700 digital control module. In particular, both examples 5700, 5800 have the same input interface 5602, and substantial portions of the output interface (the output interface in Figure 58 is marked with reference number 5604 '). The differences between examples 5700 and 5800 are related to the type of feedback information that is being provided to the digital control module. Specifically, the two examples 5700 and 5800 are designed to work with distinctly different feedback mechanisms for error correction. These mechanisms will be further described in the following in section 4.3 with reference to exemplary analog core implementations. The exemplary 5800 implementation includes different input selection control signals 5808, 5810 and 5812 compared to the exemplary 5700 implementation. The input selection control signals 5810 and 5812 control whether feedback information is to be received from the high band or the low band analog circuitry of the VPA, depending on which band is in use. The I / Qn 35 5808 input selection control signal controls the multiplexing of the I and Q feedback data from the VPA analog core. In one example, the control signal 5812 allows a sequential switching between the I data and the Q data on the A / D IN signal 5736. As a further distinction with respect to example 5700, example 5800 includes a data bus An additional 5802, which carries digital information from the 5800 digital control module that is used to generate a 5806 automatic gain control signal. The automatic gain control signal 5806 is used to control the gain of an amplifier circuit that is used in the feedback mechanism in the VPA analog core. An additional description of this component of the feedback mechanism will be provided in the following. In one example, the digital information that is carried by data bus 5802 is converted from digital to analog by DAC_11 to generate analog signal 5806. The DAC_11 is controlled by a 455804 clock signal that is provided by the digital control module, and the VREF_B 5739 signal is provided as a central reference voltage. It is noted that the 5700 and 5800 digital control modules exemplify some of the typical digital input and output control module signals that can be used in a digital control module implementation. More or less input and output signals can also be used, as will be appreciated by one skilled in the art based on the teachings herein, depending on the system in which the VPA and / or the core is being used. specific VPA analog to be used with the digital control module. In one example, the 5700 and 5800 digital control module implementations can be used in conjunction with a VPA analog core using error correction only for feedback, only for feed in advance, or both for feedback and feed in advance. When using a feed-only approach in 55, the elements and / or feedback signals (for example, A / D INPUT 5702, control signals 5738, 5740, 5742, 5744, 5746, control signals gain and balance phase 5749 and 5751) can be disabled or deleted. Accordingly, variations of the digital control module implementations 5700 and 5800 copies are within the scope of the examples disclosed herein. <figref>image99</figref> 4.3) VPA Analog Core In this section, various exemplary implementations of the VPA analog core will be provided. As will be described in the following, the various exemplary implementations share a large number of components, circuits and / or signals, with the main differences in relation to the output phase architecture, the error correction feedback mechanism 5 adopted and / or the actual semiconductor material used in the manufacture of microplates. As will be understood by one skilled in the art based on the teachings herein, other implementations of VPA analog core can also be devised by exchanging, adding and / or removing features from among the various exemplary implementations that are describe in the following. Therefore, the embodiments of the present invention should not be limited to the 10 exemplary implementations described herein. 4.3.1) VPA Analog Core Implementation A Figure 59 illustrates an exemplary VPA 5900 analog core implementation. In one example, the input signals of the analog core 5900 connect directly or indirectly (through a DAC) with the output signals from the output interface 5604 of the digital control module 5600. Similarly, the feedback signals from the analog core 5900 connect directly or indirectly (through a DAC) to the input interface of the digital control module 5600. For illustrative purposes, the analog core 5900 is shown in figure 59 as it is connected to the digital control module 5700, as indicated by the same numerical signals in both figure 57 and figure 59. The 5900 analog core implementation is an exemplary 2-branch VPA. This 5900 implementation, however, can easily be modified to a 4-branch VPA or an exemplary CPCP, as will be apparent to those skilled in the art based on the teachings herein. At a high level, the analog core 5900 includes an input phase to receive data signals from the digital control module 5700, a vector modulation phase to generate substantially constant envelope signals, and an amplification output phase for amplify and output the desired VA 25 output signal. Additionally, the 5900 analog core includes a power supply circuitry to control and deliver power to the different phases of the analog core, an optional output phase protection circuitry and an optional circuitry to generate and provide feedback information to the control module VPA digital. The input phase of the VPA 5900 analog core includes an optional interpolation filter bank (5910, 5912, 5914 30 and 5916) and a plurality of switches 5964, 5966, 5968 and 5970. The interpolation filters 5910, 5912, 5914 and 5916, which can also serve as anti-lap filters, make up the analog outputs 5753, 5755, 5757 and 5759 of DAC 01-04 to generate the desired output waveform. In one example, the response of interpolation filters 5910, 5912, 5914 and 5916 is dynamically changed using control signal 5790 from digital control module 5700. The digital control module signal 5790 can control, for example, the 35 switches inside the interpolation filters 5910, 5912, 5914 and 5916 to give rise to a change in the active circuitry (the enabling RC circuitry / disabling) inside the filters 5910, 5912, 5914 and 5916. This may be necessary because the interpolation filters 5910, 5912, 5914 and 5916 have different optimal responses for different communication standards. It should be noted that interpolation filters 5910, 5912, 5914 and 5916 can be implemented using digital circuitry such as FIR filters or programmable FIR 40 filters. When implemented digitally, these filters can be included inside the VPA system or integrated with a baseband processor. Subsequently, the outputs of the interpolation filters 5910, 5912, 5914 and 5916 are switched using switches 5964, 5966, 5968 and 5970 to connect with either an upper band path 5964 or a lower band path 5966 of the analog core of VPA 5900. This determination between the upper and lower band paths is generally made by the digital control module 5700 based on the frequency range selected for transmission by the VPA. For example, the lower band path 5966 is used for GSM -900, while the upper band path 5964 is used for WCDMA. In one example, switches 5964, 5966, 5968 and 5970 are controlled by the vector or high band signal of vector MOD / band or low band of vector MOD 5786, which is provided by the digital control module 5700. fifty Signal 5786 controls the coupling of each of the switches 5964, 5966, 5968 and 5970 with the first or second respective inputs, thereby controlling the coupling of the interpolation filter outputs 5910, 5912, 5914 and 5916 or with the upper trajectory 5964 or with the lower trajectory 5966 of the analog core of VPA 5900. The vector modulation phase of the VPA 5900 analog core includes a plurality of vector modulators 5922, 5924, 5926 and 5928, divided between the upper band path 5964 and the lower band path 5966 of the analog core 5900. Based on the Selected operating band, either the upper band path vector modulators (5922, 5924) or the lower band path vector modulators (5926, 5928) are active. <figref>image100</figref> In one example, the operation of the vector modulators 5922, 5924 or 5926, 5928 is similar to the operation of the vector modulators 1750 and 1752 in the embodiment of Figure 17, for example. Vector modulators 5922 and 5924 (or 5926 and 5928) receive input signals 5919, 5921, 5923 and 5925 (5927, 5929, 5931 and 5933) from the optional interpolation filters 5910, 5912, 5914 and 5916, 5 respectively. The input signals 5919, 5921, 5923 and 5925 (or 5927, 5929, 5931 and 5933) include amplitude information that is used to generate the constant envelope signals by means of vector modulators. In addition, vector modulators 5922 and 5924 (or 5926 and 5928) receive a HIGH-band 5935 CLOCK_RF signal (LOW 5937 LOW-CLOCK signal) from a 5918 high-band or band frequency synthesizer (a frequency synthesizer of low band or bands 5920). The 10-band frequency synthesizer or HIGH 5918 bands (the low frequency band synthesizer or low bands 5920) are optionally located externally or in the VPA analog core. In one example, the HIGH 5918 band or band frequency synthesizer (the 5920 low band or band frequency synthesizer) generates RF frequencies in the upper band range of 1.7-1.98 GHz (lower band range 824-915 MHz). In another example, the high frequency band or band synthesizer 5918 and the low band frequency synthesizer 1520 are controlled by the digital control module signals 5796 and 5798, respectively. The signals 5796 and 5798, for example, turn on the appropriate frequency synthesizer according to the selected transmission frequency band, and indicate to the selected synthesizer that it generates an RF frequency clock according to the selected transmission frequency. Vector modulators 5922 and 5924 (or 5926 and 5928) modulate the input signals 5919, 5921, 5923 and 5925 20 (5927, 5929, 5931 and 5933) with the HIGH-band 5935 CLOCK signal (LOW-band CLOCK_RF signal 5937). In one example, the vector modulators 5922 and 5924 (or 5926 and 5928) modulate the input signals with appropriately deduced and / or phase-shifted versions of the HIGH-band 5935 CLOCK_RF signal (LOW-band CLOCK_RF signal 5937), and combine the modulated signals generated to generate substantially constant envelope signals 5939 and 5941 (5943 and 5945). 25 In another example, the vector modulators 5922 and 5924 (or 5926 and 5928) also receive a phase balance control signal 5751 from the VPA digital control module. The phase balance control signal 5751 controls the vector modulators 5922 and 5924 (or 5926 and 5928) to result in a phase change in the constant envelope signals 5939 and 5941 (or 5943 and 5945), in response to phase feedback information from the analog core. The amplitude and phase feedback mechanism is further analyzed 30 in the following. Optionally, the 5922 and 5924 upper band path vector modulators also receive a 3G 5788 ALTA / Normaln band signal from the digital control module. Signal 5788 can be used, if necessary, to further support the excitation of vector modulators at the higher frequencies of the upper band. The output phase of the VPA 5900 analog core includes a plurality of MISO amplifiers 5930 and 5932, 35 divided between the upper band path 5964 and the lower band path 5966 of the analog core 5900. Based on the selected operating band Either the upper band path MISO amplifier 5930 or the lower band MISO amplifier 5932 is active. In one example, the MISO amplifier 5930 (or 5932) receives the substantially constant envelope signals 5939 and 5941 (or 5943 and 5945) from the vector modulators 5922 and 5924 (or 5926 and 5928). The MISO 5930 (or 5932) amplifier individually amplifies the 5939 and 5941 (or 5943 and 5945) signals to generate amplified signals, and combines the amplified signals to generate the 5947 (or 5949) output signal. In one example, the MISO amplifier 5930 (or 5932) combines the amplified signals by means of a direct coupling, as described herein. Other modes of combining the amplified signals have been described above in section 3. 45 The output phase of the VPA 5900 analog core is capable of supporting multi-band and multi-mode VPA operation. As shown in Figure 59, the output phase includes two MISO amplifiers 5930 and 5932 for upper and lower band operation, respectively. In addition, the output of each of the upper band 5964 and the lower band 5966 is further switched between one or more output paths according to the selected transmission mode (eg, GSM, WCDMA, etc.). Generally, separate output paths are required for different transmission modes because FDD-based modes (for example, WCDMA) require the presence of duplexers at the output, while TDD-based modes (for example , GSM, EDGE) have switched T / R outputs. In the analog core 5900, the output 5947 of the MISO amplifier 5930 can be coupled with one of the three output paths 5954, 5956 and 5958, with each output path 5954, 5956, 5958 being the one that is coupled with an antenna (not shown) or connector (not shown) for a particular transmission mode. Similarly, the output 5949 of the MISO amplifier 5932 can be coupled with one of the two output paths 5960 and 5962. In one example, the output selection signals 5776, 5778, 5780, 5782 and 5784, which are provided by the digital control module, control switches 5942 and 5944 to couple the output of the active MISO amplifier with the output path appropriate, based on the transmission mode 60 selected. It is noted that more or less output paths 5954, 5956, 5958, 5960 and 5962 can be used.<figref>image101</figref> Therefore, with only two MISO 5930 and 5932 amplifiers, the 5900 analog core supports multiple different transmission modes. In one example, the 5900 analog core provides for the use of a single MISO amplifier to support GSM, EDGE, WCDMA and CDMA2000. Therefore, it is evident that one of the advantages of this exemplary VPA analog core according to the 5900 implementation is in the reduction in the number of PAs per output path supported. This corresponds directly to a reduction in the microplate area required for the VPA 5900 analog core. In one example, the output phase of the analog core 5900 receives the optional output phase autopolarization signal 5761, the autopolarization signal of excitation circuit phase 5763 and gain balance control signal 5749 from the digital control module. Or, it may not be necessary, the output phase autopolarization signal 5761 and the excitation circuit phase autopolarization signal 5763 according to the particular type of transistors used in the actual MISO implementation. In one example, the output phase autopolarization signal 5761 and the excitation circuit phase autopolarization signal 5763 control the polarization of the MISO amplification phases to result in a change in the power output and / or the VPA energy efficiency. Similarly, the gain balance control signal 5749 may result in a change in the gain levels of different MISO amplification phases, in response to the power output feedback information received by the module. Digital control from the analog core. In the following an additional analysis of these optional output phase input signals will be provided. In one example, the output phase of the analog core 5900 provides optional feedback signals 20 to the digital control module 5700 of the VPA. Typically, these feedback signals are used by the 5700 digital control module to correct the amplitude and phase variations in the VPA branches and / or to control the VPA output power. In the specific implementation of the 5900 analog core, a differential feedback approach is used to monitor amplitude and phase variations, using a differential branch amplitude signal 5950 and a differential branch phase signal 5948 that are provided by the phase of 25 output. In addition, output power monitoring is provided using the Power detection signals A 5938 and Power detection B 5940, which measure the output power of the MISO amplifiers 5930 and 5932, respectively. Because only one of the MISO amplifiers 5930 and 5932 can be active at any time, in one example, the POWER detection A 5938 and the POWER detection 5940 are added together using the adder 5942, to generate a signal which corresponds to the 30 output power of the VPA. In one example, the feedback signals from the output phase are multiplexed using an input selector 5946 that is controlled by the digital control module 5700. In another example, the digital control module 5700 uses the A / D input selector signals 5738, 5740, 5742, 5744 and 5746 to control input selector 5946 and select the feedback signal to be received. It is noted that it may not be necessary for the supervision of the feedback signals to take place at a real-time rate and it may only be necessary that it be performed periodically at a low rate. For example, for the purpose of correcting phase errors and branch amplitude, the rate at which feedback monitoring is performed depends on several factors such as the degree of correction of feed in progress that is being performed in the module digital control, process variations due to temperature, or changes in operation such as changing battery or supply voltages. In the foregoing, the commitments between compensation techniques and / or correction of feed errors in advance and feedback have been described. Therefore, the parameters that govern the rates at which feedback monitoring is performed are design options that are generally selected by the actual VPA designer. As a result, the 5900 analog core implementation can be programmed to function as a pure feedback implementation by disabling any feed forward correction in the digital control module, a pure feed feed implementation by disabling supervision. of feedback signals, or as a hybrid feed / feed feed implementation with a feed feed / variable feedback feed. 50 In one example, the output phase of the analog core 5900 includes an optional output phase protection circuitry. In Figure 59, this is illustrated using the VSWR protection circuitry (voltage standing wave ratio) 5934 and 5936, which is coupled with the MISO amplifiers 5930 and 5932, respectively. The protection circuitry of VSWR 5934, 5936 may or may not be required depending on the actual MISO amplifier implementation. In one example, the VSWR 5934 and 5936 55 protection circuitry protects the output phase PAs (see PA 6030 and 6032 in Figure 60, for example) against their thermal shutdown or device breakdown, when the Output voltage level could result in the output phase breaking voltage being exceeded. In conventional systems, this is achieved through the use of an RF insulator at the output of the PAs, which is both expensive and has losses (usually resulting in a power loss of approximately 1.5 dB). Consequently, the protection circuitry of VSWR 5934, 60 5936 eliminates the need for insulators in the output phase, further reducing the cost, size and power loss of the VPA. In one example, the protection circuitry of VSWR 5934, 5936 enables an insulator-free output phase capable of supporting WCDMA. The VSWR 5934 and 5936 protection circuitry also enables the VPA to operate at any level of VSWR without damaging the VPA. The VSWR protection circuitry can be designed to deliver the maximum output power of a particular implementation of a VPA at any level of VSWR.<figref>image102</figref> As described above, the 5900 analog core includes a power supply circuitry to control and deliver power to the different phases of the 5900 analog core. In one aspect, the power supply circuitry provides means for lighting portions. VPA 5900 analog core active. In another aspect, the power supply circuitry provides means to control the energy efficiency and / or the output power of the VPA. In the 5900 analog core implementation, the power supply circuitry includes the power supply of MA 5902, the excitation circuit phase power supply 5904, the output phase power supply 5906, and the power supply of vector mod 5908. In one example, the power supply circuitry is controlled by the output selection signals 5776, 5778, 5780, 5782 and 5784, which are provided by the digital control module 5700. The power supply of MA 5902 includes a circuitry to control the ignition of active portions of the VPA 5900 analog core. In the 5900 analog core, the power supply of MA 5902 has two outputs VSUMINIST of MA1 5903 and VSUMINIST of MA2 5905. At any time, only one of the VSUMINIST of MA1 5903 or the VSUMINIST of MA2 5905 is active, ensuring that only the upper band portion 5964 or the lower band portion 5966 of the analog core of VPA 5900 is on. In one example, the active output of the power supply of MA 5902 is coupled with all the active circuitry of the VPA 5900 analog core, with the exception of the circuitry having unique power supply signals as described in what follow. The power supply of MA 5902 receives output selection signals from the digital control module, which enable one or the other of the output signals VSUMINIST of MA1 5903 or VSUMINIST of MA2 5905, based on the selected output of the VPA The excitation circuit phase power supply 5904 includes a circuitry to provide power to the excitation circuit phase circuitry of the MISO amplifiers 5930, 5932. Similar to the power supply of MA 5902, the excitation circuit phase power supply 5904 has two VS1 supply of excitation circuit of MA1 5907 and VSUMINIST of excitation circuit of MA2 5909, with only one of the two outputs being active at any time. The excitation circuit phase power supply 5904 is also controlled by the output selection signals 5776, 5778, 5780, 5782 and 5784 according to the selected VPA output. In addition, the excitation circuit phase power supply 5904 receives an excitation circuit phase voltage control signal 5767 from the digital control module 5700. In one example, the excitation circuit VSUMINIST outputs of MA1 5907 and the excitation circuit VSUMINIST of MA2 5909 are generated according to the excitation circuit phase voltage control signal 5767 received. In another example, the excitation circuit phase voltage control signal 5767 results in the excitation circuit phase power supply 5904 increasing or decreasing the excitation circuit VS. supply of MA1 5907 or the VS. circuit supply. MA2 5909 excitation to control the power amplification level of excitation circuit phase. In another example, the excitation circuit phase voltage control signal 5767 is used by the digital control module 5700 to effect a change, using the excitation circuit phase power supply 5904, in the supply voltage of power of the excitation circuit phase of the active MISO amplifier 5930 or 5932, thereby controlling the energy efficiency of the VPA. The output phase power supply 5906 includes a circuitry to provide power to the PA phase circuitry of the MISO amplifiers 5930, 5932. Similar to the power supply of MA 5902, the output phase power supply 5906 has two outputs VSUMINIST of output phase of MA1 5911 and VSUMINIST of output phase of MA2 5913, with only one of the two outputs being active at any time. The output phase power supply 5906 is also controlled by the output selection signals 5776, 5778, 5780, 5782 and 5784 according to the selected VPA output. In addition, the output phase power supply 5906 receives an output phase voltage control signal 5765 from the digital control module 5700. In one example, the output phase VSUMINIST of MA1 5911 and output phase VSUMINIST of MA2 5913 outputs are generated in accordance with the output phase voltage control signal 5765 received. In another example, the output phase voltage control signal 5765 results in the output phase power supply 5906 increasing or decreasing the output phase VSAMINIST of MA1 5911 or the output phase VSUMINIST of MA2 5913 to control the PA phase power amplification level. In another example, the output phase voltage control signal 5765 is used by the digital control module 5700 to make a change, using the output phase power supply 5906, in the phase power supply voltage PA of the active MISO amplifier 5930 or 5932, thereby controlling the energy efficiency of the VPA. The power supply of vector mod 5908 includes a circuitry to provide power to the vector modulators 5922, 5924, 5926 and 5928 of the analog core 5900. In the analog core 5900, the power supply of vector mod 5908 has two outputs 5915 and 5917 to turn on the upper band vector modulators 5922 and 5924 and the lower band vector modulators 5926 and 5928, respectively. At any time, only one of the outputs 5915 or 5917 is active, ensuring that only the upper or lower band vector modulators of the 5900 analog core are on. The power supply of vector mod 5908 receives a vector mod selection signal 5786 from the digital control module 5700, which controls which of its two outputs 5915 and 5917 is active, according to the selected transmission frequency requirements.<figref>image103</figref> In addition to the power supply circuitry described above, the analog core 5900 may optionally include a voltage reference generator circuitry. The voltage reference generator circuitry can reside externally or inside the VPA 5900 analog core. The voltage reference generator circuitry generates reference voltages for different circuits inside the VPA. In one example, as illustrated in Figure 57, the voltage reference generator circuitry provides reference voltages to DACs 01-10, which are coupled with data outputs of the digital control module. In another example, as illustrated in Figure 59, the voltage reference generator circuitry provides reference voltages to the interpolation filters and / or the vector modulators in the VPA analog core. In one example, circuits of the same branch of the VPA are provided with the same reference voltage. For example, it is noted that DAC 01 and 02, interpolation filters 5910 and 5912 and vector modulators 5922 and 5924, which represent a data path or VPA branch, all share the same reference voltage VREF_C 5741. For different implementations and system performance requirements, voltage reference signals can be provided as a single reference voltage or multiple reference voltages. Figure 60 illustrates an example of output phase 6000 according to the VPA 5900 analog core implementation. The example of output phase 6000 includes a MISO 6058 amplifier phase, an optional output switching phase (which is performed by switch 6044) and an optional output phase protection and power detection circuitry. In one example, the MISO 6058 amplifier phase corresponds to the MISO 5930 amplifier in the 5900 analog core. Accordingly, the VSUMINIST signal of MA 6006, the excitation circuit VSUMINIST signal of MA 6004 and the output phase VSUMINIST signal of MA2 6002 correspond to signals 5903, 5907 and 5911 in Figure 59, respectively . Similarly, the input signals of INPUT1 of MA and INPUT2 of MA 6008 and 6010 and the output signals of MA 6046, 6048 and 6050 correspond to the input signals of MISO 5939 and 5941 and output signals 5954 , 5956 and 5958 in Figure 59, respectively. The POWER detection signal 6023 corresponds to the POWER detection signal A 5938 in Figure 59 (in general, the implementation of the MISO amplifier 5932 could also be based on the amplifier phase of MISO 6058 in Figure 60) . The amplifier phase of MISO 6058 in example 6000 includes a preexcitation circuit amplification phase, which is performed by the pre-excitation circuits 6012 and 6014, an excitation circuit amplification phase, which is performed by the circuits of excitation 6018 and 6020, and a phase of amplification of PA, that is realized by means of the PA of exit phase 6030 and 6032. In one example, the substantially constant envelope input signals IN1 of MA 6008 and INPUT2 of MA 6010 are amplified at each phase of the MISO 6058 amplifier, before being added to the outputs of the PA phase. In one example, the MISO 6058 amplifier phase is powered by power supply signals that are provided by voltage controlled power supply circuits. As described with reference to Figure 59, the power supply signals are generated by the power supply circuitry of the VPA 5900 analog core. In one example, the power supply signals are used to control the supply voltages. of power of the different amplification phases of the MISO 6058 amplifier phase, thereby affecting the energy efficiency of the VPA under various operating conditions. In another example, the power supply signals are used to control the gain of each of the different amplification phases of the MISO 6058 amplifier phase, thereby enabling a power control mechanism. In addition, the power supply signals can be independently controlled from each other, allowing independent control of the power and / or efficiency for each of the different amplification phases of the MISO 6058 amplifier phase. This independent control allows , for example, disconnect one or more amplification phases of the MISO 6058 amplifier according to the desired output power of the VPA. In Figure 60, the power supply signals are illustrated using signals 6002, 6004 and 6006. In one example, the MISO amplifier phase 6058 includes a polarization control circuitry. The polarization control circuitry may be optional according to the particular MISO amplifier implementation. In one example, the polarization control circuitry provides a mechanism to control the efficiency and / or power at each amplification phase of the MISO 6058 amplifier. This mechanism is independent of the mechanism described above with reference to The power supply signals. In addition, this mechanism envisages controlling each amplification phase independently and individually. In Fig. 60, polarization control circuitry is illustrated using gain balance control circuitry 6016, excitation circuit phase autopolarization circuitry 6022 and output phase autopolarization circuitry 6028. <figref>image104</figref> In one example, the gain balance control circuitry 6016 is coupled with the inputs of the pre-excitation circuit amplification phase as illustrated in Figure 60. The gain balance control circuitry 6016 receives a signal. of gain balance control 5749 from the digital control module 5700 (through a DAC), and outputs the input polarization control signals 6013 and 6015. The excitation circuit phase autopolarization circuitry 6022 is coupled with the inputs of the excitation circuit amplification phase as illustrated in Figure 60. The excitation circuit phase autopolarization circuitry 6022 receives the autopolarization signal phase circuit 5763 from the digital control module 5700 (through a DAC), and outputs the input polarization control signals 6017 and 6019. Similarly, the output phase autopolarization circuitry 6028 is coupled with the inputs of the PA amplification phase as illustrated in Figure 60. The output phase autopolarization circuitry 6028 receives the phase autopolarization signal. output 5761 from the digital control module 5700 (through a DAC), and outputs the input polarization control signals 6029 and 6031. In one example, the digital control module 5700 independently controls the polarization of the pre-excitation circuit phase, the excitation circuit phase and the PA phase of the MISO 6058 amplifier using the balance control signal of gain 5749, the excitation circuit phase autopolarization signal 5763 and the output phase autopolarization signal 5761, respectively. In another example, the digital control module 5700 can effect a change in the polarization of the pre-excitation circuit phase, the excitation circuit phase and / or the PA phase of the MISO 6058 amplifier only using the signal of gain balance control 5749. As illustrated in Figure 60, the gain balance control circuitry 6016 is coupled with the excitation circuit phase autopolarization circuit 6022 and the output phase autopolarization circuitry 6028. In one example, a change in the The overall gain of the VPA is effected by the 5700 digital control module firstly by controlling the polarization in the pre-excitation circuit phase. If an additional gain change is required, a polarization control is performed in the excitation circuit phase, and subsequently in the PA phase. In one example, the MISO 6058 amplifier phase includes circuits to enable a compensation and / or error correction feedback mechanism. In the example of output phase 6000, a differential feedback mechanism is adopted, whereby the differential branch amplitude measurement circuitry 6024 and the differential branch phase measurement circuitry 6026 measure, respectively, the differences in amplitude and phase between the branches of the MISO 6058 amplifier. In one example, the differential branch amplitude measurement circuitry 6024 and the differential branch phase measurement circuitry 6026 are coupled to the inputs of the PA phase (the PA 6030 and 6032) of the MISO amplifier 6058. In others examples, circuitry 6024 and 6026 can be coupled to the previous phase inputs of the MISO 6058 amplifier. In one example, the differential branch amplitude measurement circuitry 6024 and the differential branch phase measurement circuitry 6026 respectively emit the differential branch amplitude signal 5950 and the differential branch phase signal 5948, which are fed back to the module 5700 digital control (through A / D converters). Because the 5700 digital control module knows at any particular time the correct differences in amplitude and / or phase between the branches of the MISO 6058 amplifier, it can determine any errors in amplitude and / or phase based on the amplitude signal differential branch 5950 and differential branch phase signal 5948. The example of output phase 6000 includes an optional output phase protection circuitry. It may or may not be necessary for the output phase protection circuitry according to the particular MISO amplifier implementation. In Figure 60, the output phase protection circuitry is illustrated using the VSWR 6034 protection circuitry. In one example, the VSWR 6034 protection circuitry monitors the output of the PA phase, and controls the gain of the amplifier. of MISO 6058 to protect PA 6030 and 6032. In example 6000, the VSWR 6034 protection circuitry receives a signal 6036, which is coupled either directly or indirectly with the output of the PA phase. In one example, the VSWR 6034 protection circuitry ensures that the voltage level at the output of the PA phase remains below a certain level, to prevent PA 6030 and 6032 from entering thermal shutdown or experiencing device breakage. . In one example, the protection circuitry of VSWR 6034 ensures that a breaking voltage of the PA 6030 and 6032 is not exceeded. Therefore, provided that the voltage level at the output of the PA 6030 and 6032 is above At a previously determined threshold, the VSWR 6034 protection circuitry may result in a decrease in the gain of the MISO amplification phases. In one example, the VSWR protection circuitry 6034 is coupled with the balance gain control circuitry 6016, which is coupled, in turn, with both the circuit autopolarization circuitry of excitation circuit 6022 and the circuitry of output phase autopolarization 6028. In one example, the VSWR 6034 protection circuitry responds to a previously determined voltage level in the output phase PAs by decreasing the gain first in the pre-excitation circuit phase, then in the circuit phase of excitation and, finally, in the PA phase. As described above, the protection circuitry of VSWR 6034 may or may not be required according to the particular MISO amplifier implementation. For example, an implementation of a GaAs MISO amplifier (gallium arsenide) would not require VSWR protection circuitry, because the breakdown voltages typical of GaAs transistors are too large to be overcome in many RF scenarios. The example of output phase 6000 includes an optional power detection circuitry. In one example, the power detection circuitry serves as a means to provide a power level feedback to the digital control module. In Figure 60, the power detection circuitry is illustrated using the power detection circuitry 6038. In one example, the power detection circuitry 6038 is coupled with the output of the PA phase of the MISO amplifier 6058. The power detection circuitry 6038 can be directly or indirectly coupled with the output of the PA phase as illustrated by signal 6040 in Figure 60. In one example, the power detection circuitry 6038 emits a signal from POWER detection 6023. The POWER detection signal 6023 may be equivalent to the POWER detection signal A 5938 or the POWER detection signal B 5940 shown in Figure 59, which are fed back (via A / D converters) to the VPA digital control module. The digital control module uses the 6023 POWER detection signal to regulate the output power of the VPA as desired.<figref>image105</figref> The optional output switching phase of the example of output phase 6000 is performed by a switch 6044 in Figure 60. In one example, the switch 6044 is coupled with one of the three outputs 6046, 6048 or 6050 of the VPA. As described above, the switch is controlled by a set of output selection signals 5776, 5778 and 5780, which are provided by the digital control module. Switch 6044 is coupled with the appropriate output according to the selected transmission mode and / or the desired output frequency requirements (eg, GSM, WCDMA, etc.). Accordingly, the polarization impedance coupling at the VPA output can be performed in various ways. In one example, as shown in Figure 60, the polarization impedances 6052, 6054 and 6056 are respectively coupled between outputs 6046, 6048 and 6050 and the output phase VSISTIN of MA2 6002. In another example, it is used a single polarization impedance and is coupled between the 6042 output of the PA phase and the VS2 phase input of MA2 6002. The advantage of the first approach is that, by placing the polarization impedance after the switch 6044, the impedance characteristics of the switch 6044 can be taken into account when selecting values ​​for the impedances 6052, 6054 and / or 6056, allowing The VPA designer takes advantage of an additional aspect to increase the efficiency of the VPA. On the other hand, the second approach requires a smaller number of polarization impedances. According to the particular MISO amplifier implementation, the example of output phase 6000 may include more or less circuitry than what is illustrated in Figure 60. In accordance with the examples disclosed herein, the example of the output phase 6000 that includes the MISO amplifier phase 6058, the optional output switching phase (switch 6044) and the output protection circuitry and optional power detection can be manufactured using a SiGe (silicon-germanium) material. In another example, the MISO 6058 amplifier phase is manufactured using SiGe, and the output switching phase is manufactured using GaAs. In another example, the PA phase (PA 6030 and 6032) and the output switching phase are manufactured using GaAs, while another circuitry of the MISO 6058 amplifier phase and the optional circuitry of the output phase are manufactured. using SiGe. In another example, the PA phase, the excitation circuit phase and the output switching phase are manufactured using GaAs, while another circuitry of the MISO 6058 amplifier phase and the optional circuitry of the output phase are manufactured. using SiGe. In another example, the PA phase, the excitation circuit phase, the pre-excitation circuit phase and the output switching phase are manufactured using GaAs. In another example, the VPA system can be implemented using CMOS for all circuitry except for the output phase (6030 or 6032) that could be implemented in a SiGe or GaAs material. In another example, the VPA system can be fully implemented in CMOS. Other variations and / or combinations of material or manufacturing materials that are used for the circuitry of the output phase are also possible, as can be understood by one skilled in the art and, therefore, are also within the scope of the examples disclosed in this document. Therefore, because different semiconductor materials have different costs and performance, the examples disclosed herein provide a variety of VPA designs that encompass a wide range of performance and cost options. 4.3.2) VPA Analog Core Implementation B Figure 61 illustrates an alternative exemplary exemplary VPA 6100 analog core implementation. For illustrative purposes, the VPA 6100 analog core is shown in Figure 61 as being connected to the 5700 digital control module, although other digital control modules could alternatively be used. The physical connection between the analog core 6100 and the implementation of digital control module 5700 is illustrated in Figure 61, as indicated by the same numerical signals in both Figure 57 and Figure 61. The 6100 analog core implementation is corresponds to an exemplary 2-branch VPA. This implementation, however, can be easily modified to a 4-branch VPA or an exemplary CPCP, as will be apparent to those skilled in the art based on the teachings herein. The 6100 analog core implementation has the same input phase and vector modulation phase as the 5900 analog core implementation, which has been described above. Accordingly, similar to the implementation of analog core 5900, analog core 6100 includes an upper band path 5964 and a lower band path 5966 for upper and lower band operation of the VPA, respectively.<figref>image106</figref> One of the differences between the 5900 analog core and the 6100 analog core lies in the output phase of the VPA. In contrast to the 5900 analog core output phase, which includes two MISO 5930 and 5932 amplifiers, the 6100 analog core output phase includes five MISO 6126, 6128, 6130, 6132 and 6134 amplifiers, divided by the path of upper band 5964 and lower band path 5966 of the analog core. In one example, the output phase includes a combination of MISO amplifiers from SiGe and GaAs. In one example, the upper band path 5964 includes three MISO amplifiers 6126, 6128 and 6130, and the lower band path 5966 includes two MISO amplifiers 6132 and 6134. Based on the selected operating band, a single amplifier of MISO, either on the upper band path 5964 or on the lower band path 5966, is active. In one example, each of the MISO 6126, 6128, 6130, 6132 and 6134 amplifiers may be dedicated to a single transmission mode (eg, WCDMA, GSM, EDGE, etc.) of the VPA. This is in contrast to the 5900 analog core, in which each of the MISO 5930 and 5932 amplifiers supports more than one transmission mode. The advantages and disadvantages of each architecture will be further analyzed in the following. As a result of having more than one MISO amplifier per path, a switching phase is necessary to couple the vector modulation phase with the MISO amplifiers in the analog core 6100. In Figure 61, this is illustrated using switches 6118, 6120, 6122 and 6124. In one example, according to the selected transmission mode, switches 6118 and 6120 couple the outputs 5939 and 5941 of the vector modulators 5922 and 5924 with one of the MISO amplifiers 6126, 6128 and 6130. Similarly, the switches 6122 and 6124 couples outputs 5943 and 5945 with one of the MISO 6132 and 6134 amplifiers, according to the selected transmission mode and / or frequency requirements. In one example, the MISO amplifier 6126 (or 6128, 6130, 6132, 6134) receives the constant envelope signals 6119 and 6121 (or 6123 and 6125, 6127 and 6129, 6131 and 6133, 6135 and 61137). The MISO 6126 amplifier (or 6128, 6130, 6132, 6134) individually amplifies signals 6119 and 6121 (or 6123 and 6125, 6127 and 6129, 6131 and 6133, 6135 and 6137) to generate amplified signals, and combines the amplified signals to generate the output signal 6141 (6144, 6146, 6148, 6150). In one example, the MISO amplifier 6126 (or 6128, 6130, 6132, 6134) combines the amplified signals by means of a direct coupling, as described herein. Other modes of combining the amplified signals in accordance with the examples disclosed herein have been described above in section 3. The output phase of the VPA 6100 analog core is capable of supporting multi-band and multi-mode VPA operation. In addition, because the output phase of the 6100 analog core can dedicate a MISO amplifier to each supported transmission mode, the output switching phase (which is performed on the 5900 analog core by the 5942 and 5944 switches) can be eliminated. . This results in a more efficient output phase (without any loss of power due to the switching phase), but at the expense of a larger microplate area. This summarizes the main compromise between the architecture of analog core 5900 and that of analog core 6100. In one example, the output phase of analog core 6100 receives optional polarization control signals from digital control module 5700. These are the output phase autopolarization signal 5761, the excitation circuit phase autopolarization signal 5763 and the gain balance control signal 5749, which have been described above with reference to the analog core 5900. In an example, the output phase of the analog core 6100 provides optional feedback signals to the digital control module 5700 of the VPA. These feedback signals include the differential branch amplitude signal 5950 and the differential branch phase signal 5948, which have been described above with reference to the analog core 5900, to enable a differential feedback approach to monitor the variations of amplitude and phase in the branches of the VPA. Likewise, similar to analog core 5900, the output power monitoring is provided using the POWER detection signals 6152, 6154, 6156, 6158 and 6160, each measuring one of the outputs 6142, 6144, 6146, 6148 and 6150 of the VPA. Because only one of the VPA outputs can be active at any time, the POWER detection signals 6152, 6154, 6156, 6158 and 6160 are added together, in one example, using adder 5952, to generate a signal which corresponds to the current output power of the VPA. Similar to analog core 5900, feedback signals from the output phase are multiplexed using an input selector 5946 that is controlled by the digital control module. Other aspects of multiplexing the feedback signals have been described above with reference to the 5900 analog core. Similar to analog core 5900, analog core 6100 can be designed to function as a pure feedback implementation by disabling any feed forward correction in the digital control module, a pure feed feed implementation by disabling supervision of feedback signals, or as a hybrid feed / feed feed implementation with a feed feed / variable feedback feed. <figref>image107</figref> In one example, the output phase of the analog core 6100 includes an optional output phase protection circuitry. In Figure 61, this is illustrated using the VSWR protection circuitry (voltage standing wave ratio) 6136, 6138 and 6140 which is coupled with the MISO amplifiers 6128, 6130 and 6134, respectively. The VSWR protection circuitry may or may not be needed depending on the actual MISO amplifier implementation. For example, it is noted that MISO 6126 and 6132 amplifiers, which are GaAs amplifiers, do not require any VSWR protection circuitry for many applications. The functions and advantages of the VSWR protection circuitry in accordance with the examples disclosed herein have been described above with reference to the 5900 analog core. The analog core 6100 includes a power supply circuitry to control and deliver power to the different phases of the analog core. In one aspect, the power supply circuitry provides means for switching on active portions of the VPA analog core. In another aspect, the power supply circuitry provides means to control the energy efficiency and / or the output power of the VPA. The power supply circuitry of the analog core 6100 is substantially similar to the power supply circuitry of the analog core 5900, the difference being that the analog core 6100 includes five MISO amplifiers as opposed to two in the analog core 5900. In Figure 61, the power supply circuitry is performed in the GMA and MA 6102 power supply circuitry, the excitation circuit phase power supply circuitry 5904, the phase power supply circuitry output 5908 and power supply circuitry of vector mod 5908. Each of the circuitry 6102, 5904 and 5906 has five output power supply signals, with only one of these five output signals being active at any time, according to the VPA's MISO active amplifier. The function and operation of the power supply circuitry of the analog core 6100 are substantially similar to those of the power supply circuitry of the analog core 5900, which has been described above. Figure 62 illustrates an example of the output phase 6200 according to the VPA 6100 analog core implementation. The example of the output phase 6200 includes a MISO 6220 amplifier phase and an output phase protection circuitry and Optional power detection. The MISO 6126, 6128, 6130, 6132 and / or 6134 amplifiers shown in Figure 61 can be implemented using an amplifier such as the MISO 6220 amplifier phase. The example of the output phase 6200 is substantially similar to the example of the output phase 6000 illustrated in Figure 60, the main difference being found in the elimination of the output switching phase (which is performed by the switch 6044 in Figure 60) in example 6200. Similar to example 6000, the MISO 6220 amplifier phase in example 6200 includes a pre-excitation circuit amplification phase, which is performed by pre-excitation circuits 6206 and 6208, a circuit amplification phase of excitation, which is performed by the excitation circuits 6210 and 6212, and an amplification phase of PA, which is performed by the output phase PAs 6214 and 6216. In one example, the substantially constant envelope input signals IN1 of MA 6202 and INPUT of MA 6204 are amplified at each phase of the MISO 6220 amplifier, before being added to the outputs of the PA phase. The input signals IN1 of MA 6202 and INPUT of MA 6204 correspond to signals 6123 and 6125 in Figure 61, for example. In one example, the MISO amplifier phase 6220 of the example of output phase 6200 is fed by power supply signals that are provided by voltage controlled power supply circuits. In another example, the MISO 6220 amplifier phase includes an optional polarization control circuitry controllable by the digital control module. In another example, the MISO 6220 amplifier phase includes circuits to enable a compensation and / or error correction feedback mechanism. In another example, the example of output phase 6000 includes an output phase protection circuitry and optional power detection circuitry. These aspects (power supply, polarization control, error correction, output protection and power detection) of the example of output phase 6200 are substantially similar to what has been described in the foregoing. with respect to the example of the output phase 6000. In accordance with the examples disclosed herein, the example of the output phase 6200 can be manufactured using a SiGe (silicon-germanium) material that includes the MISO 6220 amplifier phase and the output protection circuitry and Optional power detection. In another example, the MISO 6220 amplifier phase is manufactured using SiGe in its entirety. In another example, the PA phase (PA 6214 and 6216) of the MISO 6220 amplifier phase is manufactured using GaAs, while another circuitry of the MISO 6220 amplifier phase and the optional circuitry of the output phase are manufactured using SiGe. In another example, the PA phase and the excitation circuit phase (excitation circuits 6210 and 6212) of the MISO 6220 amplifier phase are manufactured using GaAs, while another circuitry of the MISO 6220 amplifier phase and The optional circuitry of the output phase is manufactured using SiGe. In another example, the PA phase, the excitation circuit phase and the pre-excitation circuit phase (the pre-excitation circuits 6206 and 6208) are manufactured using GaAs. In another example, the VPA system can be implemented using CMOS for all circuitry except for the output phase (6030 or 6032) that could be implemented in a SiGe or GaAs material. In another example, the VPA system can be fully implemented in CMOS. Other variations and / or combinations of material or manufacturing materials that are used for the circuitry of the output phase are also possible, as can be understood by one skilled in the art and, therefore, are also within the scope of the examples disclosed in this document. In addition, the output phases inside the same VPA can be manufactured using a different material, as illustrated in Figure 61 for example, in which the MISO amplifiers 6128, 6130 and 6134 are SiGe amplifiers and the amplifiers of MISO 6126 and 6132 are GaAs amplifiers (one or more phases of their output phase are GaAs). <figref>image108</figref> 4.3.3) VPA Analog Core Implementation C Figure 63 illustrates another exemplary VPA 6300 analog core implementation. For illustrative purposes, the analog core 6300 by way of example is shown in Figure 63 as being connected to the digital control module 5800, although other digital control modules could alternatively be used. The physical connection between the analog core 6300 and the digital control module 5800 is indicated by the same numerical signals in both figure 58 and figure 63. The implementation of analog core 6300 corresponds to an exemplary 2-branch VPA. This implementation, however, can be easily modified to a 4-branch VPA or an exemplary CPCP, as will be apparent to a person skilled in the art based on the teachings herein. The 6300 analog core implementation includes an input phase, a vector modulation phase and an amplification output phase similar to those of the 5900 analog core of Figure 59. The function, operation and control of these phases have been described. in the foregoing with reference to Figure 59. Similar to analog core 5900, analog core 6300 includes a compensation and / or correction mechanism for feedback errors. In contrast to the 5900 analog core, however, the 6300 analog core employs a receiver-based feedback mechanism, as opposed to a differential feedback mechanism in the 5900 analog core. A receiver-based feedback mechanism is one that is based on having a receiver that receives the active VPA output, generates I data and Q data from the received output, and feeds the I and Q data. generated to the digital control module. By estimating the delay between the input and output of the VPA, the feedback I and Q signals can be properly aligned with their corresponding input I and Q signals. In another example, receiver feedback includes the complex output signal (polar magnitude and phase information) instead of Cartesian I and Q data signals. In one example, this is done by coupling a receiver (not shown) to the active VPA output (5947 or 5949). In Figure 63, signals 6302 and 6304 respectively represent RF inputs of upper band and lower band to the receiver. Only one of the signals 6302 and 6304 can be active at any time, depending on whether the upper band path 5964 or the lower band path 5966 of the analog core 6300 is being used. Similarly, the receiver-based feedback mechanism includes an upper band path and a lower band path. In one example, each of the upper and lower band feedback paths includes an automatic gain controller (AGC) (6306 and 6308), a sampling and retention (S / H) I / Q circuitry ( 6314, 6316 and 6318, 6320), a switching circuitry (6322 and 6324) and optional interpolation filters (6326 and 6328). In one example, a switch 6330, which is controlled by the digital control module by means of input selection signals 5810 and 5812, couples either the upper band feedback paths or the lower band feedback paths with the module digital control Furthermore, based on the coupled feedback path, the I / Qn selection signal of digital control module 5808 controls the switching circuitry 6322 or 6324 to alternate the coupling of the I data and the Q data with the module of digital control. Other implementations are also possible, as can be understood by one skilled in the art based on the teachings in this document. In one example, AGC circuitry is used to allow the receiver to feedback useful I and Q information over a wide dynamic range of VPA output power. For example, the output signals 5954, 5956, 5958, 5960 and 5962 may vary from +35 dBm to -60 dBm in certain cell phone applications. For the I and Q data to contain accurate feedback information, it is necessary that the I and Q output of the receiver be scaled to use the majority of the input voltage range of the A / D INPUT signal. 5736, regardless of the output signal power. The 5800 digital control module is designed to control the VPA at the required output power, which allows the 5800 digital control module to determine an appropriate receiver gain to achieve the appropriate A / D input voltage that is digitized through of A / D 5732. An analog VPA core with a receiver-based feedback mechanism can be implemented as a pure feedback system, feed in advance or feedback / feed in hybrid advance. As described above, a pure feedback implementation requires a minimum or no amount of memory (RAM 5608, NVRAM 5610) in the digital control module. This may represent an advantage of an analog core implementation according to the analog core 6300, in addition to the elimination of the differential feedback measurement circuitry from the analog core. However, the analog core 6300 can be programmed to function as a pure feedback implementation by disabling any feed correction in advance in the digital control module 5800, a pure feed feed implementation by disabling the supervision of the feedback signals, or as a hybrid feed / feed feed implementation with a feed feed / variable feedback feed. <figref>image109</figref> In one example, the output phase of analog core 6300 includes an optional output phase protection circuitry. This is not shown in Figure 63, but has been described above with respect to the 5900 and 6100 analog core implementations. Other aspects of the 6300 analog core (polarization control, power supply, etc.) are substantially similar to analog core 5900, and have been described above with reference to Figure 59. Figure 64 illustrates an example of the 6400 output phase according to the VPA 6300 analog core implementation. The example of the 6400 output phase includes a 6434 MISO amplifier phase and an output switching phase. In one example, the MISO 6434 amplifier phase corresponds to the MISO amplifier 5930 and / or 5932, which is shown in Figure 63 (i.e., either or both of the MISO amplifiers 5930, 5932 can be implemented using an amplifier such as the amplifier phase of MISO 6434). The example of the output phase 6400 is substantially similar to the example of the output phase 6000 illustrated in Figure 60, the main difference being found in the elimination of the differential branch measurement circuitry (6024 and 6026) due to use of a receiver based feedback mechanism. Similar to Example 6000, the MISO 6434 amplifier phase in Example 6400 includes a pre-excitation circuit amplification phase, which is performed by pre-excitation circuits 6406 and 6408, a circuit amplification phase. of excitation, which is carried out by means of excitation circuits 6410 and 6412, and an amplification phase of PA, which is carried out by means of the output phase PAs 6414 and 6416. In one example, the constant envelope input signals IN1 of MA 6402 and INPUT of MA 6404 are amplified at each phase of the amplifier phase of MISO 6434, before being added to the outputs of the PA phase of the amplifier phase of MISO 6434. In one example, the amplifier phase of MISO 6434 in the example of output phase 6400 is fed by power supply signals that are provided by voltage controlled power supply circuits. In another example, the MISO 6434 amplifier phase includes an optional polarization control circuitry controllable by the digital control module. In another example, the example of output phase 6400 includes an optional output phase protection circuitry (not shown in Figure 64). These aspects (the power supply, the polarization control and the output protection) of the example of the output phase 6400 are substantially similar to what has been described above with respect to the example of the output phase 6000. According to the examples disclosed herein, the example of the output phase 6400 can be manufactured using a SiGe material (silicon-germanium) that includes the amplifier phase of MISO 6434, the output switching phase 6420 and the optional output protection circuitry. In another example, the MISO 6434 amplifier phase is manufactured using SiGe, and the output switching phase 6420 is manufactured using GaAs. In another example, the PA phase (PA 6414 and 6416) of the amplifier phase of MISO 6434 and the output switching phase 6420 are manufactured using GaAs, while another circuitry of the amplifier phase of MISO 6434 and the Optional circuitry of the output phase are manufactured using SiGe. In another example, the PA phase, the excitation circuit phase (excitation circuits 6410 and 6412) and the output switching phase 6420 are manufactured using GaAs, while another circuitry of the amplifier phase of MISO 6434 and The optional circuitry of the output phase is manufactured using SiGe. In another example, the PA phase, the excitation circuit phase, the pre-excitation circuit phase (the pre-excitation circuits 6406 and 6408) and the output switching phase 6420 are manufactured using GaAs. In another example, the VPA system can be implemented using CMOS for all circuitry except for the output phase (6030 or 6032) that could be implemented in a SiGe or GaAs material. In another example, the VPA system can be fully implemented in CMOS. Other variations and / or combinations of material or manufacturing materials that are used for the circuitry of the output phase are also possible, as can be understood by one skilled in the art and, therefore, are also within the scope of the examples disclosed in this document. In addition, the output phases inside the same VPA can be manufactured using a different material, as illustrated in Figure 61 for example, in which the MISO amplifiers 6128, 6130 and 6134 are SiGe amplifiers and the amplifiers of MISO 6126 and 6132 are GaAs amplifiers (one or more phases of their output phase are GaAs). 5. VPA Output Phase Real-Time Amplifier Class Control In accordance with the embodiments of the present invention, a VPA output phase can be controlled to vary its amplifier operating class according to changes in its shape path. Output wave This concept is illustrated in Figure 65 with reference to an exemplary WCDMA waveform. The graph in Figure 65 illustrates a synchronization diagram of a WCDMA output waveform envelope versus the operating class of the VPA output phase. It is noted that the output waveform envelope is directly proportional to the output power of the VPA output phase.<figref>image110</figref> It is noted that the VPA output phase amplifier class passes from a class S amplifier to a class A amplifier as the output waveform envelope decreases from its maximum value to zero. In the zero crossing, the VPA output phase functions as a class A amplifier, before switching to a higher class amplifier operation as the output waveform envelope increases. A major problem overcome by this real-time ability to control the performance class of VPA output phase amplifier is the problem of phase precision control. With respect to the example shown in Figure 65, the problem of phase precision control lies in the fact that, in order to produce high quality waveforms, at any given power level, a Dynamic output power range of 40 dB. However, the phase accuracy required to produce a dynamic output power range of 40 dB (approximately 1.14 degrees or 1.5 PS) is well beyond the tolerance of practical circuits in high volume applications. . As will be appreciated, the specific power ranges cited in this paragraph, and elsewhere in this document, are provided for illustrative purposes only, and are not limiting. The embodiments according to the present invention solve the problem of phase precision control by going through multiple kinds of operation based on the waveform path in order to maintain the best balance of efficiency versus control accuracy. practice for all waveforms. In embodiments, the dynamic output power range of the VPA output phase exceeds 90 dB. In one embodiment, at higher instantaneous signal power levels, the amplifier class in operation (the S class) is extremely efficient and the phase accuracy is easily achieved using a phase control. At lower instantaneous signal power levels, however, the phase control may not be sufficient to achieve the required waveform linearity. This is illustrated in Figure 66, which shows a graphical representation of the VPA output power (in dBm) versus the offset angle between the branches of the VPA. It can be seen that, at high power levels, a change in the offset angle results in a smaller output power change than at lower power levels. Consequently, phase control provides higher resolution power control at higher power levels than at lower power levels. Therefore, in order to withstand high resolution power control at lower power levels, other control mechanisms are necessary in addition to the phase control. Figure 67 illustrates exemplary power control mechanisms in accordance with the embodiments of the present invention using an exemplary QPSK waveform. The constellation of QPSK is imposed on a unit circle in the complex domain defined by cos (wt) and sin (wt). The constellation space is divided between three concentric and non-intersecting regions: a “phase control only” region that is outermost, a central “phase control, polarization control and amplitude control” region, and a region of "polarization control and amplitude control" the innermost. In accordance with the embodiments of the present invention, the innermost, central and outermost regions define the type of power control to be applied according to the power level of the output waveform. For example, referring to Figure 67, at lower power levels (the points that fall in the innermost region), polarization control and amplitude control are used to provide the required waveform linearity. On the other hand, at higher power levels (the points that fall in the outermost region), only the phase control (by controlling the offset angle) is sufficient. As can be understood by those skilled in the art, the control regions illustrated in Figure 67 are provided for illustration purposes only and are not limiting. Other control regions may be defined in accordance with the embodiments of the present invention. Generally, but not exclusively, the boundaries of the control regions are based on the complementary cumulative density (CCDF) function of the desired output waveform and the lateral band performance criteria. Accordingly, the boundaries of the control regions change according to the desired output waveform of the VPA. In the embodiments, the power control mechanisms defined by the different control regions enable the transition of the VPA output phase between amplifiers of different classes. This is shown in Figure 68, which illustrates, next to each other, the operation of the output phase amplifier class versus the output waveform envelope and the control regions imposed on a unit circle. Figure 69 further shows the output phase intensity in response to the output waveform envelope. It is noted that the output phase intensity closely follows the output waveform envelope. In particular, it is noted that the output phase intensity becomes completely zero when the output waveform envelope experiences a zero crossing. Figure 70 illustrates the theoretical efficiency of the VPA output phase versus the output phase intensity. It is noted that the output phase intensity waveform of Figure 70 corresponds to that shown in Figure 69. In one embodiment, the VPA output phase operates at a theoretical efficiency of 100% during 98% (or higher) of the time. It is also noted from Figure 70 the transition of the output phase between different kinds of amplifier operation according to the changes in the output phase intensity. <figref>image111</figref> Figure 71 illustrates an exemplary VPA in accordance with an embodiment of the present invention. For illustrative purposes, and not for purposes of limitation, the exemplary embodiment of Figure 71 will be used herein to further describe the various control mechanisms that can be used to result in transitions of the VPA output phase. (which is illustrated as a MISO amplifier in Figure 71) between different kinds of amplifier operation. The VPA embodiment of Figure 71 includes a transfer function module, a pair of vector modulators that are controlled by a frequency reference synthesizer, and a MISO amplifier output phase. The transfer function module receives I and Q data and generates an amplitude information that is used by the vector modulators to generate substantially constant envelope signals. The substantially constant envelope signals are amplified and summed in a single operation using the MISO amplifier output phase. In accordance with the embodiments of the present invention, the MISO amplifier output phase may result in a real-time transition between different kinds of amplifier operation in accordance with changes in the output waveform path. . In one embodiment, this is achieved by controlling the phases of the constant envelope signals that are generated by the vector modulators. In another embodiment, the amplitudes of the MISO amplifier input signals are controlled using the transfer function. In another embodiment, the MISO amplifier inputs are polarized (the polarization of the MISO inputs can be performed at any amplification phase inside the MISO amplifier) ​​using the transfer function to control the MISO amplifier operating class . In other embodiments, combinations of these control mechanisms (the phase, the input polarization and / or the input amplitude) are used to enable the MISO amplifier phase to transition between different kinds of amplifier operation. Fig. 72 is a process flow diagram 100 illustrating a procedure for real-time amplifier class control in a power amplifier, in accordance with changes in the output waveform path, in accordance with a embodiment of the present invention. The process flow diagram 100 begins in step 110, which includes determining an instantaneous power level of a desired output waveform. In one embodiment, the instantaneous power level is determined as a function of the desired output waveform envelope. Based on the determined instantaneous power level, step 120 of the process flow chart 100 includes determining a desired amplifier operation class, in which said amplifier operation class optimizes the linearity and energy efficiency of the power amplifier. In one embodiment, determining the amplifier operating class depends on the specific type of output waveform desired (eg, CDMA, GSM, EDGE). Step 130 includes controlling the power amplifier to operate in accordance with the determined amplifier operating class. In one embodiment, the power amplifier is controlled using phase control, polarization control and / or amplitude control procedures, as described herein. According to the process flow chart 100, the power amplifier is controlled in such a way that it transitions between different kinds of amplifier operation according to the instantaneous power level of the desired output waveform. In other embodiments, the power amplifier is controlled such that it makes a transition between different kinds of amplifier operation according to the average output power of the desired output waveform. In additional embodiments, the power amplifier is controlled such that it transitions between different kinds of amplifier operation according to both the instantaneous power level and the average output power of the desired output waveform. . In accordance with the embodiments of the present invention, the power amplifier can be controlled to transition from a class A amplifier to a class S amplifier, while passing through the intermediate amplifier classes (AB, B, C and D). The embodiments of the present invention control the realization of transitions of the amplifier or power amplifiers to different amplifier classes as follows: To achieve a class A amplifier, the excitation level and polarization of the power amplifier are controlled in such a way. that the driving angle of output intensity is equal to 360 degrees. The driving angle is defined as the angular portion of an excitation cycle in which the output current is flowing through the amplifier. <figref>image112</figref> To achieve a class AB amplifier, the excitation level and the polarization of the power amplifier are controlled such that the driving angle of the output current is greater than 180 degrees and less than 360 degrees. To achieve a class B amplifier, the excitation level and the polarization of the power amplifier are controlled such that the driving angle of the output current is approximately equal to 180 degrees. To achieve a class C amplifier, the excitation level and the polarization of the power amplifier are controlled such that the driving angle of the output current is less than 180 degrees. To achieve a class D amplifier, the excitation level and the polarization of the power amplifier are controlled such that the amplifier is operated in switching mode (on / off). To achieve a class S amplifier, the amplifier is controlled to generate an output signal pulse width modulated (PWM). In one embodiment, the real-time amplifier class control described above from the VPA output phase is accompanied by a dynamic change in the transfer function that is being implemented in the digital control module of the VPA This is further described in the following with respect to Figures 73-77. Figure 73 illustrates an exemplary VPA output phase according to an implementation of npn with two branches. Each branch of the VPA output phase receives a respective substantially constant envelope signal. The substantially constant envelope signals are illustrated as INPUT1 and INPUT2 in Figure 73. The transistors of the VPA output phase are coupled to each other by their emitter nodes to form a VPA output node. When the VPA output phase functions as a class S amplifier, it performs a pulse width modulation (PWM) on the substantially constant envelope signals INPUT1 and INPUT2 received. A theoretical equivalent circuit of the VPA output phase in this kind of amplifier operation is illustrated in Figure 74. It is noted that the transistors of the VPA output phase are equivalent to switching amplifiers in this kind of operation. The VPA output as a function of the offset angle θ between the substantially constant envelope signals INPUT1 and INPUT2 (assuming that INPUT1 and INPUT2 have a substantially equal amplitude of value A) is given by<figref>image113</figref> A graphic representation of this function, which has been previously described as the phase shift magnitude transform, is illustrated in Figure 76. On the other hand, when the VPA output phase functions as a class A amplifier, it emulates A perfect sum node. A theoretical equivalent circuit of the VPA output phase in this kind of amplifier operation is illustrated in Figure 75. It is noted that the transistors of the VPA output phase are equivalent to current sources in this kind of operation. The VPA output as a function of the offset angle θ between the substantially constant envelope signals INPUT1 and INPUT2 (assuming that a substantially equal amplitude of value A) is given by<figref>image114</figref> A graphic representation of this function, which has been previously described as the phase shift magnitude transform, is illustrated in Figure 76. According to an embodiment of the present invention, the amplifier operating classes A and S represent two ends of the amplifier operating range of the VPA output phase. However, as described above, the VPA output phase can transition through a plurality of other amplifier operation classes that include, for example, classes AB, B, C and D. Therefore, the transfer function that is implemented by the VPA digital control module varies within a spectrum of phase shift magnitude transform functions, with the transform functions illustrated in Figure 76 representing the boundaries of this spectrum. This is shown in Figure 77, which illustrates a spectrum of phase shift magnitude transform functions that correspond to a range of amplifier operating classes of the VPA output phase. Figure 77 illustrates 6 functions that correspond to the six amplifier operating classes A, AB, B, C, D and S. In general, however, an infinite number of functions can be generated using the functions that correspond to the two end-to-end operating classes A and S. In one embodiment, this is done using a weighted sum of the two functions and is given by (1 -K) × R (θ) + K × SQ (θ), with 0 ≤ K ≤ 1. <figref>image115</figref> 6. Summary This document provides the mathematical basis for a new concept in relation to signal processing to provide power amplification and high conversion. These new concepts allow arbitrary waveforms to be constructed from sums of waveforms that are, as regards their nature, substantially constant envelope. Desired waveforms and output signals can be constructed from substantially constant envelope constituent signals that can be created from the knowledge of the complex envelope of the desired output signal. The constituent signals are added using new, unique and novel techniques that are not commercially available, nor are taught or found in the literature or in the related art. In addition, the combination of various techniques and circuits provided in the disclosure provide unique aspects of the embodiments of the present invention, allowing for superior linearity, added energy efficiency, monolithic implementation and low cost compared to offers. current. In addition, the embodiments of the present invention are inherently less sensitive to process and temperature variations. Certain embodiments include the use of the multi-input and single-output amplifiers described herein. The embodiments of the present invention can be implemented by a combination of hardware, software and firmware. Both analog and digital techniques with or without microprocessors and DSP can be used. The embodiments of the present invention can be implemented for communications systems and electronics in general. In addition, and without limitation, mechanics, electromechanics, electro-optics and fluid mechanics can make use of the same principles for amplification and signal transduction efficiently. 7. Conclusion In the foregoing, embodiments of the present invention have been described with the help of functional building blocks that illustrate the behavior of the specified functions and their relationships. The limits of these functional building blocks have been defined arbitrarily in this document for the convenience of the description. Alternative limits may be defined as long as the specified functions and their relationships are performed appropriately. Any such alternative limits are thus found within the spirit of the claimed invention. One skilled in the art will recognize that these functional building blocks can be implemented by discrete components, application-specific integrated circuits, processors that run an appropriate software and the like and combinations thereof. While several embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not by way of limitation. Therefore, the breadth and scope of the present invention should not be limited by any of the exemplary embodiments described above, but should be defined only in accordance with the following claims and their equivalents.