System and method of reducing click and pop noise in audio playback devices

ES 2 393 440 T3

DESCRIPTION

Popping and Crackle Noise Reduction System and Procedure in Audio Reproduction Devices

Background

Field

The present disclosure is generally about audio devices and systems, and more specifically about a system and method for reducing the noise of pops and crackles in audio reproduction devices.

Background

In many audio systems, the output of an audio device is coupled to a speaker by means of a capacitor, typically called a direct current (DC) or alternating current (AC) coupling capacitor. Typically, the output of an audio device consists of an audio signal and an associated DC offset voltage. Before connecting the audio device, the voltage across the AC coupling capacitor is normally zero (0) volts. When the audio device is connected, the audio device charges the AC coupling capacitor to the associated DC offset voltage.

Charging the AC coupling capacitor produces a rising voltage that typically has frequency components within the range of human hearing. Typically, these frequency components produce undesirable noise at the speaker output that is commonly referred to in the relevant art as "popping and crackling" noise. Also, when the audio device is disconnected, the charge on the AC coupling capacitor drops, producing a falling voltage that typically also has frequency components of the human hearing range. Again, these frequency components produce undesirable popping and crackling noise at the speaker output. This is best explained with reference to the following example.

FIG. 1 illustrates a block diagram of an exemplary conventional audio system 100. Audio system 100 supplies an audio signal to speaker 150 via an AC coupling capacitor CCA. In this example, the audio system 100 consists of a first op amp AOP1, a second op amp AOP2, and resistors R1A, R1B, R2A, and R2B. The first operational amplifier AOP1 serves to amplify the input audio signal, which can be configured as a differential signal Vim and Vip. The second operational amplifier AOP2 is configured as a voltage follower to generate a DC reference voltage Vref at the output of the first operational amplifier AOP 1. Normally, this voltage V is set._ref in Vdd / 2 to optimize or enhance the dynamic range of the audio signal at the output of the first op amp AOP 1.

The Ria and Rib resistors serve as input resistors to the first op amp AOP1 from the perspective of the input audio signal Vim and Vip. Resistor R2B serves as the input resistance to the first operational amplifier AOP1 from the perspective of the reference voltage Vref generated by the second operational amplifier AOP2. Resistor R2A serves as the feedback resistor for the first op amp AOP 1.

Before the audio system 100 is connected, the voltage across the AC coupling capacitor Cca is typically approximately zero (0) volts. When the first and second operational amplifiers AOP1-2 are initially connected via power inputs EN1 and EN2, the voltage between the ends of the AC coupling capacitor Cca begins to rise from zero (0) volts towards the reference voltage Vref. Normally, the transition voltage has frequency components that are within the human hearing range. Typically this produces undesirable popping and crackling noise at the output of speaker 150.

When the audio system 100 is disconnected, the voltage across the AC coupling capacitor CCA drops from the reference voltage Vref toward zero (0) volts. Also, the transition voltage typically has frequency components that are within the human hearing range. This also produces undesirable popping and crackling noise at the output of speaker 150.

Document EP1879290 describes procedures and arrangements for controlling the starting of amplifiers while minimizing transient voltages in the associated circuitry.

US 7224218 describes a pre-charging apparatus and method for controlling pickup transients in a capacitively coupled switching power stage.

EP0281117 describes a crackling noise suppression circuit for an audio amplifier.

ES 2 393 440 T3

Document US2002 / 0094091 describes procedures, systems and circuits for controlling transient disturbances during startup and shutdown of audio devices.

Document EP1361656 describes a method and device for avoiding audio output noise at startup of a wireless telephone terminal.

US6600365 describes a method and apparatus for suppressing audio transients when an amplifier is switched between an active and a standby mode.

EP 1229639 describes a method and apparatus for eliminating or reducing audible noise during power supply switching of an audio amplifier circuit without requiring the provision of an external switch.

Document WO 98/45938 describes a method of lowering or suppressing a transient voltage comprising the step of biasing an output node for an output signal.

Summary

One aspect of the disclosure concerns an audio system that reduces or eliminates popping or crackling noise during startup and shutdown operations. In particular, the audio system comprises an amplifier, such as an operational amplifier, which includes an input adapted to receive an input audio signal and an output adapted to produce an amplified output audio signal for an associated speaker. The audio system further comprises noise reduction circuitry adapted to gently apply a voltage to the output of the amplifier, or smoothly remove it, in a manner that reduces or eliminates the popping or crackling noise generated by the associated speaker. The voltage at the output of the amplifier can be derived from the DC reference voltage source and / or the input audio signal.

In another aspect of the disclosure, the noise reduction circuit comprises a selectable current path adapted to smoothly dissipate charges from the amplifier output during shutdown operation. The smooth dissipation of the loads from the amplifier output lowers the output voltage in such a way that the transition voltage has frequency components that are substantially outside the range of human hearing. In an exemplary embodiment, the selectable current path comprises a resistor in series with the drain and source of a field effect transistor (FET), the selectable current path being coupled between the amplifier output and ground or the potential line. Vss. In response to a shutdown operation, a control signal is applied to the gate of the FET to activate the FET, allowing the loads from the amplifier output to dissipate to ground or to the potential Vss.

In yet another aspect of the disclosure, the noise reduction circuit comprises a controllable resistor device coupled between a source of a DC reference voltage and the output of the amplifier. Furthermore, the noise reduction circuit comprises a generator adapted to generate a control signal that lowers the resistance of the controllable resistor device in such a way that the DC reference voltage from the source is smoothly applied to the output of the amplifier. a way that reduces or eliminates the popping or crackling noise generated by the associated speaker during a power-up operation. The generator may comprise a ramp signal generator, and the controllable resistor device may comprise a transistor, such as a FET.

In yet another aspect of the disclosure, the noise reduction circuit comprises a controllable resistance device coupled to the input of the amplifier, and a generator adapted to generate a control signal that decreases or increases the resistance of the controllable resistance device so that the input audio signal is smoothly applied to the input of the amplifier, or smoothly removed from it, in a way that reduces or eliminates the popping or crackling noise generated by an associated speaker during a power-on or power-off operation. The generator may comprise a ramp signal generator, and the controllable resistor device may comprise a transistor, such as a FET.

Other aspects, other advantages, and novel features of the present disclosure will become apparent from the following detailed description of the disclosure when considered in conjunction with the accompanying drawings.

Brief description of the drawings

FIG. 1 illustrates a block diagram of a conventional exemplary audio system.

FIG. 2 illustrates a block diagram of an exemplary audio system in accordance with one embodiment of the disclosure.

FIG. 3 illustrates a schedule of exemplary control signals for the audio system in accordance with another aspect of the disclosure.

FIGURES 4A-D illustrate graphs of exemplary signals generated by the audio system in response to a power-on condition in accordance with another aspect of the disclosure.

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FIG. 5 illustrates a graph of an exemplary signal generated by the audio system in response to a shutdown condition in accordance with another aspect of the disclosure.

FIG. 6 illustrates a schematic diagram of an exemplary ramp generator in accordance with another aspect of the disclosure.

FIG. 7 illustrates a block diagram of a second exemplary audio system in accordance with another aspect of the disclosure.

FIG. 8 illustrates an exemplary control signal schedule for the second audio system in accordance with another aspect of the disclosure.

FIG. 9 illustrates a block diagram of a third exemplary audio system in accordance with another aspect of the disclosure.

Detailed description

FIG. 2 illustrates a block diagram of an exemplary audio system 200 in accordance with one embodiment of the disclosure. Audio system 200 includes noise reduction circuitry that is adapted to reduce or completely eliminate popping or crackling noise generated at an associated speaker output. In particular, the noise reduction circuit does this by providing a smooth rise and fall of the voltage between the ends of an AC coupling capacitor during power-up and power-down, such that the frequency components of the voltage of transition are substantially outside the range of human hearing.

More specifically, the audio system 200 comprises a first operational amplifier AOP1, a second operational amplifier AOP2, resistors Ria, Ríb, R2A and R2B, and a noise reduction circuit 210. The noise reduction circuit 210, in turn, comprises a ramp generator 212, a first field effect transistor (FET) M1, a second FET M2, and a Ra-off resistor. These devices can be implemented as one or more integrated circuits, as discrete devices, or as a combination of one or more integrated circuits and one or more discrete devices. The output of the first operational amplifier AOP1 is adapted to be coupled to a loudspeaker 250 via an AC coupling capacitor Cca, both of which may be located external to one or more integrated circuits incorporating the audio system 200.

The first operational amplifier AOP1 is adapted to amplify an input audio signal to a level sufficient to drive the associated speaker 250. In this example, the input audio signal is configured as a differential signal having a positive component Vip and a negative component V¡m. The first operational amplifier AOP1 includes a positive (+) input adapted to receive the positive component Vip of the input audio signal via the resistor Ríb. The first operational amplifier AOP1 also includes a negative (-) input adapted to receive the negative component Vim of the input signal via the resistor Ria. Resistor R2A is coupled between the output and negative input (-) of the first operational amplifier AOP1, and serves to set the gain of the first operational amplifier AOP1. The first operational amplifier AOP1 further includes a control input adapted to receive a control signal EN1 that enables or disables the amplifier Aop1.

The second operational amplifier Aop2 is configured as a voltage follower adapted to receive and produce a DC reference voltage Vref so that it can be generated at the output of the first operational amplifier Aop1. The reference voltage Vref can be set to half the power supply voltage Vdd for the first operational amplifier AOP1 (ie, Vdd / 2). This improves or optimizes the dynamic range of the audio signal generated at the output of the first op amp AOP1. The second operational amplifier AOP2 includes a positive (+) input adapted to receive the voltage V_reDC reference f, and a negative input (-) coupled to its output. The output of the second operational amplifier AOP2 is coupled to the positive (+) input of the first operational amplifier AOP1 by means of the resistor R2B. The output of the second operational amplifier AOP2 is also coupled to the drain of the first FETM1 of the noise reduction circuit 210. The second operational amplifier AOP2 further includes a control enable input adapted to receive a control signal EN2 that enables or disables the amplifier Aop2.

The ramp generator 212 of the noise reduction circuit 210 includes a control input adapted to receive a control signal EN4 that enables or disables the ramp generator 212. Ramp generator 212 includes an output that is electrically coupled to the gate of the first FET M1. Ramp generator 212 outputs an up ramping control voltage Vctl, as discussed in more detail below. The source of the first FET M1 is electrically coupled to the output of the first operational amplifier AOP1, and to the drain of the second FET M2 by means of the Raoff resistor. The gate of the second FET M2 is adapted to receive a control signal EN3. The source of the second FET M2 may be coupled to a ground potential or a relatively "negative" supply voltage Vss. Now the operation of the audio system 200 will be explained.

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FIG. 3 illustrates a schedule of exemplary control signals EN1-4 for the audio system 200 in accordance with another aspect of the disclosure. In this example, the control signals EN1-4 are binary, indicating a high logic level that the corresponding device is enabled, and a low logic level indicating that the corresponding device is disabled. It will be understood that the control signals EN1-4 may be configured in other ways to achieve operation of the audio system 200 as discussed herein. In the schedule, there are four (4) particular moments, indicated faith, t2, faith and faith. The first instant fe indicates the beginning of the power-up operation of the audio system 200. The second instant fe indicates the moment when the ramping control voltage Vctl reaches its final value (for example, Vdd). The third instant fe indicates the time when the first operational amplifier AOP 1 is enabled, and marks the end of the power-on operation. The fourth instant fe indicates the beginning of the shutdown operation of the audio system 200.

Before time t1, the control signals EN1, EN2 and EN4 are all at a low logic level, and the control signal EN3 is at a high logic level. Thus, at these logic levels, the first and second op amps AOP1-2 and ramp generator 212 are disabled, and the second FET M2 is on to effectively ground the output of the first op amp AOP1. At time fe, the control signals EN2 and EN4 go from the low logic level to the high logic level, and the control signal EN3 goes from the high logic level to the low logic level. The high levels of the control signals EN2 and EN4 enable the second operational amplifier AOP2 and the ramp generator 212, and the low logic level of the control signal EN3 turns off the second FET M2.

Enabling the second op amp AOP2 causes voltage V to occur_reDC reference f at the drain of the first FET M1. Enabling the ramp generator 212 causes the control voltage Vctl to rise relatively smoothly, as discussed in more detail below. Deactivation of the second FET M2 removes a current path between the output of the first op amp AOP1 and ground or the potential Vss.

The smooth rising control voltage Vctl causes the resistance Rds of the first FET M1 to decrease relatively smoothly. The falling resistance of the first FET M 1 smoothly applies the DC reference voltage Vref to the output of the first op amp AOP1. Consequently, the voltage between the ends of the DC blocking capacitor Cca rises relatively smoothly, such that the frequency components of the rising voltage are substantially outside the normal range of human hearing. This prevents or reduces the popping or crackling noise generated by the associated speaker 250 during power-up of the audio system 200.

The ramping voltage Vctl continues to rise until it reaches its final or maximum voltage at time fe, which can be set to substantially coincide with Vdd. At time t3, the control voltage EN1 goes from the logic low level to the logic high level to enable the first operational amplifier AOP1, and the control voltage EN4 goes from the logic high level to the logic low level to disable the ramp generator 212. Enabling the first operational amplifier AOP causes it to output the output audio signal and the DC reference voltage Vref that is applied to its positive (+) input by the second operational amplifier AOP2 through resistor R2B. Since the voltage at the output of the first operational amplifier AOP1 is already substantially at the DC reference voltage Vref due to the noise reduction circuit 210, enabling of the first operational amplifier AOP1 does not cause a substantial change in its DC voltage from output, thereby reducing or eliminating popping or crackling noise generated by associated speaker 250. Disabling the ramp generator 212 causes the control voltage Vctl to drop to substantially zero (0) volts, thereby disconnecting the first FET M1.

Between times t3 and t4, the control signals EN3 and EN4 are at logic low to effectively disable the noise reduction circuit 210 during steady state or normal operation of the audio system 200. With these control signals at the low logic level, the first and second FETs M1 and M2 turn off, so that the noise reduction circuit 210 does not significantly affect the operation of the remaining audio system 200. During steady state or normal operation between times t3 and t4, the first operational amplifier AOP1 operates by amplifying a differential input audio signal Vip and Vim. The second operational amplifier AOP2 operates to continue to produce the DC reference voltage Vref at the output of the first operational amplifier AOP1 to improve the dynamic range of the output audio signal.

As mentioned above, time t4 indicates the beginning of the shutdown operation of the audio system 200. At this time, the control signals EN1-2 go from logic high to logic low to disable the first and second operational amplifiers AOP1-2, respectively. At the same time, the control signal EN3 goes from logic low to logic high to activate the second FET M2. The OFF resistor and the second M2 FET form a current path to ground to smoothly dissipate the voltage between the ends of the DC blocking capacitor Cca. The Rapagado resistor is configured to provide relatively smooth dissipation of the output voltage, so that the frequency components of the transition voltage are substantially outside the normal range of human hearing, to reduce or eliminate popping or crackling noise. during shutdown of the audio system 200.

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FIGURES 4A-D illustrate graphs of exemplary signals generated by audio system 200 in response to a power-on condition in accordance with another aspect of the disclosure. In particular, the graph depicted in FIG. 4A illustrates the variation in time of the control voltage Vctl generated by the ramp generator 212. The graph depicted in FIG. 4B illustrates the variation in time of the resistance Rds of the first FET M1. The graph depicted in FIG. 4C illustrates the variation in time of the output voltage Vop of the audio system 200. The graph depicted in FIG. 4D illustrates the variation in time of the voltage Vload on the associated loudspeaker 250.

As the graph in FIG. 4A, the control voltage Vctl generated by ramp generator 212 may increase substantially linearly from zero (0) volts to Vdd. At some point between times ti and fe, the ramping voltage Vctl crosses the threshold voltage of the first FET M1. This causes the first FET M1 to start conducting current significantly. This is best shown by the graph of FIG. 4B, which illustrates the relatively smooth drop in resistance Rds of the first FET M1. The falling resistance Rds of the first FET M1 smoothly applies the voltage V_reDC reference f generated by the second op amp AOP2 at the output of the audio system 200. This is best shown by the graph of FIG. 4C, illustrating the output voltage rising smoothly from zero (0) volts at time t1 to substantially the DC reference voltage Vref at time t2. The voltage Vload between the ends of the load (for example, the associated loudspeaker 250) is essentially the derivative of the output voltage due to the DC blocking capacitor Cca, which basically exhibits half a cycle of a sine wave between time t1 and faith. The noise reduction circuit 210 is configured to produce a smooth voltage V load load such that its frequency components are substantially outside the normal range of human hearing to reduce or eliminate popping or crackling noise.

FIG. 5 illustrates a graph of an exemplary signal generated by the audio system 200 in response to a shutdown condition in accordance with another aspect of the disclosure. In particular, the graph of FIG. 5 shows the variation in time of the output voltage Vop of the audio system 200 during shutdown. As illustrated, at time f, which, as discussed above, indicates the start of the shutdown operation, the output voltage of the audio system 200 drops relatively smoothly until it is essentially zero ( 0) at the instant faith. The noise reduction circuit 210 is configured to produce a smoothly decaying output voltage Vop such that its frequency components are outside the normal range of human hearing to reduce or eliminate popping or crackling noise.

FIG. 6 illustrates a schematic diagram of an exemplary ramp generator 600 in accordance with another aspect of the disclosure. The ramp generator 212 of the noise reduction circuit 210 discussed previously may be configured as the ramp generator 600. The ramp generator 600 comprises a current generator 602, the p-channel Mp-m FETs, the n-channel Mn1-7 FETs, and the capacitor Cl. The sources of the Mp-m FETs are electrically coupled to the positive power supply line Vdd, and the gates of the Mp2-4 FETs are electrically coupled to the sinks of the Mp1-2 FETs and to the drain of the Mn4 FET. The gate of the FET Mp1 is electrically coupled to the gate of the FET Mn1, and both are adapted to receive the control signal EN. The Mp3 FET drain is electrically coupled to the Mns FET drain and to the Mns-6 FET gates. The drain of the Mp4 FET is electrically coupled to the drain of the Mn6-7 FETs, and to a first end of the capacitor Cl.

The current generator 602 is coupled between the positive power supply line Vdd and the drain of the FET Mn1. The source of the Mn1 FET is electrically coupled to the Mn2-3 FET sinks and to the Mn3-4 FET gates. The gates of the FETs Mn2 and Mn7 are adapted to receive the control signal ENB (for example, complement of the control signal EN). The sinks of the Mn2-7 FETs, as well as the second end of the capacitor CL, are electrically coupled to the negative power supply line Vss, which could be at ground potential.

In operation, the ramp circuit 600 is disabled when the control signal EN is at a low logic level and the control signal ENB is at a high logic level. That the EN control signal is at the logic low level deactivates the FET Mn1 to prevent current flowing through the FET Mn3 and, consequently, through the FET Mn4 due to its mirror configuration with the FET Mn3. In addition, that the EN control signal is at the logic low level activates the FET Mp1, which couples the Vdd to the gates of the FET Mp2-4, thereby deactivating these FETs. That the ENB control signal is at the high logic level activates the FETs Mn2 and Mn7 to ground the respective sinks of the FETs M N3-4 and Mn6-7 to reduce or eliminate current leakage through these transistors. Consequently, the currents I0-4 are substantially zero when the ramp circuit 600 is disabled.

When the control signal EN goes high and the control signal ENB goes low, the ramp circuit 600 is enabled. That the EN control signal is at the high logic level activates the FET Mn1 and deactivates the FET Mp1. That the ENB control signal is at the low logic level disables Mn2 and Mn7. Activation of FET Mn1 electrically couples current source 602 to the drain of FET Mn3, and deactivation of transistor Mn2 eliminates shorting or shunting of FET Mn3. This allows current I0 to flow from current source 602 to line Vss through FETs Mn1 and Mn3. This current also allows the FET Mn4 to conduct current I1.

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Deactivating the Mpi FET removes the short circuit or bypass of the Mpi FET, thereby activating the M p2, Mp3 and Mp4 FETs because Vdd is no longer applied to their gates. This allows Ii, I2, and I3 currents to flow through the Mp2, Mp3, and Mp4 FETs. Deactivation of FET Mn7 eliminates shorting or shunting of FET Mn6, thereby allowing current I4 to flow through FET Mn6. The output current Isout that produces the voltage Vctl ramping between the ends of the capacitor Cl is the difference between the currents I3 and I4 (that is, Is OUT = I3-I4).

The ramp circuit 400 can be configured to generate the ramp voltage Vctl using a capacitor Cl which may be implemented in an integrated circuit, due to its relatively small output current Isout. For example, the Mn3 FET can be configured to have a channel width 20 times (20 *) greater than the channel width of the Mn4 FET. Thus, due to the mirror configuration of the currents of the FETs Mn3 and Mn4, the current Ii is substantially 20 times less than the current I0 (that is, Ii = 1/20 * I0). Also, the Mp2 FET can be configured to have a channel width five (5) times (5 *) greater than the channel widths of the Mp3 and Mp4 FETs. Thus, due to the mirrored configuration of the currents of the Mp2, Mp3 and Mp4 FETs, the currents I2 and I3 are substantially five (5) times less than the current Ii (that is, I2 = I3 = 1/5 * Ii ). The FET M N5 can be configured to have a channel width 5/4 times greater than the channel width of Mn6. Thus, due to the mirror configuration of the currents of the FETs Mns and Mn6, the current I4 is 4/5 times the current I2 (that is, I4 = 4/5 * I2).

Using the fact that the current I1 is 20 times less than the current I0, the current I3 can be written in terms of I0 as follows:

1₃ = 1/5 * f = 1/100 * 1₀Eq. 1

Furthermore, using the fact that the current I2 is also 100 times less than the current I0, the current I4 can be written in terms of I0 as follows:

1₄ = 4/5* 1₂ = 4/500* 1₀Eq. 2

As discussed above, the output current Isout can be represented as follows:

¹ OUT = ¹3

Eq. 3

Substituting I3 and I4 as provided in Equations 1 and 2 in I3 and I4 as provided in Eq. 3, the output current Isout can be presented as follows:

Isalida = 1100 * 10 - 4/500 * 10 = 1/500 * 10Ec. 4

For example, if I0 is chosen to be approximately two (2) microamps, the Isalida output current would be approximately 4 nanoamps. Such a small current would allow the capacitor Cl to be implemented in an integrated circuit and still provide ramping Vctl control with due rise time to reduce or eliminate the popping or crackling noise generated by the associated speaker 250 during power-up operation. .

FIG. 7 illustrates a block diagram of a second exemplary audio system 700 in accordance with another aspect of the disclosure. In addition to reducing or eliminating popping or crackling noise due to applying or removing a DC reference voltage Vref to and from its output, the audio system 700 is configured to reduce or eliminate popping or crackling noise. crackles due to the DC offset voltage present in the input audio signal. The audio main amplifier of the audio system 700 amplifies the input audio signal, including the DC offset voltage, to produce a DC offset voltage at its output. During power-up, such a DC offset voltage can also cause popping or crackling noise to be generated by the associated loudspeaker.

In particular, the audio system 700 comprises a first operational amplifier AOP1, a second operational amplifier AOP2, and a noise reduction circuit 710. The first op amp AOP1 is configured to amplify the input audio signal. The second op amp AOP2 is configured to provide a DC reference voltage (for example, V_ref ~ Vdd / 2) at the output of the first op amp AOP1 to substantially improve or optimize the dynamic range of the output audio signal. The noise reduction circuit 710 is adapted to reduce or eliminate the popping or crackling noise generated by an associated speaker 750 due to the provision of the DC reference voltage Vref to the output of the first operational amplifier AOP1, and to the voltage of DC offset present in the input audio signal, ending at the output of the first op amp AOP1.

More specifically, the first operational amplifier AOP1 includes a negative (-) input adapted to receive a negative component Vim of the input audio signal via the input resistor Ria and the

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FET M3 (which is a component of the noise reduction circuit 710). The first op amp AOP1 also includes a positive (+) input adapted to receive a positive component Vip of the input audio signal via the input resistor R1B and the FET M4 (which is a component of the reduction circuit 710). noise). The first operational amplifier AOP1 further includes an output coupled to the associated speaker 750 via an AC coupling capacitor CCA. A feedback resistor R2A is coupled between the output and negative input (-) of the first operational amplifier AOP1. The first operational amplifier AOP1 includes an input adapted to receive the control signal EN2.

The second operational amplifier AOP2 is configured as a voltage follower to generate a DC reference voltage Vref at the positive input terminal (+) of the first operational amplifier AOP1. The second operational amplifier AOP2 includes a positive (+) input adapted to receive the DC reference voltage Vref. The second op amp AOP2 also includes a negative (-) input coupled to its output. The output of the second operational amplifier AOP2 is electrically coupled to the positive (+) input of the first operational amplifier AOP1 by means of the resistor R2B. The second operational amplifier AOP2 includes an input adapted to receive a control signal EN1.

The noise reduction circuit 710 comprises a ramp generator 712, the FETs M1-M4, the SWITCH resistor and controllable switch sensitive to control signals EN2, EN2B, EN5 and EN5B. In particular, the FET M1 includes a drain electrically coupled to the output of the second operational amplifier AOP2, a source electrically coupled to the output of the first operational amplifier AOP1, and a gate electrically coupled to the ramp generator 712 by means of a controllable switch EN5. . The FET M2 includes a drain electrically coupled to the output of the first operational amplifier AOP1 via the Rapagado resistor, a source electrically coupled to ground or to Vss, and a gate adapted to receive the control signal EN3.

The FET M3 includes a sink adapted to receive the negative component Vim of the input audio signal via the resistor Ria, a source electrically coupled to the negative (-) input of the first operational amplifier AOP1, and a gate electrically coupled to the gate of the FET M4 and the ramp generator 712 via the controllable switch EN2. The FET M4 includes a sink adapted to receive the positive component Vip of the input audio signal via the resistor Rib, a source electrically coupled to the positive (+) input of the first operational amplifier AOP1, and a gate electrically coupled to the gate of the FET M3 and the ramp generator 712 by means of the controllable switch EN2. The controllable switch EN2B is electrically coupled between the gates of the M3 and M4 FETs and ground or Vss. The controllable switch EN5B is electrically coupled between the gate of the FET M1 and ground or Vss. The operation of the audio system 700 is explained as follows.

FIG. 8 illustrates an exemplary control signal schedule for audio system 700 in accordance with another aspect of the disclosure. The schedule includes five (5) times t1-5 that are noted. Time ti represents the beginning of the power-on operation of the audio system 700 and, in particular, the procedure of smooth application of the DC reference voltage Vref to the output of the first operational amplifier AOP1 in a manner that reduces or eliminates the popping or crackling noise generated by associated speaker 750. Time t₂represents the end of the procedure of smooth application of the DC reference voltage Vref to the output of the first operational amplifier AOP1. The instant fe represents the beginning of the coupling of the input audio signal (which may include a DC offset voltage) to the input of the first op amp AOp1 in a way that reduces or eliminates the popping or crackling noise generated by the associated speaker 750. The instant time t4 represents the end of the procedure of coupling the input audio signal to the input of the first operational amplifier AOP1. And the instant ts represents the beginning of the shutdown operation of the audio system 700.

Before time t1, the control signals EN1, EN2, EN4 and EN5 are at a low logic level, and the control signal EN3 is at a high logic level. In this configuration, the 1st and 2nd op amps AOP1-2 and the ramp generator 712 are disabled, the Mi, M3, and m4 FETs are off, the M2 FET is on, the EN2 and EN5 controllable switches are in their open position, and the controllable switches EN2B and EN5B are in their closed position.

At time t1, the control signals EN1, EN4 and EN5 go from the low logic level to the high logic level, and the control signal EN3 goes from the high logic level to the low logic level. That the control signal EN1 is at the high logic level causes the second operational amplifier AOp2 to produce the DC reference voltage Vref at its output and at the drain of the FET M1. The control signal EN5 being at the logic high level causes the controllable switch EN5 to be in the closed position and the controllable switch EN5B to be in the open position. That the control signal EN4 is at the high logic level enables the ramp generator 712 to begin generating a first ramp control voltage Vctli. That the control signal EN3 is at the low logic level deactivates the FET M2.

Between the instants ti and fe, the first rising control voltage Vctli causes the resistance Rds of the FET Mi to decrease relatively smoothly, to smoothly apply the DC reference voltage Vref to the output of the first op amp AOP1 in a manner that reduces or eliminates clicking noise or

ES 2 393 440 T3 crackles generated by associated speaker 750, as previously discussed in more detail with reference to the previous embodiment. Already at time t2, the voltage at the output of the first operational amplifier AOP1 should be substantially at the voltage V_ref of DC reference. At time t2, the control signals EN4 and EN5 go from logic high to logic low to disable ramp generator 712, open controllable switch EN5 to uncouple gate ramp generator 712 from FET M1, and close the controllable switch EN5B to ensure that the FET M1 turns off.

At time te, the EN2 and EN4 enable signals go from the low logic level to the high logic level. For the control signal EN2 to be high, enables the first op amp AOP1, closes the controllable switch EN2, and opens the controllable switch EN2B. That the control signal EN4 is at the high logic level enables the ramp generator 712 to begin generating a second ramp control voltage Vctl2. Between times t3 and t4, the rising control voltage Vctl2 causes the resistances of the FETs M3 and M4 to drop relatively smoothly, to smoothly apply the input audio signal, including its DC offset voltage, to the input of the first operational amplifier AOP1 and consequently to the output of the first operational amplifier AOP1 in a manner that reduces or eliminates the popping or crackling noise generated by the associated speaker 750.

At times t4 and t5, the audio system 700 is operating in normal or steady state mode amplifying the input audio signal to generate an output audio signal with sufficient power level to drive the associated speaker 750. During the Normal or steady state operation, the controllable switch EN2 remains closed and the ramp generator 712 generates a logic high level to keep the FETs M3 and M4 on. At instant ts, which, as stated above, indicates the start of the shutdown operation, the control signals EN1, EN2 and EN4 go from the high logic level to the low logic level, the control signal EN3 goes from logic low to logic high, and the control signal E5 remains at logic low. This puts the audio system 700 into its off mode by disabling the first and second op amps AOP1-2 and the ramp generator 712, and connecting the M2 FET. Connecting the FET M2 causes the charges between the ends of the capacitor Cca to dissipate in a relatively smooth manner to avoid the popping or crackling noise generated by the associated speaker 750. The Rapagado resistor can be configured to provide relatively smooth dissipation of charges between the ends of the capacitor Cca.

FIG. 9 illustrates a block diagram of a third exemplary audio system 900 in accordance with another aspect of the disclosure. The audio system 900 is configured to reduce or eliminate popping or crackling noise for the case where the audio system is coupled to the directly associated speaker (eg, in the absence of an AC coupling capacitor). In particular, the audio system 900 comprises an operational amplifier AOP1, resistors Ria, Ríb, R2a and R2B, the FETs M3 and M4, and the ramp generator 902. These devices can be implemented in one or more integrated circuits, in discrete devices, or in a combination of one or more integrated circuits and one or more discrete devices.

More specifically, the operational amplifier Aop1 includes a negative (-) input adapted to receive a negative component Vim of a differential input audio signal via the resistor Ria and the drain and source of the FET M3. The operational amplifier AOP1 also includes a positive input terminal (+) adapted to receive a positive component Vim of a differential input audio signal via the resistor Ríb and the drain and source of the FET M4. It will be understood that the input audio signal need not be configured as a differential signal. Resistor R2B is coupled between the positive (+) input of the op amp AOP1 and the Vss or ground potential. The operational amplifier AOP1 includes an output coupled to the negative (-) input via a feedback resistor R2A. The output of the op amp AOP1 can be coupled to the associated loudspeaker without an interposed AC coupling capacitor. Ramp generator 902 is coupled to the gates of FETs M3 and M4 to provide them with a ramp control signal during on and / or off operation. Both the operational amplifier AOP1 and the ramp generator 902 include an enable input to receive a control signal EN1.

In operation, prior to power-up of the audio system 900, the control signal EN1 is at a logic low level to disable the operational amplifier AOP1 and the ramp generator 902. At power up, the control signal EN1 goes from logic low to logic high. This causes the operational amplifier Aop1 and the ramp generator 902 to be enabled. Ramp generator 902 generates an up ramping control voltage Vctl that smoothly lowers the resistances of FETs M3 and M4. This has the effect of smoothly applying the input audio signal (Vim and V¡p) to the inputs of the op amp AOP1. If any DC offset is present in the input audio signal, the effect of gently lowering the resistances of FETs M3 and M4 causes the amplified DC offset voltage to appear smoothly at the output of op amp AOP1. The ramp generator 902 can be configured to generate the control voltage Vctl in such a way that the transition DC offset voltage at the output of the op amp Aop1 reduces or eliminates the popping or crackling noise generated in the associated speaker 950. .

During normal or steady state operation, the ramp generator 902 continues to generate a high logic level control signal Vctl to keep the M3 and M4 FETs on to allow the audio signal of

ES 2 393 440 T3 input is coupled to the input of the operational amplifier AOP1. In response to a shutdown operation, the control signal EN1 goes from logic high to logic low to disable operational amplifier AOP1 and ramp generator 902. Alternatively, the ramp generator 902 can be configured to provide a ramp-down voltage to smoothly increase the resistances of the FETs M3 and M4 to smoothly decouple the input audio signal from the input of the op amp AOP1. This causes the voltage at the output of the op amp AOP 1 to drop smoothly to avoid or eliminate the popping or crackling noise generated by the associated speaker 950.

In one or more exemplary embodiments, the described functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. A storage medium can be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to transport or store desired program code in terms of instructions or data structures and that can be accessed by a computer. Furthermore, any connection is aptly called computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio and microwaves, then coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwave are included in the definition of medium. As used in this document, the English terms disk and disc include compact disk (CD), optical disk, digital versatile disk (DVD) [all referred to as disc], floppy disk [written disk in English], and Blu-ray disc [disc], usually designating disk in English to a medium that reproduces data magnetically, while disc in English refers to a medium that reproduces data optically with lasers. In the scope of computer-readable media they should also include combinations of the above.

Although the invention has been described in connection with various aspects, it will be understood that the invention is susceptible to further modifications. The present application is intended to encompass any variation, use, or adaptation of the invention by generally following the principles of the invention with reference to the appended claims, and including such departures from the present disclosure that are within known practice and customary within the art to which the invention belongs.