Current generation architecture for an implantable stimulator device having coarse and fine current control

ES 2 345 293 T3

DESCRIPTION

Current generation architecture for an implantable stimulator device having coarse and fine current control.

Field of the invention

The present invention relates generally to implantable stimulator devices, for example, a pulse generator used, for example, in a Spinal Cord Stimulation (SCS) system. More particularly, the present invention relates to the current source / sink architecture used to provide currents to or from the device electrodes.

Background

Implantable stimulation devices are devices that generate and provide electrical stimulation to the nerves and tissues of the body for the therapy of various biological disorders, such as pacemakers to treat cardiac arrhythmia, defibrillators to treat heart fibrillation, cochlear stimulators to treat deafness , retinal stimulators to treat blindness, muscle stimulators to produce coordinated movement of a limb, spinal cord stimulators to treat chronic pain, cortical and deep brain stimulators to treat motor and psychological disorders, and other nerve stimulators to treat urinary incontinence, sleep apnea, shoulder subluxation, etc. The present invention may find applicability in all those applications of this type, although the description that follows generally focuses on the application of the invention within a Spinal Cord Stimulation (SCS) system, as described in US patent 6,516,227 ("the '227 patent"), issued February 4, 2003 to Paul Meadows et al.

Spinal cord stimulation is a well-accepted clinical method for reducing pain in certain patient populations. As shown in Figure 1, a SCS system typically includes an Implantable Impulse Generator (IPG) 100, which includes a biocompatible cage 116 formed of titanium for example. Box 116 contains the circuitry and power source or battery necessary for the IPG to operate. The IPG 100 is coupled to the electrodes 106 via one or more electrode leads (two of these leads 102 and 104 are shown), such that the electrodes 106 form a set of electrodes 110. The electrodes 106 are carried in a flexible body 108, which also contains individual signal leads 112, 114, coupled to each electrode. The signal cables 112, 114 are in turn connected to the IPG 100 by an interface 115, which allows the conductors 102 and 104 to be connected to the IPG 110 in a detachable manner. Exemplary connector arrangements are described in US Patent Nos. 6,609,029 and 6,741,892. In the illustrated embodiment, there are eight electrodes on lead 102, labeled Ei-E₈, and eight electrodes on lead 104, labeled E₉-Ei₆, although the number of conductors and electrodes are specific to the application and therefore may vary.

The electrode assembly 110 is typically implanted along the dura of the spinal cord, and the IPG 100 generates electrical impulses that are delivered through the electrodes 106 to nerve fibers within the spinal column.

Additional details regarding the structure and function of typical IPGs, as well as IPG systems including telemetry and power / recharge details, are described in many of the documents cited in this description, with which it is assumed that the reader is familiar.

An IPG 100 may include current source / sink circuitry that is configured to supply / receive stimulating current to or to the IPG electrodes 106, and ultimately to or tissue. For example, Figure 2 shows an exemplary current source 500 and a corresponding current sink 501 used to stimulate tissue, exemplified generically as a 505 (R) charge. As one skilled in the art will understand, transistors M1 and M3 of current source 500, and transistors M2 and M4 of current sink 501, comprise a current mirror. However, other current source or sink circuitry may be used, for example that described in US Patent Application Serial No. 11 / 138,632 ("the '632 application"), filed May 26, 2005.

Both source 500 and sink 501 are coupled to a current generator 506 configured to generate a reference current, I_ref. A suitable reference current generator is described in US Patent 6,181,969 ("the '969 Patent"), issued on January 30, 2001 in the name of inventor Juan C. Gord. The reference current in both the 500/501 current source and sink is fed into a digital-to-analog converter (DAC) configured to regulate the current that is taken from the source or drawn to the sink from the 505 load or the herself. Thus, source circuitry 500 employs DAC circuitry 502, while sink circuitry 501 employs DAC circuitry 503.

The DAC circuitry 502, 503 is configured to regulate and / or to amplify an output current I_ref is determined to output current an output current I_out. Specifically, the relationship between I_ref and I_out it is determined in accordance with the input control bits arriving on the main leads 513, 513 ', which gives the DAC circuitry 502, 503 its digital-to-analog functionality. Essentially, according to the values ​​of the various control bits M of the main conductor 513, any number of output stages (i.e., transistors M1,

ES 2 345 293 T3

M2) are connected to each other in parallel in such a way that I_out can be extended from I_ref to 2^M* I_ref in increments of I_ref, $ as will be explained in more detail later with reference to Figure 4.

As shown in Figure 2, for the sake of simplicity, the current source circuitry 500 is coupled to a different electrode E_x in the IPG device 100, while the sink current circuitry 501 is coupled to an electrode E_Y different on the IPG device. However, according to the approach described in the '969 patent, each electrode in the device is actually wired to a current source 500 and a current sink 501, of which only one (or none) is activated at any one time. to allow the electrode to be selectively used as a source or sink (or as neither). This is shown in Figure 3, which shows four exemplary electrodes, E_n AND₂, E₃, and E₄, each of which has its own current source 500 and sink 501 circuitry assigned and wired. A primary clinical advantage of having control current capability at each electrode is that it allows for precise shaping of the electric field used for the stimulation of the electrode array. Systems without this capability have less field control and are subject to variations and impedance changes between electrodes.

The circuitry of current source 500 and sink 501 wired into each electrode are sometimes designated PDAC and NDAC respectively, reflecting the fact that sources 500 are typically made up of P-type transistors while sinks 501 are typically made up of P-type transistors. by N-type transistors. The use of transistors of these polarities is sensitive since the source is diverted to a high voltage (V +), for which the P-type transistors are more logical, while the sink is diverted to a low voltage (V-) , for which N-type transistors are more logical, as shown in Figure 2. The substrate connection (not shown) for the transistors would typically be connected to the appropriate power source, be it V + or V-, but could also be connected to the sources of the transistors.

As shown in Figure 3, current sources (PDAC) and sinks (NDAC) active at any given time can be programmed. Thus, as shown, the source circuitry at electrode E2 in the IPG is currently active, while the sink circuitry at electrode E3 is also currently active. At a later time, the electrodes E₂ and E₃ could be switched in such a way that E₂ now function as the sump, while E₃ function as the source, or new sources or sinks, etc. could be chosen, depending on how the logic is programmed into the IPG according to the optimal therapy for the patient in which the IPG is implanted.

One consequence of this architecture is that, as mentioned, each electrode has its own assigned source (ie PDAC) and sink (ie NDAC) circuitry. Other details of such assigned current source circuitry 500 for a particular electrode (e.g., E_x) as described in the '969 patent. Similarly, assigned current sink circuitry 501 for each electrode, similar to current circuitry 500 but differentiated from source in polarity (see for example, Fig. 2), would also be wired to electrode E_x, but is not shown for convenience in Figure 4. (However, the source and sink circuitry are shown in a simplified manner in Figure 7). The presence of a coupling capacitor typically wired to each Ex electrode is also not shown for convenience (see the '969 patent, Fig. 3, item 203).

The source circuitry of Figure 4 can be programmed to output a source current of a particular magnitude. Specifically, the circuitry as shown is capable of outputting the electrode Ex a current Iout ranging from I_ref to 127I_ref in increments of I_ref, depending on the state of the control bits (Bit <1: M>). This occurs as follows: each control bit, when selected, contributes 2^(M-1) times the value of the current to the output current, Iout, with the activation of the step transistors 530 in each of the M stages that comprise the current source. For example, if a current of 53 Iref is desired in Iout, the control bits Bit <1, 3, 5, 6> should be enabled (set low) to connect the 530 transistors₁, 530₃, 530₅, and 530₆, which contribute respectively to I_ref, 4I_ref, 16I_ref, and 32I_ref, in short, 53I_ref. Although each stage is shown to have its own current source I_ref, it would generally be the case that each stage gives rise to a single reference current (not shown for convenience), which is preferable to ensure uniformity of the current through the stages.

However, this current source / sink architecture of Figures 3 and 4 does not comprise efficient use of space in the IPG IC in which the current source / sink circuitry is manufactured. In a typical implementation of an SCS system, the IPG could contain 16 electrodes, from E₁ to E_[6. However, it is generally the case that only one PDAC (source) and one NDAC (sink) are active at the same time. Or, more rarely, four or more PDACs (sources) or NDACs (sinks) could be active at the same time. Even in an extreme case of this type, it will be seen that most PDACs (sources) and NDACs (sinks) are inactive. Furthermore, even for those electrodes that are active at a particular time, only one source 500 or sink 501 circuitry can be active for that electrode. The result is that most of the time, most of the PDACs or NDACs on the IPG 100 are not being used. When PDACs or NDACs are considered to occupy significant space in the integrated circuit (see Fig. 4), establishing such redundancy for each electrode seems ineffective.

Another current source / sink architecture is described in the aforementioned '227 patent and particularly in Figure 4A of the' 227 patent, highlights of which are summarized in the present application in Figures 5 and 6. As shown In Figure 5, the architecture of the '227 patent also uses a plurality

ES 2 345 293 T3 of current sources and sinks, and additionally uses a low impedance switching matrix that intervenes between the sources / sinks and the electrodes E_x. It should be noted that each source / sink pair is wired together at the nodes 333, such that the switching matrix intervenes between the common nodes 333 and the electrodes. Of course, only one source or sink in each pair is activated at a time, and thus point 333 of any pair will act as a current source or sink at any given time. With proper control of the switching matrix, any of the 333 nodes (and therefore any of the PDAC / NDAC pairs) can be connected to the E electrodes._x anytime.

Although this is generally a suitable architecture, the architecture of Figures 5 and 6 suffers from disadvantages. First, this architecture puts additional resistance - that is, the resistance of the switch matrix switches - in the output path between the power source in the DAC circuitry and the electrode. As explained in the aforementioned '632 application, it is generally desired to minimize resistance between the power source and the electrode. Thus, and referring to Figure 6, which shows the architecture of Figure 5 in additional detail, it is desired that the resistance be minimized in the output path between the V + or V- power supply and an electrode. given E_x. This is because any resistance in the output path will lead to a voltage drop in the output path (the resistance of the output path multiplied by I_out) which is otherwise not useful in the context of circuitry. But in the architecture of Figures 5 and 6, it can be seen that three elements are connected in series between the power supplies and the electrode: the current mirror, the bit selection transistor, and the transistor (switch). of the low impedance switching matrix. Due to the additional resistances of these components, and specifically the additional resistance of the switch matrix switches, the power (that is, the product of the output path resistance times I_out²) is wasted. In an implantable stimulator device, such unnecessary loss of power is regrettable, because battery life in such devices is critical and is beneficially intended to be as long as possible.

On the other hand, the architecture of Figures 5 and 6 is further inefficient from an arrangement perspective. Due to the common node 333 between a given PDAC source and NDAC sink pair, only one DAC in each pair can be active at any one time. Thus, and like the architecture of Figures 3 and 4, the DAC circuitry is guaranteed not to be used at any particular time. More specifically, at least 50% of the DAC circuitry (the unselected DAC of a pair), and probably more, will be unused at any given time, which in turn is wasteful use of the arrangement in the integrated circuit.

In summary, the implantable stimulator technique, or more specifically the IPG or SCS system technique, would benefit from an architecture that allows variable currents to be delivered across a number of electrodes, but in a more space efficient manner.

Additionally, such an improved architecture would also preferably allow fine adjustments of the current to be supplied by the source or sent to the sink. In this regard, it has been recognized in the art that it may be beneficial to finely adjust the value of the current to be supplied by the source or sent to the sink at a particular electrode in increments less than I_ref. For example, in the aforementioned '969 patent, and as shown herein in Figure 7, it is disclosed that the 500/501 source / sink circuitry may include a stage or stages 550 that provide a fraction of the reference current, I_ref. These stages 550 are controlled by another control bit, Bit <0> (designated as "0+" for the source and "0-" for the sink). Specifically, as noted in the '969 patent, fractional values ​​of (1/2) "(ie, 1/2 * I_ref, 1/4 * I_ref, 1/8 * I_ref, etc.) or 1 / m (for example, 1/2 * I_ref, 1/3 * I_ref, etc.), or multiples thereof, by step (s) 550. See the '969 patent, column. 6, l. 43rd column. 7, l. 6.

Providing the ability to include the reference current fractions, I_refIn general current, fine current adjustments (via steps 550) can be made to otherwise coarse current adjustments provided by the rest of the circuitry. However, the overall result is still one that is not terribly space efficient, because as noted above, much of the current source and sink circuitry is guaranteed to be unused at any given time.

Summary

Described herein is a current generation architecture for an implantable stimulator device such as an Implantable Impulse Generator (IPG) or more specifically for a Spinal Cord Stimulation system (SCS). In architecture, the current source and sink circuitry are both divided into coarse and fine portions, which respectively have the ability to provide a coarse and fine amount of current to a specified IPG electrode.

The coarse portion of the current circuitry is distributed across all of the electrodes and can therefore source or sink the current to / from any of the electrodes. Specifically, the thick portion is divided into a plurality of stages, each of which is capable, via an associated switch bank of providing from the source or withdrawing to the sink an amount of current to any of the electrodes of the device or from the same. Each stage is preferably formed of a current mirror to receive a reference current and to output a current to the switch bank of that stage. The output current in the stage preferably represents a scaled version of the reference current, i.e. the output current

ES 2 345 293 T3 comprises the reference current multiplied by a scalar in the stage, which can be established by wiring a desired number of output transistors in the current mirror in parallel. In a preferred embodiment, the scalars of the various stages are set uniformly to provide a coarse increase in reference current to the switch banks, and thus to any of the electrodes.

The fine portion of the current generating circuitry, in the preferred embodiment, includes source and sink circuitry assigned to each of the electrodes of the device. The assigned circuitry preferably comprises digital-to-analog current converters (DACs). The DACs include a current mirror and also receive current from the aforementioned reference. The reference current is amplified in the DACs in fine increments by appropriate selection of the fine current control signals. When the coarse and fine current control circuitry is used in tandem, sufficient fine current control can be achieved at any electrode and in a space and power efficient manner.

Brief description of the drawings

The aforementioned and other aspects of the present invention will be more apparent from the more specific description thereof given below, presented in conjunction with the following drawings, in which:

Figure 1 shows an exemplary implantable pulse generator (IPG) and its associated electrode assembly in accordance with the prior art.

Figure 2 shows an exemplary prior art current source and current sink corresponding to an IPG, each having digital-to-analog converter (DAC) current circuitry in series with a load.

Figure 3 shows a prior art architecture for coupling current sources and sinks to a plurality of electrodes using the assigned circuitry wired at each electrode.

Figure 4 shows the complexity of the arrangement of one of the current sources of Figure 3.

Figure 5 shows a prior art architecture for coupling current sources and sinks to a plurality of electrodes using a switch matrix.

Figure 6 shows the disadvantages regarding the architecture of Figure 5 in terms of unnecessary power consumption within the IPG.

Figure 7 shows a prior art modification to the architecture of Figures 3 and 4 in which a fractional amount of the reference current can be provided to an electrode.

Figures 8A and 8B illustrate an improved current source / sink architecture having coarse and fine current control in accordance with one embodiment of the invention.

Figure 9 shows current mirror circuitry that can be used in the thick portion of the circuitry of the architecture of Figures 8A and 8B.

Figure 10 shows the switch banks used in the coarse portion of the circuitry to distribute a coarse amount of current from any of the current mirrors to either of the electrodes.

Figure 11 shows the PDAC used in the fine portion of the architecture circuitry of Figures 8A and 8B that is assigned to each electrode.

Figures 12A and 12B illustrate an alternative embodiment to that shown in Figure 8A and 8B in which two different reference currents are used for the thick and thin portions.

Figure 13 illustrates the control signals necessary to operate the described embodiment of the current circuitry shown in Figures 8A and 8B.

Corresponding reference characters indicate corresponding components throughout the various views of the drawings.

Detailed description

The following description is currently viewed as the best mode of carrying out the invention. This description is not to be taken in a limiting sense, but is made simply for the purpose of describing the general principles of the invention. The scope of the invention should be determined by reference to the claims and their equivalents.

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In principle, it is noted that the present invention can be used with an implantable pulse generator (IPG), or a similar electrical stimulator and / or electrical sensor, which can be used as a component of various types of numerous stimulation systems. The description that follows relates to the use of the invention within a spinal cord stimulation system (SCS). However, it should be understood that the invention is not limited thereto. Rather, the invention can be used with any type of implantable electrical circuitry that could benefit from efficient current source / sink circuitry. For example, the present invention can be used as part of a pacemaker, a defibrillator, a cochlear stimulator, a retinal stimulator, a stimulator configured to produce the coordinated movement of a limb, a cortical and deep brain stimulator, or in any other nerve stimulator configured to treat urinary incontinence, sleep apnea, shoulder subluxation, etc.

As noted above, exemplary embodiments of the present invention involve the architecture used in the current source and sink circuitry, sometimes referred to as the PDAC and NDAC circuitry, respectively. Previous approaches were summarized in the background section of this description. But as observed, these architectures suffered from several disadvantages.

A new and improved current generation architecture is illustrated in Figures 8-13. The new architecture, like the previous architectures, employs a current source and current sink circuitry, which receives in Figures 8A and 8B respectively the circuitry designations 400 and 401, which would logically be realized, for example, in JC analogical. As shown, the source circuitry 400 is in solid lines while the sink circuitry 401 is illustrated in broken lines. However, the sink circuitry 401, although not specifically discussed, is similar in design and operation to the source circuitry 400, although different in polarity (e.g., connection to the negative V- power source, use of N-channel transistors, etc.). In other words, and for the sake of simplicity, and to avoid redundancy, source circuitry 400 is specifically discussed in this description, although it should be understood that sink circuitry 401 is similar in all material respects and of equal importance.

Unique to the new architecture, each source / sink circuitry 400/401 is divided into two portions: a thick portion 402 (Fig. 8A) and a thin portion 403 (Fig. 8B). As the name suggests, the thick portion 402 allows a thick amount of current to be delivered to a particular electrode . In other words, the amount of current that can be programmed to be sourced or withdrawn as a sink at a particular electrode by the thick portion 402 can be incremented in a relatively large type of increment. In contrast, the amount of current that can be programmed to be sourced or withdrawn as a sink at a particular electrode by the fine portion 403 can be incremented in a relatively small type of increment. Having both thick and thin portions 402 and 403 allows efficient and dynamic control of the current in a particular electrode, as will be explained later.

Because they are different in architecture and operation, the thick and thin portions 402/403 of the current circuitry are discussed separately, with the thick portion 402 discussed first.

Unlike the prior art architecture of Figures 3 and 4, the coarse current circuitry 402 preferably does not involve dedicating or wiring the source and sink circuitry to each E₁ to E_N in the IPG 100. Instead, the thick portion 402 of the source 400 and sink 401 circuitry is shared or distributed among the various electrodes by means of a network of switch banks 405, as will be explained later.

As shown, the source circuitry 400 comprises various current mirrors 410 and various switch banks 405. Specifically, there are a number L of current mirrors 410 and switch banks 405. Each switch bank comprises N switches, corresponding to the number of electrodes in the IPG 100. Thus, there are a total of N * L 417 switches in the 405 switch banks, controlled by N * L control signals (C_N,_L). As shown in Figure 10, the control signals to switches 417 may need to be level switched to the appropriate DC values ​​for switches 417, which can easily be produced by means of level switches 415, as you will understand. the skilled in the art. Switches 417 are preferably single transistors of a logical polarity depending on whether they are present in source circuitry 400 (P-channels) or sink circuitry 401 (N-channels). However, other structures could also be used for the switches 417, such as pass gantries or transmission gantries, etc.

The current mirrors 410 of the thick portion 402 receive a reference current, I_ref. Because it can be useful to set this reference current to a particular value, a PDAC 407 can be used to convert an initial current from the reference to the true reference current I_ref sent to each of the current mirrors 410. The PDAC 407 may comprise any structure known in the art for programming the amplification of a current based on digital inputs. For example, the PDAC can be constructed as in Figure 4. As shown, the PDAC 407 scales the initial reference current Ii by a factor Z to produce the true reference current I_ref. In this way, the currents ultimately sent to the electrodes can be further (and globally) varied by adjusting the gain of the PDAC 407. If smaller current resolutions are required in the coarse and fine portions 402 and 403, they can be reduced by means of the appropriate digital control of the PDAC. If higher total currents are required, Z can be increased analogously. Also, since

ES 2 345 293 T3 that the PDAC 407 is digitally controllable, it can be controlled to various values ​​at various times. That being said, however, the PDAC 407 is not required in all embodiments of the invention, and the reference current I_refit can be provided in different ways.

The various current mirrors 410 take the reference current I_ref and scale that current to produce the desired magnitude currents in each of the L stages of the thick portion 402. In this way, the first stage scales I_ref by the A₁, the second by A₂, and so on. The various scalars A₁, TO₂,... TO_LThey may be different or they may be the same in each of the stages. For example scalars can increase exponentially (Ai = 1, A₂= 2, A₃= 4, A₄= 8, etc.), or increase linearly (Aj = l, A₂= 2, A₃= 3, etc.), or they may remain the same. (In this sense, it can be said that a current is "scaled" even if the scalar of the stage is equal to one).

In an exemplary embodiment, each of the scalars A₁ to A_L are set to the same value 5 and thus each of the L stages outputs the same current value (5I_ref) to their respective 405 banks of switches. To set this amount of gain in each of the L stages, five transistors 413 are placed in parallel to the balance transistor 414 in the output stages of the current mirrors 410, as shown in Figure 9. However, You should note that current mirrors 410 are simply an example of a current converter, that is, a circuit used to convert a current (I_ref) in another stream (A_x I_ref). Many other circuits capable of performing this function are known in the art, therefore the use of current mirrors at each stage should be understood as merely exemplary.

In further distinction to the architecture of Figures 3 and 4, it is noted that the current mirrors 410 in the coarse current circuitry 402 are not individually selectable in and of themselves, that is, they do not have transistors of Bit selection as in the DACs in Figures 3 and 4. They are always on and supplying current to switch banks 405, with the current selection or not of a particular current mirror 410 occurring in its given switch bank 405.

As shown in Figures 8A and 10, and as previously noted, each of the L switch banks 405 contains N switches, S_N, each of which is capable of routing the output current of its current mirror 410_X (TO_X I_ref) to any of the electrodes E_X on the IPG 100, depending on the state of the current coarse control signals, C_N,_L. Thus, at each stage X, the control signal C_Y._X you can send that current from that stage to E_Y. In other words, each stage can be controlled to send its output current to more than one of the electrodes and thus can affect the current at any given electrode, and the multiple stages can work together to produce a current at one electrode. given.

For example, each current mirror 410 is assumed to have a scalar A = 5, such that each sends 5I_refto their respective 405 bank of switches. It is further assumed that there are 19 stages, such that all 410 current mirrors together can supply a maximum current of 95I_ref. If at electrode E₂ a current of 50I is desired_ref, switches 417 could be closed in any 10 of the stages: the first 10 stages (C₂,₁ to C₂,₁₀); the last 10 stages (C_2J0 to C₂,₁₉); etc. Similarly, multiple electrodes can be stimulated at the same time. For example, assume that you want 50I_ref at electrode E₂; 10I_ref at electrode E₅, and 15I_ref at electrode E₈. This could be achieved by simultaneously activating the following coarse control signals: (C₂,₁ to C₂,₁₀), (C₅,₁₁ to C₅,₁₂), (C₈,₁₃ to C₈,₁₅). Of course, at some point the total amount of current that can be drawn from source circuitry 400 (or from sink circuitry 401) at any given time will be dictated by the load that the compliance voltage V + can handle.

Not every stage L would necessarily require N switches. For example, a given stage could comprise fewer than N switches, provided there is the ability to send the current from that stage to a particular electrode E_x. On the other hand, it is not necessary for each X-th switch in switch banks 405 to supply current to the X-th electrode, EX. In summary, while Figure 8A illustrates a preferred embodiment, other designs are possible that still achieve the advantages of the architecture described herein.

Because the gain in each of the current mirrors 410 in the exemplary embodiment is A = 5, the minimum current resolution provided by any of the L current mirrors 410 is 5I_ref, which can be thought of as coarse current resolution of coarse portion 402 of source current circuitry 400. Accordingly, to further provide the ability to make fine adjustments to the current provided at the electrodes, the fine current source and sink circuitry 403 are also provided.

As shown in Figure 8B, and differently from the thick portion 402, the thin portion 403 is preferably wired to each of the N electrodes. In this regard, thin portion 403 is similar to the architecture of Figures 3 and 4, which further utilized the assigned source and sink circuitry at each electrode. As noted when discussing the architecture of Figures 3 and 4, the use of the assigned source and sink circuitry at each electrode can be inefficient (guaranteed unused circuitry, etc.). However, any inefficiencies in this regard is offset by the concurrent use of the coarse circuitry 402 to set the current at any given electrode, as will be explained below.

In a preferred embodiment, and as shown in Figure 8B, the thin portion 403 of the source circuitry 400 comprises a PDAC 409 at each electrode. (In addition, each electrode will preferably also have a corresponding NDAC for the sink current, as shown in dotted lines in Fig. 8B, but not covered in

ES 2 345 293 T3 for the sake of simplicity). Such PDAC 409s may be similar in design and architecture to the PDAC 407 used to set the reference current, I_ref (see Fig. 8a), but again any current circuitry can be used.

A preferred embodiment for PDACs 409 used in thin portion 403 of source circuitry 400 is shown in Figure 11. As can be seen in Figures 8B and 11, each PDAC 409 receives the reference current from the PDAC 407, I_ref (see Fig. 8A), as well as fine current control signals (F_j,_n) used to set the current output value for each PDAC 409. As shown in Figure 11, each PDAC 409 preferably constitutes a current mirror having a balancing transistor 424 and a plurality (J) of output transistors 422 (stages ), each blocked by one of the J control signals (F_or to F_Jx). Each of the output transistors 422 is connected in parallel, and they are allowed to contribute I_ref (i.e., the input current) to the output current, depending on which of the transistors 431 are selected by the fine current control signals F_j,_n.

Because they are wired in parallel, the more fine current control signals that are enabled for any given stage, the higher the current output for that stage, which in effect sets the B gain for that stage. For example, if only Fi is enabled,_x for a given stage, then the current output of that stage equals I_ref (that is, B = l). If F are enabled₁,_x and F₂,_x, then the current output for stage (electrode) X is equal to 2I_ref(that is, B = 2), etc. In a preferred embodiment, J = 4, such that there are four output transistors 431 in each stage, and therefore each stage (PDAC) 409 can output a current 4I_ref, which requires, of course, that all current fine control signals (i.e. Fi,_x to F_j,_x) for a given stage (electrode). If necessary, level shifters 430 can be used to convert the fine control signals to appropriate levels to control switches 431.

In other words, it can be given as a source, depending on the state of the control signals F_j,_n for each electrode, a minimum of 0I_ref and a maximum of 4I_ref, in increments of I_ref, by the fine portion 403 of the source current circuitry 400 for any given electrode E_x. (Again, sink circuitry 401 would be similar). Note therefore that the fine portion 403 has a current resolution, I_ref, which is less than the current resolution of the thick portion 402.5I_ref. Due to this difference in resolution, both portions can be used simultaneously to establish a particular current at a given electrode. For example, and returning to the example illustrated in the background, it is assumed that it is desired to provide as a source a current of 53I_ref at electrode E₂. In such an embodiment, any of the ten current sources 410 can be activated by means of the coarse control signals that correspond to electrode E₂ (C_x,₂) to provide 50I_ref to electrode E₂. Similarly, any of the three fine control signals corresponding to electrode E can be activated.₂ (F_x,₂) to provide an additional current value 3I_ref in addition to the 50I value_ref provided by the thick portion, resulting in the desired total current of 53I_ref.

Of course, electrode-assigned PDACs 409 can provide fine current resolution using other designs, and the particular design of the PDACs is not critical to embodiments of the invention.

As a person skilled in the art will appreciate, it is a matter of design choice as to how many coarse L stages are used and how many fine J stages are used, and these values ​​can be subjected to optimization. However, if it is assumed that J stages are used in thin portion 403, then the number of L stages used in thick portion 402 is preferably equal to (100 / (J + I)) - 1. Thus, if J is equal to 4, the number of stages L will be equal to 19, thereby allowing the thick portion 402 to supply approximately 95% of the current range to any electrode E_x with a resolution of approximately 5%. In this case, the fine portion 403 supplies approximately the remaining 5% of the current to any electrode E_x with the highest resolution about 1%. However, these values ​​are for example only.

As shown in the Figures, it is preferred to use the same reference current, I_ref, as input to stream mirrors 410 in thick portion 402 and PDAC 409 in thin portion. However, this is not strictly necessary. For example, in Figures 12A and 128, two PDACs 407c and 407f are used to respectively set various reference currents, I_ren, and I_ref2, in the thick and thin portions 402 and 403. By programming the PDAC 407c and 407f accordingly, these two reference currents can be one equal to a scalar by the other (that is, I_ref1 = Q * I_ref2). I am supposed to_ref1 is 5 times the value of I_ref2 (Q = 5). It is further assumed that only a single output transistor 413 (Fig. 9) is used in the current mirrors 410 in the thick portion 402. Based on these assumptions, the circuitry would function as discussed above: each PDAC 409 of the portion fine 403 outputs a current with fine resolution, I_ref2, while each stage of the coarse portion 402 outputs a current with coarse resolution, I_ref1 = 5I_ref2. However, in such an embodiment, it would be necessary to isolate the thick and thin portions 402 and 403 and provide isolated compliance voltages (power supplies), V1 + and V2 +, to each as shown.

Several advantages are achieved with the new current source / sink architecture of Figures 8-13.

First, by dividing source 400 and sink 401 circuitry into portions 402 coarse and 403 fine, the number of control signals is reduced versus schemes that offer only unified resolution. The control signals necessary to operate and control the described current source / sink circuitry are shown in Figure 13. The coarse control signals (C_n,_l) and fine (F_j,_n) for both the source circuitry (PDAC; designated with a "+") and sink circuitry (NDAC; designated with a These control signals are ultimately generated by a 570 microcontroller, which may be the microcontroller

ES 2 345 293 T3 used otherwise to execute the logic functions in the IPG. Alternatively, the current source / sink circuitry may be implemented in an analog integrated circuit, which receives the control signals from a digital integrated circuit. Once again the specific details regarding the integration of the current source / sink circuitry with the logic can take place in any number of ways, as one of ordinary skill in the art will readily recognize.

Second, and unlike the prior art architectures discussed above, the circuitry is kept to a minimum occupancy by reducing the use of allocated circuitry that might otherwise be guaranteed to go unused at specific times throughout. weather. In large part, this advantage is a result of the distributed nature of the thick portion 402 of the circuitry across all of the electrodes. As long as the described design does not rely on the use of some assigned circuitry - specifically, the thin portion 403 - that circuitry is preferably kept to a minimum. In any case, such additional assigned circuitry is a good trade-off when it is recognized that it reduces the number of control signals required.

Third, compared to the prior art matrix switcher approach of Figures 5 and 6, the new architectures of Figures 8-12 comprise one less component in the output path, which reduces voltage drops. unwanted in the exit path and results in energy savings. As can be seen by making a brief reference to Figures 9 and 10, which show the circuitry in the thick portion 402, only two components are involved between the V + power supply and a given electrode: the transistor (s) 413 of current mirror output and select switches 417 of switch banks 405. On the other hand, as regards the thin portion 403, shown in Figure 11, only two components again intervene between the power supply V + and a given electrode: the current mirror output transistors 422 and the switches 431 of selection. In addition to reducing the series resistance of the circuit by eliminating the series switching matrix, the selector switches 417 make the current sources 410 linear by reducing the Vds voltage drop across the current mirrors on the electrodes that require less voltage. compliance than the difference between V + and V-. If it weren't for switches 417, all of the excess compliance drop would take place across current mirror 410 and the current would tend to be slightly higher than programmed into electrodes that require less compliance voltage.

It should be understood that the direction in which the stream flows is a relative concept, and various conventional arrangements can be used to define whether streams flow to or from various sources. In this regard, the arrows showing the directions of current flows in the Figures refer to a current flowing to or from various nodes of the circuit, therefore references to currents arising from source or are withdrawals in sinks, etc. they are understood they should all be understood as relative and not in any limiting sense.

Reference to an implantable electrode adjacent to the tissue to be stimulated should also be understood to include the implantable stimulator device electrodes, or associated electrode leads, or any other structure for stimulating the tissue.

On the other hand, it should be understood that an implantable electrode adjacent to the tissue to be stimulated without regard to any output capacitance, such as the coupling capacitances C_N included in the manifold connector 192 or elsewhere (see Fig. 7). This is so because it should be understood that the nodes on either side of such a coupling capacitor or any other output impedance are not, in the context of this invention, materially different from an architectural point of view, such that any node would be considered as the node of the implantable electrode adjacent to the tissue to be stimulated. The same would be true for other impedances, for example if an output resistor were used in addition to or instead of a coupling capacitor.

Although the invention described herein has been through specific embodiments and applications thereof, numerous additional modifications and variations could be made by those skilled in the art without departing from the scope of the claims that define the invention.