Framing structure for digital broadcasting and interactive services
Abstract
A method for providing carrier synchronization in a digital and interactive broadcasting system, the method comprising: receiving a frame (400) transmitted according to a carrier signal, wherein the frame (400) includes a plurality of separate segments (401) by a plurality of auxiliary resource fields, and each auxiliary resource field includes a preamble (405) and pilot blocks corresponding to the respective segments (401); generate estimated phase values associated with the carrier signal based on the auxiliary resource fields, in which for each of the segments (401), the estimated carrier phase values of the auxiliary resource fields correspond to a principle and an end of the segment (402); estimate the phase of the carrier signal associated with a random data field within the segments (401) based on the estimated phase values and random data; and estimating the frequency of the carrier signal based on the auxiliary resource fields, in which the step of estimating the phase is performed in the table (400) on a segment by segment basis, and for each segment comprises the following steps : estimate a value of an instantaneous carrier frequency from the estimated carrier phase values based on the auxiliary resource fields; for each of the segments (401), perform a direct phase scan on the segment random data field using a loop (400) locked in initialized phase with the estimated carrier phase value from the auxiliary resource field at the beginning of the segment, in which the instantaneous carrier frequency is eliminated from the symbols received from the random data field before direct scanning; for each of the segments (401), perform a reverse scan on the segment random data field using the loop (900) locked in initialized phase with the estimated carrier phase value from the auxiliary resource field at the end of the segment adjusted with the estimated value of the instantaneous carrier frequency, at which the instantaneous carrier frequency is removed from the symbols received from the random data field before the reverse scan; determine whether the direct scan or reverse scan is in sync; and calculate the final carrier phase estimates on the random data field by combining the estimated carrier instantaneous frequency value, the direct scan phase estimates and the reverse scan phase estimates.

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24 claims: 1 independent, 23 dependent
- 1ES 2 340 552 T3 REIVINDICACIONES 1. Un método para proporcionar sincronización de portadora en un sistema de radiodifusión digital e interactivo, comprendiendo el método:recibir un cuadro (400) transmitido según una señal de portadora, en el que el cuadro (400) incluye una pluralidad de segmentos (401) separados por una pluralidad de campos de recurso auxiliar, y cada campo de recurso auxiliar incluye un preámbulo (405) y bloques de piloto correspondientes a los segmentos respectivos (401);generar valores estimados de fase asociados con la señal de portadora basado en los campos de recurso auxiliar, en el que para cada uno de los segmento (401), los valores estimados de fase de portadora de los campos de recurso auxiliar corresponden a un principio y un final del segmento (402);estimar la fase de la señal de portadora asociada con un campo de datos aleatorios dentro de los segmentos (401) basado en los valores estimados de fase y datos aleatorios;y estimar la frecuencia de la señal de portadora basado en los campos de recurso auxiliar, en el que el paso de estimar la fase es realizado en el cuadro (400) sobre una base de segmento por segmento, y para cada segmento comprende los pasos siguientes: estimar un valor de una frecuencia instantánea de portadora a partir de los valores estimados de fase de portadora basado en los campos de recurso auxiliar;para cada uno de los segmentos (401), realizar un barrido directo de fase sobre el campo de datos aleatorios del segmento usando un bucle (400) enclavado en fase inicializado con el valor estimado de fase de portadora procedente del campo de recurso auxiliar al principio del segmento, en el que la frecuencia instantánea de portadora es eliminada de los símbolos recibidos del campo de datos aleatorios antes del barrido directo;para cada uno de los segmentos (401), realizar un barrido inverso sobre el campo de datos aleatorios del segmento usando el bucle (900) enclavado en fase inicializado con el valor estimado de fase de portadora procedente del campo de recurso auxiliar al final del segmento ajustado con el valor estimado de frecuencia instantánea de portadora, en el que la frecuencia instantánea de portadora es eliminada de los símbolos recibidos del campo de datos aleatorios antes del barrido inverso;determinar si el barrido directo o el barrido inverso está en sincronización;y calcular las estimaciones finales de fase de portadora sobre el campo de datos aleatorios combinando el valor estimado de frecuencia instantánea de portadora, las estimaciones de fase de barrido directo y las estimaciones de fase de barrido inverso.
- 2Un método según la reivindicación 1, en el que los bloques de piloto son independientes del campo de datos aleatorios.
- 3Un método según la reivindicación 2, en el que cada bloque de piloto exhibe un modelo que está basado en una señal de onda continua mezclada según una secuencia predeterminada.
- 4Un método según la reivindicación 1, en el que cada bloque de piloto tiene una longitud de 36 símbolos y cada segmento tiene una longitud de 1.440 símbolos.
- 5Un método según la reivindicación 1, en el que uno de los bloques de piloto es insertado en un transmisor configurado para emitir el cuadro (400) transmitido y realizar los pasos de:determinar si una posición de inserción de piloto coincide con la posición de uno de los preámbulos.
- 6Un método según la reivindicación 5, en el que el transmisor está configurado además para realizar el paso de:esperar un número predeterminado de símbolos, en el que el número predeterminado de símbolos corresponde a la longitud del segmento.
- 7Un método según la reivindicación 1, en el que el campo de datos aleatorios tiene símbolos especificados por esquema de modulación que incluye uno de modulación por desplazamiento de fase binaria (BPSK), modulación por desplazamiento de fase en cuadratura (QPSK), modulación por desplazamiento de fase de 8 símbolos (8PSK), ES 2 340 552 T3 modulación por desplazamiento de amplitud y fase de 16 símbolos (16APSK), modulación por desplazamiento de amplitud y fase de 32 símbolos (32APSK) y modulación de amplitud en cuadratura (QAM) de orden alto.
- 8Un método según la reivindicación 1, en el que el cuadro (400) es transmitido por un canal (103) de comunicación vía satélite.
- 9Un método según la reivindicación 1, en el que el segmento incluye información codificada según codificación de comprobación de paridad de baja densidad (LDPC).
- 10Un método según la reivindicación 9, en el que la señal recibida es transmitida en transmisión de modo continuo.
- 11Un método según la reivindicación 9, en el que los preámbulos y los bloques de piloto son modulados según esquemas de modulación diferentes.
- 12Un método según la reivindicación 1, comprendiendo además:obtener una señal de onda continua a partir de las señales recibidas correspondientes a los campos de recurso auxiliar;calcular una pluralidad de valores de autocorrelación asociados con la señal de onda continua;acumular los valores de autocorrelación sobre una pluralidad de cuadros;y extraer la frecuencia de la señal de portadora basado en una suma ponderada de valores de fase no envueltos de los valores de autocorrelación acumulados.
- 13Un método según la reivindicación 12, en el que la señal de onda continua es obtenida a partir de las señales recibidas según:x k pk donde x k es la señal recibida correspondiente al campo de recurso auxiliar, p k es un modelo conocido relacionado con la señal en el campo de recurso auxiliar, y * es una operación conjugada compleja.
- 14Un método según la reivindicación 12, en el que los valores de autocorrelación están basados en los campos de recurso auxiliar sobre una pluralidad N de cuadros y son obtenidos, por cuadro, según /1-1 donde f es un índice de cuadro, s es un índice de campo de recurso auxiliar, N p es el número de campos de recurso auxiliar en un cuadro, k es el índice de símbolo x s , k es la señal recibida, p s , k es un símbolo de instrucción conocido, en el que los valores de autocorrelación calculados son acumulados sobre la pluralidad de cuadros según Λ»-Ι A-ο
- 15Un método según la reivindicación 14, en el que la frecuencia es extraída según:ES 2 340 552 T3 donde T s es el período de símbolo, y Δ(?η) mod(urg(7?(»i i J))-arg(jR(w)), 2zr],
- 16Un método según la reivindicación 12, comprendiendo además el método:estimar el valor de fase de portadora de cada uno de los campos de recurso auxiliar dentro del cuadro;y calcular la frecuencia de la señal de portadora basado en una suma ponderada de los valores estimados no envueltos de fase de portadora.
- 17Un método según la reivindicación 16, en el que el valor estimado de fase de portadora del campo de recurso auxiliar está basado en:donde x k es un símbolo recibido asociado con el campo de recurso auxiliar, p k es un modelo conocido en el campo de recurso auxiliar, Nu es la longitud del campo de recurso auxiliar.
- 18Un método según la reivindicación 17, en el que la frecuencia es calculada una vez por cuadro como sigue:donde M es el número de campos de recurso auxiliar en un cuadro.
- 19Un método según la reivindicación 1, comprendiendo además:obtener una estimación grosera de frecuencia basado en los campos de recurso auxiliar sobre uno o más cuadros;aplicar la estimación grosera de frecuencia a un mezclador (705) de entrada para corregir la desviación de frecuencia de las señales recibidas;y rastrear una frecuencia residual usando una estimación de frecuencia obtenida a partir de los campos de recurso auxiliar, una vez por cuadro.
- 20Un método según la reivindicación 1, en el que los valores estimados de fase de portadora de los campos de recurso auxiliar están basados en ES 2 340 552 T3 donde x k es un símbolo recibido asociado con el campo de recurso auxiliar, p k es un modelo conocido en el campo de recurso auxiliar, N u es la longitud del campo de recurso auxiliar, siendo la estimación de frecuencia instantánea determinada según ¿ donde y φ η ., y φ η son las estimaciones de fase a partir de los campos de recurso similar al principio y al final, respectivamente, del segmento correspondiente, y N s es la longitud del segmento dentro del cuadro, en el que φ η+1 pasa primero por una operación de desenvolver fase antes de la estimación de frecuencia instantánea, que es dada por donde suelo (x) redondea x al número entero más próximo hacia menos infinito.
- 21Un método según la reivindicación 20, en el que las estimaciones finales de fase, 3(m), son calculadas según:8(ηϊ)= 9 / (m)+0 r (m) + 2n:xsuelo^ , Ó m ^ ^~——^/2+ώιη,ιη = 0^.. Ν { -1, donde 3 f (m) y 3 r (m) son, respectivamente, las estimaciones de fase de barrido directo y las estimaciones de fase de barrido inverso.
- 22Un método según la reivindicación1, comprendiendo además:después de conseguir la sincronización de portadora, desmodular la señal recibida según una de la modulación por desplazamiento de fase binaria (BPSK), modulación por desplazamiento de fase en cuadratura (QPSK), modulación por desplazamiento de fase de 8 símbolos (8PSK), modulación por desplazamiento de amplitud y fase de 16 símbolos (16APSK), modulación por desplazamiento de amplitud y fase de 32 símbolos (32APSK) y una modulación de amplitud en cuadratura (QAM) de orden alto.
- 23Un método según la reivindicación 22, comprendiendo además:descodificar la señal desmodulada según un proceso de descodificación de comprobación de paridad de baja densidad (LDPC).
- 24Un soporte legible por ordenador que lleva instrucciones para proporcionar sincronización de portadora en un sistema de radiodifusión digital e interactivo, estando dispuestas dichas instrucciones, en la ejecución, para causar que uno o más procesadores realicen el método de la reivindicación 1.
Independent claims24
172 paragraphs in 9 sections, as filed
IS 2 340 552 T3
DESCRIPTION
Carrier synchronization using a sparse preamble and pilot blocks.
Field of the invention
The present invention relates to communication systems and, more particularly, to digital broadcasting systems.
Background of the invention
Broadcasting systems have included the demand for high-quality transmissions made possible by digital technology. The digital revolution has transformed the provision of broadband services, including audio and video programming as well as data transmission. Satellite communication systems have emerged as a viable solution to support such broadband services. As such, bandwidth and power efficient modulation and coding are highly desirable for satellite communication systems to provide reliable communication over noisy communication channels. In broadcast applications supported by such systems, streaming modems are widely used. Codes that perform well in low signal-to-noise environments disagree with these modems with respect to timing (eg, carrier phase and carrier frequency).
Conventional digital broadcasting systems require the use of additional instruction symbols beyond the normal auxiliary resource bits in a frame structure for their synchronization processes. The increase in auxiliary resource is particularly necessary when the signal-to-noise ratio is low; such an environment is typical when high performance codes are used in conjunction with high order modulation. Traditionally, continuous mode modems use a feedback control loop to acquire and track carrier frequency and phase. In this synchronization process, Forward Error Correction (FEC) encoded data fields, eg preambles of a block code, containing known data symbols, are simply ignored. Such conventional procedures that are purely based on feedback control loops are prone to strong thermal noise and radio frequency (RF) phase noise, causing high cycle slip rates and an error floor in overall receiver performance. Thus, these procedures are loaded by increased auxiliary resource in terms of instruction symbols for a certain functional performance objective, in addition to limited acquisition margin and long acquisition time. Furthermore, these conventional timing techniques are dependent on the particular modulation scheme, thereby hindering flexibility in the use of modulation schemes.
Document EP1059786A discloses a receiver that provides carrier synchronization by estimating the phase values of a carrier signal using auxiliary resource fields.
There is a need for a digital communication system that provides a synchronization procedure that is simple to implement and incurs as few instruction symbols as possible. There is also a need to provide a synchronization technique that is flexible in order to provide modulation independence.
Summary of the invention
These and other needs are addressed by the present invention, in which a method for providing carrier synchronization in an interactive digital broadcasting system uses Low Density Parity Check (LDPC) codes and modulation schemes. of higher order. Unlike conventional continuous modems, the carrier synchronization method estimates carrier frequency and phase on a segment-by-segment basis and continuously tracks the carrier frequency between segments. The preamble of a forward error correction (FEC) table and pilot blocks (ie, added pilot symbols), which aid carrier synchronization, serve as segment boundaries. In an exemplary embodiment, a pilot symbol insertion process splits the forward error correction (FEC) code word into multiple code segments and inserts a pilot block in the form of a single word (UW: unique word). before each code segment of the physical layer table. The preamble and pilot blocks serve as an instruction block. The carrier synchronization process uses the instruction block to estimate the carrier frequency and phase and reinitializes the phase tracking loop for each new segment. The frequency acquisition process involves computing an autocorrelation of a continuous wave signal (CW) with data removed. The carrier frequency of the received signal is estimated based on a weighted sum of the non-enveloped phase of the accumulated autocorrelation values. Regarding frequency tracking, a feedforward structure is implemented to generate estimates and update the carrier frequency once per Low Density Parity Check (LDPC) frame based on the phase estimates from the instruction block (or that is, preamble and single word). For phase tracking, a two-scan Phase Locked Loop (PLL) architecture with a maximum probability (ML) phase detector is used. Two-scan phase locked loop (PLL) tracks carrier phase on a segment-by-segment basis to estimate carrier phase based on both past and future samples by sweeping the data segment in both forward and reverse directions. A segment is a segment of code. The above provision
ES 2 340 552 T3 advantageously reduces the need to introduce additional auxiliary resource for carrier synchronization, dramatically reduces cycle slip rate and limits its error propagation impact, and works well in low signal-to-noise ratio environments, providing good immunity against thermal noise and phase noise. Additionally, the frequency estimation process provides a large margin of frequency acquisition and short acquisition time.
According to one aspect of an embodiment of the present invention, a method for providing carrier synchronization in an interactive digital broadcasting system is disclosed. The method includes receiving a frame transmitted according to a carrier signal, wherein the frame includes a plurality of segments separated by a plurality of auxiliary resource fields and the auxiliary resource fields include a preamble and pilot blocks corresponding to the respective segments. . The method also includes generating estimated phase values associated with the carrier signal based on the auxiliary resource fields, wherein for each of the segments, the estimated carrier phase values of the auxiliary resource fields correspond to an initial and an end of the segment. The method also includes estimating the phase of the carrier signal associated with a random data field within the segment, based on the estimated phase values and random data. The method further includes estimating the phase of the carrier signal associated with a random data field within the segment, based on the estimated phase values and random data; and estimating the frequency of the carrier signal based on the auxiliary resource fields. The step of estimating the phase is performed in the chart on a segment-by-segment basis. Also, the method includes estimating a value of an instantaneous carrier frequency from the estimated carrier phase values based on the auxiliary resource fields. For each of the segments, the method also includes performing a direct phase sweep over the segment's random data field using a phase lock loop initialized with the estimated carrier phase value from the auxiliary resource field at the beginning of the segment. segment. In addition, for each of the segments, the method includes performing a reverse sweep over the segment's random data field using a phase-locked loop initialized with the estimated carrier phase value from the auxiliary resource field at the end of the segment. and the estimated instantaneous value of the carrier frequency, where the instantaneous carrier frequency is eliminated before the forward sweep and the reverse sweep. In addition, the method includes determining whether the forward sweep or the reverse sweep is in sync, and calculating the final carrier phase estimates over the random data field by combining the carrier frequency estimated instantaneous value, the forward sweep phase estimates. , and the inverse sweep phase estimates.
Brief description of the drawings
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to like elements, and in which:
Figure 1 is a diagram of a digital broadcast system configured to use low density parity check (LDPC) codes, in accordance with one embodiment of the present invention;
Figure 2 is a schematic of an exemplary transmitter employed in the digital transmission equipment of the system of Figure 1;
Figure 3 is a schematic of an exemplary digital modem in the system of Figure 1;
Figures 4A and 4B are, respectively, a diagram of an exemplary frame structure used in the system of Figure 1, and a flow chart of a process for inserting pilot blocks into the frame structure, in accordance with one embodiment of the present invention;
Figures 5A and 5B are flow charts of a frequency acquisition process in accordance with one embodiment of the present invention;
Figure 6 is a flow chart of a frequency tracking process according to one embodiment of the present invention;
Figure 7 is a schematic of a carrier sync module operating with additional pilot blocks for low signal-to-noise ratio 8-symbol phase shift keying (8PSK), in accordance with one embodiment of the present invention;
Figure 8 is a diagram of a two-scan phase locked loop (PLL) process operating in the frame structure of Figure 4A, in accordance with one embodiment of the present invention;
Figure 9 is a schematic of a phase-locked loop (PLL) used in a two-scan phase-locked loop (PLL), in accordance with one embodiment of the present invention;
Figure 10 is a flow chart of a two scan phase locked loop (PLL) process in accordance with one embodiment of the present invention;
Figure 11 is a schematic of a loop filter used in the two-scan phase locked loop (PLL) process of Figure 10;
Figure 12 is a schematic of a carrier synchronization module operating without additional pilot blocks for Quadrature Phase Shift Keying (QPSK), according to related apparatus;
Figure 13 is a flow chart of a fine tuning thread of the frequency acquisition process used in the carrier synchronization module of Figure 12;
Figure 14 is a flow chart of a frequency tracking process used in the carrier synchronization module of Figure 12;
FIG. 15 is a flow chart of the phase combining stage of the two-scan phase locked loop (PLL) process of FIG. 10; and Figure 16 is a schematic of a computer system that can perform the various processes associated with carrier synchronization, in accordance with embodiments of the present invention.
Description of the preferred embodiment
An apparatus, method and software are described for efficiently providing carrier synchronization in an interactive digital broadcasting system. In the following description, for purposes of explanation, numerous specific details are set forth to provide a complete understanding of the present invention. However, it is apparent to one skilled in the art that the present invention can be practiced without these specific details or with an equivalent arrangement. In other cases, well known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the present invention.
Figure 1 is a diagram of a digital broadcast system configured to use low density parity check codes (LDPC), in accordance with one embodiment of the present invention. The digital communication system 100 includes digital transmission equipment 101 that generates signal waveforms for broadcasting, through a communication channel 103, to one or more digital modems 105. According to one embodiment of the present invention, the communication system 100 is a satellite communication system that supports, for example, audio and video broadcasting services as well as interactive services. Interactive services include, for example, electronic programming guides (EPGs), high-speed Internet access, interactive advertising, telephony, and electronic mail (e-mail) services. These interactive services may also encompass such television services as pay-per-view services, commerce-on-television, video on demand, near video on demand and audio on demand. In this environment, modems 105 are satellite modems.
These modems 105 achieve carrier synchronization by examining preambles and unique words (UW: unique words) that are embedded in broadcast data frame structures (shown in Figure 4), thereby reducing auxiliary resource usage ( overhead) specifically designated for instructional purposes. The digital modems 105 are more fully described below with respect to Figure 3.
In this discrete communication system 100, the transmission equipment 101 produces a discrete set of possible messages representing media content (eg, audio, video, textual information, data, etc.); each of the possible messages has a corresponding signal waveform. These signal waveforms are attenuated, or otherwise altered, by communication channel 103. To combat noise from channel 103, transmitting equipment 101 uses low density parity check (LDPC) codes.
The Low Density Parity Check (LDPC) codes that are generated by the transmission equipment 101 allow high speed implementation without incurring any loss of functional performance. These structured LDPC codes extracted from the transmitting equipment 101 avoid assigning a small number of check nodes to the bit nodes already vulnerable to channel errors by virtue of the modulation scheme (e.g. 8 PSK: 8 phase shift keying = 8 symbol phase shift keying). Such LDPC codes have a decoding process available in parallel (unlike turbo codes), which advantageously involves simple operations such as adding, comparing and table querying. Also, carefully designed LDPC codes do not exhibit any sign of error soil.
According to one embodiment of the present invention, the transmission equipment 101 generates, using a relatively simple coding technique as explained below in Figure 2, LDPC codes based on parity check matrices (which facilitate efficient memory access during decoding) to communicate with the satellite modem 105.
Figure 2 is a schematic of an exemplary transmitter employed in the digital transmission equipment of the system of Figure 1. A transmitter 200 is equipped with an LDPC encoder 203 that accepts input from an information source 201 and produces higher coded streams. adequate redundancy for error correction processing at receiver 105. Information source 201 generates k signals from discrete alphabet X. LDPC codes are specified with parity check matrices. On the other hand, LCPC encoding codes generally need to specify the generator matrices. Although it is possible to obtain generator matrices from parity check matrices using Gaussian elimination, the resulting matrix is no longer sparse and to store a large generator matrix to be complex.
IS 2 340 552 T3
Encoder 203 outputs alphabet Y signals to modulator 205 using a simple coding technique that uses only the parity check matrix by imposing structure on the parity check matrix. Specifically, a constraint is imposed on the parity check matrix by forcing a certain portion of the matrix to be triangular. Such a restriction produces a negligible loss of functional performance and therefore constitutes an attractive compromise.
Modulator 205 transforms the encoded messages from encoder 203 into signal waveforms that are transmitted to a transmitting antenna 207 that broadcasts these waveforms on communication channel 103. Consequently, the coded messages are modulated and distributed to a transmitting antenna 207. Transmissions from transmit antenna 207 are propagated to a digital modem as discussed below. In the case of a satellite communication system, the signals transmitted from antenna 207 are relayed via a satellite.
Figure 3 is a schematic of an exemplary digital modem in the system of Figure 1. Digital modem 300, as a modulator / demodulator, supports both transmission and reception of signals from transmitter 200. According to one embodiment of the present invention, the modem 30 has an input module 301 that provides filtering and symbol timing synchronization of the LDPC-encoded signals received from the antenna 303, a carrier synchronization module 302 that provides frequency acquisition and phase and tracing of the signals drawn from the input module 301. An inverse transformer 305 performs the inverse transformation of the received signals extracted from the carrier synchronization module 302. After demodulation, the signals are sent to an LDPC decoder 307 which attempts to reconstruct the original source messages by generating X 'messages.
On the transmit side, the modem 300 uses an LDPC encoder 309 to encode the input signals. The encoded signals are then modulated by a 311 modulator that can employ various modulation schemes (for example, binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), 8 phase shift keying). symbols (8PSK), 16 symbol amplitude and phase shift keying (16 ApSK) or other higher order modulation).
Figure 4A shows a diagram of an exemplary frame structure in accordance with one embodiment of the present invention. By way of example, an LDPC encoded frame 400 is shown that can support, for example, satellite broadcasting and interactive services. In this scenario, the frame structure splits a 400 frame of LDPC (for example, for 8 symbol phase shift keying (8PSK)) into 15 401 code segments (for example, 16 slots each, and each slot occupies 90 symbols) and inserts 14 unique words (UWs) 403 between two segments 401. The process of inserting the unique words (UWs) is explained below with respect to Figure 4B. In an exemplary embodiment, each unique word (UW) 403 has 36 symbols (PSK). A preamble 405 serves as a physical layer header (designated "PLHEADER") and occupies one slot. In this frame structure, preamble 405 and unique word (UW) 403 serve as instruction blocks; unique words (UWs) 403 are inserted as pilot blocks. Although frame 400 is described with respect to a structure that supports satellite broadcasting and interactive services (and conforms to the Digital Video Broadcast (DVB) S2 standard), it is recognized that the carrier synchronization techniques of the present invention can be applied to other frame structures.
Figure 4B shows a flow chart of a process for inserting a pilot block into the frame structure of Figure 4A. This carrier phase tracking training pilot structure can be implemented in an interactive digital broadcasting system to combat strong phase noise. At step 411, the pilot insertion process waits for a predetermined number of symbols (ie, insertion point). Next, it is determined whether the pilot position matches the preamble position, as in step 413. If the position is designated for the preamble, then the pilot block is not inserted (step 415), otherwise the pilot block is inserted, by step 417.
For example, in the frame structure of Figure 4A, the pilot insertion process inserts pilot blocks every 1,440 symbols. In this scenario, the pilot block includes 36 pilot symbols. For example, in physical layer frame 400, the first pilot block is thus inserted 1,440 symbols after the physical layer header (PLHEADER), the second pilot block is inserted after 2,880 symbols, etc. If the pilot block position matches the beginning of the next physical layer header (PLHEADER), then the pilot block is not inserted.
In accordance with one embodiment of the present invention, the carrier synchronization module 302 (Figure 3) uses the preamble 405 and unique words (UWs) 403 for carrier phase and frequency synchronization. As previously mentioned, conventionally, forward error correction encoded data, containing known data symbols (eg (FEC), preamble 405), is ignored in streaming modems. That is, preamble 405 and / or unique words (UWs) 403 are used for carrier synchronization, that is, to assist with frequency acquisition and tracking operation, and phase tracking loop. As such, preamble 405 and unique words (UWs) 403 are considered "command" or "pilot" symbols and constitute, individually or collectively, an instruction block.
IS 2 340 552 T3
The carrier frequency synchronization process, which is more fully described later in Figures 5 and 6, adopts a feedforward frequency estimator for both frequency acquisition and tracking. In an exemplary embodiment, the estimator works only in the instruction block, therefore it is independent of the modulation scheme.
Figures 5A and 5B are flow charts of a frequency acquisition process in accordance with one embodiment of the present invention. In this example, a frequency acquisition process is executed by the carrier synchronization module 302, whereby different modulation schemes may be employed (eg, BPSK, QPSK, 8PSK, 16APSK, etc.). The frequency acquisition process basically includes two steps. First, the autocorrelation of the continuous wave (CW) with removed data is determined by step 501. Next, the carrier frequency is estimated, as in step 503, based on a phase weighted sum of the autocorrelation.
The autocorrelation calculation, as in step 501, is more fully described in Figure 5B. In step 511, the data modulation is removed based on known training models to obtain the continuous wave (CW) signal. Next, the autocorrelation is calculated within a low density parity check box (LDPC), by step 513, as follows:
nl (») = ΣΣ <<sup>χ</sup>μ «Ρμ«. * Χ<sup>χ</sup>μΛλ *> * <sup>m</sup> = *· ·.<sup>L</sup> where f is the frame index, s is the single word index (UW), k is the symbol index, P<sub>s</sub> is the known symbol and the frame format of LDPC and 8PSK is assumed.
In step 515, the autocorrelation is accumulated based on various LDPC frames, as follows:
/ = or
The final frequency estimate is based on the following formula:
<img file="ES2340552T3_D0001.tif" />
where T<sub>s</sub> is the symbol period, and
Á (m) = arg [/? (L)], m = 0 mod [arg (K (m + l)) - arg (K (/ n)), 2π], m =
The above frequency acquisition process exhibits excellent functional performance. Only a small autocorrelation number (L) calculated over a few frames (N) of LDPC can achieve good performance, for example, when L = 16, N = 5, Es / No (symbol energy / power spectral density of noise) = 6.7 dB, the root mean square frequency error is 8.9x10<sup>5</sup>. The acquisition time is independent of the carrier frequency deviation and is only determined by the desired estimation accuracy. For example, if the desired residual frequency is 3x10<sup>-4</sup>, only five frames of LDPC are required to acquire the frequency deviation with a 99.999% success rate. Also, the frequency estimation process has a large frequency acquisition margin (greater than the symbol percentage of 20%), a very small estimation variance, and
ES 2 340 552 T3 works well with low signal-to-noise ratio (even at 0 dB). The procedure is also resistant to thermal noise and phase noise. Furthermore, the above method advantageously provides ease of implementation as digital logic, for example on a very large scale integration chip (VLSI).
After the carrier frequency acquisition step is performed, the frequency tracking process is started, as discussed below.
Figure 6 is a flow chart of a frequency tracking process according to one embodiment of the present invention. As noted earlier, the frequency tracking process has a feed-forward structure. By way of example, the operation of frequency tracking is explained with respect to scenarios that require additional pilot blocks, for example, 8PSK modulation with low signal-to-noise ratio. In step 601, the phase is estimated from the preamble and unique words (UWs) using the following formula:
<img file="ES2340552T3_D0002.tif" />
where x<sub>k</sub> is the received symbol, P<sub>k</sub> is the known single word (UW) model, N<sub>or</sub> is the length of the UW.
In step 603, the frequency is estimated as follows:
<img file="ES2340552T3_D0003.tif" />
where<sub>s</sub> is the length of code segments, that is 16 slots, 1,440 symbols, N<sub>or</sub> is the length of the unique word (UW) and is equal to 36, and M is the number of unique words (UW's) in an LPDC frame, for example 14 for 8PSK modulation.
In accordance with one embodiment of the present invention, the frequency tracking process estimates and updates the carrier frequency once per LDPC frame based on the phase estimates from the preamble and the single word (UW).
The above frequency tracking scheme provides a number of advantages. As the process is direct feed, stability is not a concern. Also, the process can accommodate a large frequency ramp (eg, 30 kHz) because the carrier frequency is estimated once per LDPC frame. Additionally, the process is resistant to thermal noise and phase noise. For example, the mean square frequency error has been determined to be 6.5x10<sup>-7</sup> with Additive White Gaussian Noise (AWGN) only, and 6.2x10<sup>-6</sup> with Additive White Gaussian Noise (AGWN) plus 6.7dB phase noise. At 0dB, the root mean square error is 1.3x10<sup>6</sup> (AWGN only) and 6.3x10 <sup>6</sup> (AWGN plus phase noise), that is, phase noise is the dominant source of estimation error.
Figure 7 shows a carrier synchronization module operating in the tracking mode with pilot blocks assisting in carrier synchronization for low signal-to-noise ratio 8PSK modulation, according to an embodiment of the present invention. A received signal is received and sent to a matched filter 701. A feedforward frequency estimator 703 obtains a new frequency estimate once per frame from LDPC and feeds the estimate to a loop filter 712 and then to a wideband mixer 705 to correct for frequency deviation. The matched filter 701 extracts the single word (UW) to a single word (UW) phase estimator 707 and the random data extracted from the received signal to a block carrier phase estimator 709, which generates phase estimates of a code segment for a mixer 713 based on the random data and phase estimates associated with the unique words (UW's). The single word (UW) phase estimator 707 extracts the single word (UW) phase estimates to the feedforward carrier frequency estimator 703, by input from machine 711 with finite state number (FSM: Finite State Machine) of frame synchronization that determines where the unique words (UW's) are located. Matched filter 701 also provides the received signal to mixer 713 which, in turn, extracts the resulting signal to inverse transformer 305.
The block carrier phase estimator 709 employs a carrier phase tracking process (in the exemplary 8PSK modulation scenario) that is based on a two-scan phase locked loop (PLL) architecture with a phase detector of maximum likelihood (ML) suitable for use with low signal-to-noise ratio. Unlike the conventional phase-locked loop, the two-scan phase-locked loop has a number of distinctions. The two-scan phase-locked loop (PLL) tracks carrier phase on a segment-by-segment basis.
IS 2 340 552 T3
Phase trace operations between two segments are independent. The two-sweep phase-locked loop uses the phase estimates from the single word (UW) at the beginning and end of the segment to initialize the phase and frequency components in the loop in the phase-locked loop (PLL) and also as a phase reference to determine if a cycle slip has occurred. Cycle slips in a phase locked loop (PLL) system are mainly caused by instantaneous frequency that is outside the loop tracking range.
Since a traditional phase locked loop is a causal system, such a system estimates the carrier phase based on past samples. In contrast, the two-scan phase-locked loop, according to one embodiment of the present invention, estimates the carrier phase based on both past and future samples by sweeping the data segment in both forward and reverse directions, as illustrated in Fig. Figure 8.
Figure 8 shows a diagram of a two scan phase locked loop (PLL) process operating in a frame structure, in accordance with one embodiment of the present invention. To suppress cycle slippage, the two-sweep phase-locked loop estimates the instantaneous frequency within the segment before the phase sweep, and intelligently combines the phase estimates from both forward and reverse directions as the final phase estimate.
Figure 9 shows a schematic of a phase-locked loop (PLL) used in the two-scan phase-locked loop, which performs phase sweep in one direction, according to an embodiment of the present invention. The two-scan phase-locked loop may utilize two such phase-locked (PLL) loops 900 in parallel operation or, alternatively, a single phase-locked loop 900 (PLL) operating sequentially in a series implementation. An input mixer 901 corrects the phase deviation of the input signal with the phase estimate from the tracking loop. A maximum likelihood (ML) phase detector 903 estimates the residual phase error of the rotated signal, and then passes it through a loop filter 905 (which is more fully described in Figure 11). The loop filter 905 removes noise and tracks the frequency of the signal, and then closes the phase-locked loop by sending the phase estimate to a numerically controlled oscillator (NCO) 907 that projects the phase estimate to the axes. in phase and in quadrature.
The maximum probability (ML) phase detector 903, used in the two-scan phase locked loop, is derived from the maximum probability (ML) rule and is suitable for low signal-to-noise ratio. Phase detector estimates phase 3<sub>k</sub> in each received symbol x<sub>k</sub> as follows:
<img file="ES2340552T3_D0004.tif" />
where d<sub>k</sub> is the flexible estimate of the transmitted data symbol d<sub>k</sub>, I mean,
Mt lfr »-<sup>c</sup>-ll<sup>2</sup>
Σ- '_ _____
Ml
Σ<sup>β 201</sup>
M: the modulation dimension, eg 4 for QPSK, 8 for 8PSK; <sub>c</sub> _ constellation point; σ<sup>2</sup>: variance of additive white Gaussian noise (AWGN); and the character * is the complex conjugate operation.
The signal-to-noise ratio (SNR) of the phase detector can be defined as:
<img file="ES2340552T3_D0005.tif" />
where A is the gain of the phase detector, is the estimation variance. The signal-to-noise ratio of the maximum probability (ML) phase detector for 8PSK modulation is -4.5 dB in 6.6 dB, which is 3.5 dB better than the traditional decision-driven phase detector.
IS 2 340 552 T3
Figure 10 shows a flow chart of a two scan phase locked loop (PLL) process according to one embodiment of the present invention. Two-scan phase locked loop (PLL) operation within a code segment can be divided into three stages: (1) initialization, (2) two scans, and (3) phase combining. During initialization, the phase estimates are obtained from the pilot blocks, i.e. preamble and single word (UW), at the beginning and end of the current code segment using the following formula:
<img file="ES2340552T3_D0006.tif" />
where x<sub>k</sub> is the received symbol, p<sub>k</sub> is the known pilot model, N<sub>or</sub> is the length of the pilot blocks (36 for unique words (UWs), 90 for the preamble).
The instantaneous frequency within a code segment is estimated based on the unwrapped phase estimates from the unique words (UWs) and allows for cycle slip suppression. This estimate, as in step 1001, is determined as follows:
~^<sup>n</sup> , where </> „., and φ<sub>η</sub> are the phase estimates from the unique words (UWs) at the beginning and end, respectively, and N<sub>s</sub> is the length of the code segment, for example 1,440.
The unwrapping phase operation is given by:
+ 2# <sup>x</sup> sue / o ^ -.
Where ground (x) rounds (x) to the nearest whole number towards minus infinity
The two-sweep phase begins with step 1003, in which the instantaneous frequency deviation <5 is removed before the phase-locked loop sweep by multiplying the received symbol x<sub>k</sub> by exp (-jmk), that is,
<img file="ES2340552T3_D0007.tif" />
which produces a new xk. In an exemplary embodiment, the register in numerically controlled oscillator (NCO) 907 is programmed with ω.
Figure 11 shows a schematic of a loop filter used in the two-scan phase locked loop (PLL) process of Figure 10. As shown in Figure 11, a loop filter 1100 can be used, by means of which which loop frequency register 5 (k) is initialized with 0 in the forward sweep phase locked loop (PLL) (step 1005), in the reverse swept phase locked loop (PLL), register 5 (k ) 1101 loop frequency is also initialized with 0. The phase register f (k) 1103 is initialized with the estimate φ<sub>η</sub> phase from the single word (UW) at the beginning in the direct sweep phase locked loop. The entire code segment is swept, as in step 1007, from the beginning to the end, obtaining the estimate 3<sub>{</sub>(m) of phase, m = 0, ..., N<sub>s</sub>-1 (step 1009).
The phase register f (k) 1103 is initialized with the phase estimate - mx'CAg - 1) from the single word (UW) at the end of the reverse swept phase locked loop. Afterwards, the entire code segment is swept from the end to the beginning, obtaining the estimate 3<sub>r</sub>(m) of phase, m = 0, ..., N<sub>s</sub>-1.
According to one embodiment of the present invention, the forward to reverse scans are performed simultaneously, thereby increasing speed. In other words, one or more phase-locked loops can be used. In the case of a single phase-locked loop, the forward and reverse sweeps are performed sequentially.
IS 2 340 552 T3
The final phase estimate (as seen in Figure 10) is the combination of the phase estimates from both the forward and reverse phase locked loop sweeps and the instantaneous frequency estimate (by step 1011).
Cycle slip impact can be further reduced by the following alternative process. Before combining the phase, the process tests for any substantial phase errors at the end of both scans as follows. A phase error is defined, £ f - Sy (¾ - 1) + ¢ 3 (¾ - 1) - at the end of the direct sweep, in which the unwrapping technique below can be used in e<sub>F</sub>.
<img file="ES2340552T3_D0008.tif" />
Likewise, the phase error is defined at the end of the reverse sweep, in which the same unwrapping technique is used in e<sub>s</sub>.
I | _. __ ñT
Yes | <<sub>0</sub> k<sub>s</sub>| <t<sub>s</sub> , where T<sub>s</sub> is a predetermined threshold, for example t<sub>and</sub> ~ (π / 8 for 8PSK), then the sweep is indicated "in sync", and the final estimate of phase 3 (m) is given by
<img file="ES2340552T3_D0009.tif" />
If M> y 1 ^ 1> t<sub>s</sub>, it is very likely that there is a substantial frequency change within the segment, the following steps are performed to handle such a special case. First M<sub>c</sub> is estimated (where such a substantial frequency change occurs) as follows:
k, IW-D k, l + kl phase locked loop (PLL) is initialized from mc with
Then the direct sweep of
<img file="ES2340552T3_D0010.tif" />
and a direct phase-locked loop sweep is performed from m<sub>c</sub> to N<sub>s</sub> - 1, thereby obtaining a new 3<sub>F</sub> (m) for that portion. Phase Locked Loop (PLL) reverse sweep is also initialized from mc with
<img file="ES2340552T3_D0011.tif" />
in which a direct phase-locked loop sweep is performed from m<sub>c</sub> to 0. A new 3<sub>r</sub> (m) is obtained for that portion.
The final estimate of phase 3 (m) is given by
<img file="ES2340552T3_D0012.tif" />
In the above two-scan phase locked loop (PLL) arrangement, the phase estimation is based on both past and future samples. The phase estimates from both forward and reverse sweeps are correlated, however noise caused during the processes is not. Therefore, the process can reduce the phase error variance by half (that is, 3 dB).
This process also produces good phase tracking results. The RMS phase error for 8PSK modulation with DVB-S phase noise mask is 3.2 degrees (at 6.6 dB) compared to the 4.5 degrees RMS phase error obtained by the phase locked loop. traditional direct sweep. Segment-by-segment phase tracking, instantaneous frequency estimation and elimination, and two-sweep phase estimation plus intelligent phase matching efficiently prevent cycle slippage from occurring.
Also, the loop can start phase tracking immediately after the entire code segment is received (16 slots). Also, the phase-locked loop requires only a small storage capacity.
ES 2 340 552 T3 for buffering, according to an exemplary embodiment, sample I and Q (in phase and quadrature) of 16 slots and 1,440 phase samples (half of each assigned to a sweep). The phase locked loop (PLL) is resistant to residual frequency error (up to 3x10<sup>-4</sup>) due to the instantaneous frequency estimate. For high order modulation phase tracking, such as 8PSK, the large frequency deviation is very detrimental.
Figure 12 is a schematic of a carrier synchronization module operating without additional pilot blocks to assist carrier synchronization for Quadrature Phase Shift Keying (QPSK), according to related apparatus. The carrier synchronization process for pilotless mode is similar to that used in pilot mode, as explained with respect to Figure 7. The carrier sync module 302 operates using only the preamble of a slot for instruction; that is, unique words (UWs) are not used. Frequency acquisition in pilotless mode is a two-step process that includes coarse frequency estimation by a feed-forward frequency estimator and then fine frequency estimation by a two-sweep phase-locked loop operating in acquisition mode. .
Carrier sync module 302 provides phase recovery in two-scan phase-locked loop (PLL) -based tracking mode. A preamble phase estimator 1201 receives the preamble that is extracted from a matched filter 1203. The preamble phase estimator 1201 extracts the preamble phase estimate based on the frame synchronization finite state machine (FSM) 1205 that decides where a new preamble is located and supplies it to a loop 1207 Two-scan phase locked (PLL) (similar to that used in pilot mode). The two-sweep phase-locked loop (PLL) 1207 also receives as input the random data extracted from the received signal. The phase estimate generated by the two-sweep PLL 1207 is fed to a frequency estimator 1209; finally, the phase estimate generated by the two-sweep PLL 1207 is supplied to the mixer 1206 which rotates the signal from the matched filter 1203 based on the phase estimate to the inverse transformer 305. The frequency estimator 1209 extracts the frequency estimate to a loop filter 1211 (for example, as shown in Figure 11) that tracks the frequency deviation and supplies the resulting signal to a numerically controlled oscillator 1213 (NCO: numerically controlled oscillator). The numerically controlled oscillator (NCO) 1213 rotates the received signal according to the frequency estimate from the loop filter 1211 to a wideband mixer 1215.
The carrier sync pattern 302 advantageously provides high performance with very low signal-to-noise ratio (eg, 1dB), while minimizing the use of command symbols. The carrier synchronization module 302 supports fast carrier phase and frequency acquisition (eg, less than 50 ms).
In a related method, the carrier frequency acquisition process involves two stages: a coarse frequency estimation process and a fine tuning process. The crude frequency estimation process resembles that used in 8PSK (Figure 5). The difference in pilotless mode is that only the 90 symbol preamble is used in the autocorrelation calculation. The autocorrelation is calculated within a low density parity check box (LDPC):
<sup>R</sup>f (ί ») = PÍ *) * '>” = C ·. » L where f is the frame index, k is the symbol index, p<sub>s</sub> is the known data symbol in the preamble, n equals 90. The autocorrelation is then accumulated based on various LDPC frames to determine the final frequency estimate.
Figure 13 is a flow chart of a fine tuning thread of a frequency acquisition process used in the carrier synchronization module of Figure 12. After the coarse frequency estimation ends, the frequency acquisition process performed by the carrier sync module 302 may enter the fine tune stage. The fine tuning process is based on a frequency tracking loop whose frequency error estimate is performed once per LDPC frame and based on the phase scan result of the two-scan phase-locked loop (PLL) 1207 that it works in an acquisition mode and the phase estimates coming from the preambles. In such mode, the phase locked loop (PLL) has a greater loop bandwidth (for example, 2x10<sup>-3</sup>) and a lower damping factor (for example, 1.1).
The fine-tuning process is based on the two-scan phase-locked loop (PLL) 1207 (Figure 12). The process estimates the frequency error once per LDPC frame and updates the numerically controlled oscillator (NCO) 1213 connected to the broadband mixer 1215. First, () (m), m = 0, ..., N<sub>s</sub> -1 (N<sub>1</sub>s is the LDPC frame length, eg 32,400 for QPSK) is defined as the phase scan result for an LDPC frame.
IS 2 340 552 T3
The beginning of a fine-tuning process initializes a frame counter, Nf to 0, by step 1301. In this example, the process iterates 8 times (that is, Nf = 8). At step 1303, a new LDPC frame is processed with the phase locked loop (PLL), which is initialized with the phase estimates based on the preambles; the operation of the two-scan phase locked loop (PLL) is explained in more detail later. Next, it is determined whether the forward scan or the reverse scan is in sync (step 1305). If the forward sweep or the reverse sweep (or both) is in sync, the frequency error estimate, by step 1307, is given by
A Λ <sup>J</sup>'2ríT, N,' where 3 (m) is the final phase estimate generated by the two-sweep phase locked loop 1207 (PLL), and then the frequency in the numerically controlled oscillator (NCO) is updated by
<img file="ES2340552T3_D0013.tif" />
where ρ is the 1211 loop filter parameter, for example 0.5.
If no sweep is in sync, the LDPC frame is skipped in the fine tune operation, by step 1309. If a certain number of frequency fine tunes have occurred (as implemented by steps 1311 and 1313), the loop enters in the tracking stage, by step 1315, as explained in Figure 14.
Figure 14 is a flow chart of a frequency tracking process used in the carrier synchronization module of Figure 12. The carrier frequency tracking process is similar to fine tuning in the frequency acquisition stage. The tracking process estimates the frequency error once per LDPC frame based on the phase tracking result from the two-scan phase locked loop (PLL) 1107 and updates the numerically controlled oscillator (NCO) 1213 accordingly; the process does this only when the PLL 1107 is in sync. The only difference between the fine-tuning process and this frequency tracking process is that the two-scan PLL is operated with a much smaller loop bandwidth (for example, 5x10<sup>-4</sup>) and higher damping factor (for example, 2).
At the end of an LDPC frame, the tracking process determines whether the forward scan or the reverse scan is in sync, by steps 1401 and 1403. If the scans are in sync, the frequency error estimate is calculated, by the step 1405, as follows:
AA ¿9 (N, -1) -9 (0) <sup>!and</sup> 2rtT, N, 'and the frequency in the numerically controlled oscillator 1213 (NCO) is updated by fnccO<sup>1</sup> + 1) = fnctXX) + Pfs If the forward scan and the reverse scan are not in sync, the LDPC frame is skipped, by step 1407.
FIG. 15 is a flow chart of the phase combining step of the two scan phase locked loop (PLL) process according to a related method. In pilotless mode, the carrier phase tracking process is based on the two-scan PLL architecture with a maximum probability (ML) phase detector that is suitable for low signal-to-noise ratio. The process tracks the carrier phase on a frame-by-frame basis. According to a related method, the phase tracking operations between two LDPC frames are independent. The tracing process uses the phase estimates from the current frame preamble and next frame preamble to initialize the phase component in the phase locked loop (PLL). These phase estimates also provide a phase reference to determine if cycle slip has occurred. The new phase locked loop (PLL) estimates the carrier phase based on both past and future displays by sweeping the data segment in both forward and reverse directions. To suppress cycle slippage, the new PLL cleverly combines the phase estimates from both directions as the final phase estimate, as shown in Figure 14.
The maximum probability (ML) phase detector 911 (of Figure 9), used in the two-scan PLL, is derived from a maximum probability rule. Phase detector estimates phase 3<sub>k</sub> at each symbol x<sub>k</sub> received as follows:
TO <sup>Λ</sup>
9<sub>k</sub> = lm (x<sub>k</sub>d<sub>k</sub>*),
ES 2 340 552 T3 where d<sub>k</sub> is the flexible estimate of the symbol d<sub>k</sub> of data transmitted, that is,
<img file="ES2340552T3_D0014.tif" />
μ-i licit /
Σ * <sup>2nd</sup>'ffigQ
M-1 IR.-eC<sup>3</sup> ’
Σ<sup>β</sup> j / m) constellation point;
M: the modulation dimension, 4 for QPSK, 8 for 8PSK; _ \
C ττ> - C '' and σ<sup>2</sup>: variance of additive white Gaussian noise (AWGN); the character * is the complex conjugate operation.
The signal-to-noise ratio (SNR) of the phase detector is defined as follows:
<img file="ES2340552T3_D0015.tif" />
where A is the gain of the phase detector σ<sup>2</sup> is the estimation variance. The signal-to-noise ratio of the maximum probability (ML) phase detector in QPSK modulation is -4.1 dB in 1 dB, which is 1.5 dB better than the traditional decision-driven phase detector.
As with the pilot mode operation described with respect to Figure 10, operation of the two-scan PLL 1207 within an LDPC frame has three stages. During the initialization stage, the phase estimates are obtained from the preamble at the beginning and the end of the current frame:
<img file="ES2340552T3_D0016.tif" />
where x<sub>k</sub> is the received symbol, p<sub>k</sub> is the known preamble model, N<sub>or</sub> is the length of the preamble (for example, 90). Since the LDPC frame is relatively long (eg 32,400), it is difficult to estimate the instantaneous frequency based on the phase estimates from the preambles. However, the PLL for low order modulation like QPSK is more resistant to phase noise and frequency error than for high order modulation like 8PSK.
In the two-scan stage, the phase register £ (k) 1103 (Figure 10) is initialized with the estimate /<sub>n</sub>phase from the preamble at the beginning in the forward sweep PLL. Then the whole frame is swept from the beginning to the end, producing the estimate 3<sub>F</sub>(m) of phase, m = 0, ..., N<sub>s</sub> - 1. In the inverse sweep PLL, the phase register f (k) 1103 is initialized with the estimate /<sub>n + 1</sub> phase from preamble to end in reverse sweep PLL, where the process sweeps the entire frame from end to beginning to obtain estimate 3, of phase, m = 0, ..., N<sub>s</sub> -1. The loop frequency register m (k) is initialized with 0 for both directions. Forward and reverse sweeps can be performed simultaneously.
Next, the phase combining stage is started at step 1501. The final phase estimate is the combination of the phase estimates from both forward and reverse scans. At step 1503, the process determines whether the forward scan is in sync; if so, it is determined whether the reverse sweep is in sync, by step 1505. If both forward and reverse sweep are in sync, the final phase estimate 3 (m) is given by
<img file="ES2340552T3_D0017.tif" />
Otherwise, if only the forward sweep is in sync, then = 0, jV „- 1 is calculated as in step 1509. However, if only the reverse sweep (as determined in step 1511) is in sync, then § (m) = m = 0, ....- 1, (step 1513).
IS 2 340 552 T3
If neither sweep is in sync, then, as in step 1515,
<img file="ES2340552T3_D0018.tif" />
<img file="ES2340552T3_D0019.tif" />
As in the pilot mode, before combining the phase, the process tests for any substantial phase errors at the end of both sweeps as follows. A phase error is defined 7<sup>=</sup> CO - 1) - Oi at the end of the direct sweep, in which the following unwrapping technique is used in e<sub>F</sub>, I mean,
If | e<sub>F</sub>| <t<sub>s</sub>, where T<sub>s</sub> is a predetermined threshold, eg - ττ / Μ (π / 4 for QPSK), declaring that the forward sweep is in sync. Likewise, the following phase error is defined<sub>ε</sub> _ g - φ at the end of the direct sweep. The same unwrapping technique can be used in e<sub>s</sub>. If | e<sub>s</sub>| <í<sub>s</sub>, the reverse sweep is considered to be in sync.
The above carrier phase tracking process, whether it works using QPSK or 8PSK modulation, exhibits good performance characteristics, whereby, for example, the two-sweep loop is resistant to thermal noise and phase noise. Also, the phase tracking root mean square error is low (eg only 3.3 degrees for QPSK modulation with 1 dB DVB-S phase noise mask.
Figure 16 illustrates a computer system on which an embodiment according to the present invention can be implemented. Computer system 1600 includes a bus 1601 or other communication mechanism to communicate information, and a processor 1603 coupled to bus 1601 to process information. Computer system 1600 also includes main memory 1605, such as random access memory (RAM) or other dynamic storage device, coupled to bus 1601 to store information and instructions to be executed by processor 1603. Main memory 1605 It can also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by the 1603 processor. Computer system 1600 further includes read-only memory (ROM) 1607 or other static storage device coupled to bus 1601 to store static information and instructions for processor 1603. A storage device 1609, such as a magnetic disk or disk optical, it is additionally coupled to bus 1601 to store information and instructions.
Computer system 1600 may be coupled via bus 1601 to a display 1611, such as a cathode ray tube, liquid crystal display, active matrix display, or plasma display, to display information to a computer user. An input device 1613, such as a keyboard that includes alphanumeric and other keys, is coupled to bus 1601 to communicate information and command selections to processor 1603. Another type of user input device is the cursor control 1615, such as a mouse, trackball, or cursor arrow keys, to communicate direction information and command selections to the processor 1603 and to control the movement of the cursor. on screen 1611.
In accordance with one embodiment of the invention, the various carrier synchronization processes may be provided by computer system 1600 in response to processor 1603 executing an array of instructions contained in main memory 1605. Such instructions may be entered into memory main 1605 from other computer-readable media such as storage device 1609. Execution of the arrangement of instructions contained in main memory 1605 causes processor 1603 to perform the processing steps described herein. One or more processors in a multiprocessing arrangement can also be used to execute the instructions contained in main memory 1605. In alternative embodiments, a physical wiring module can be used in place of, or in combination with, software instructions to implement the embodiment of the present invention. Thus, embodiments of the present invention are not limited to any specific combination of hardware and software module.
Computer system 1600 also includes a communication interface 1617 coupled to bus 1601. Communication interface 1617 provides a two-way data communication link with a network link 1619 connected to a local network 1621. For example, the 1617 interface can be a digital subscriber line (DSL) card or modem, an integrated services digital network (ISDN) card, a cable modem, or a telephone modem. to provide a data communication connection with a corresponding type of telephone line. As another example, the communication interface 1617 may be a local area network (LAN) card (for example, for Ethernet ™ or an Asynchronous Transfer Mode (ATM) network) to provide a data communication connection with a supported local area network (LAN). Wireless links can also be implemented. In
In any such implementation, the communication interface 1617 emits and receives electrical, electromagnetic or optical signals that carry digital data streams representing various types of information. In addition, the communication interface 1617 can include peripheral interface devices such as a USB interface (Universal Serial Bus = universal serial bus), a PCMCIA interface (Personal Computer Memory Card International Association = International Association of Memory Cards for Personal Computers). , etc.
Network link 1619 typically provides data communication, over a network or more networks, with other data devices. For example, the network link 1619 may provide a connection through the local network 1621 to a host computer 1623 that has connectivity to a network 1625 (for example, a wide area network (WAN) or the network global packet data communication now commonly referred to as "Internet") or with data equipment managed by the service provider. Both the local 1621 network and the 1625 network use electrical, electromagnetic, or optical signals to carry information and instructions. The signals across the various networks and the signals on the network link 1619 and through the communication interface 1617, which communicate digital data with the computer system 1600, are exemplary forms of carrier waves that carry information and data. instructions.
Computer system 1600 can broadcast messages and receive data, including program code, over network (s), network link 1619, and communication interface 1617. In the Internet example, a server (not shown) could transmit requested code pertaining to an application program, to implement an embodiment of the present invention, over network 1625, local network 1621, and communication interface 1617. Processor 1603 can execute transmitted code as it is received and / or store the code in storage device 1609 or other non-volatile storage for later execution. In this way, the computer system 1600 can obtain application code in the form of a carrier wave.
The term "computer-readable medium" as used herein refers to any medium that participates in providing instructions to the processor 1603 for execution. Such support can take many forms, including, but not limited to, non-volatile supports, volatile supports, and transmission supports. Non-volatile media include, for example, optical or magnetic discs such as storage device 1609. Volatile carriers include dynamic memory such as main memory 1605. Transmission carriers include coaxial cables, copper wire, and fiber optics, including wires that comprise the 1601 bus. Transmission carriers can also take the form of acoustic waves, optical or electromagnetic such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media include, for example, a floppy disk, a floppy disk, a hard disk, a magnetic tape, any other magnetic media, a CD-rOm, CdRW (compact disc-rewritable), DVD, any other optical media, punched cards, paper tape, sheets with optical markings, any other physical media with hole patterns or other optically recognizable signs, a RAM (random access memory), a PROM (programmable read only memory = programmable read-only memory), an EPROM (erasable programmable read only memory = erasable programmable read-only memory), a FLASH-EPROM, any other memory chip or cartridge, a carrier wave or any other media that a computer can read.
Various forms of computer-readable media can be involved in providing instructions to a processor for execution. For example, instructions for carrying out at least part of the present invention may be initially carried on a magnetic disk of a remote computer. In such a scenario, the remote computer loads the instructions into main memory and sends the instructions over a phone line using a modem. A modem in a local computer system receives data over the telephone line and uses an infrared signal transmitter to convert the data into an infrared signal and transmit the infrared signal to a portable computing device such as a personal digital assistant (PDA: personal digital assistant) and a laptop. An infrared signal detector in the portable computing device receives the information and instructions carried by the infrared signal and places the data on a bus. The bus carries data to main memory, from which a processor retrieves and executes instructions. Instructions received by main memory can optionally be stored on a storage device before or after execution by the processor.
Accordingly, the various embodiments of the present invention provide a method of achieving carrier synchronization in an interactive digital broadcasting system using low density parity check (LDPC) codes and higher order modulation schemes. A physical layer frame includes a preamble and multiple code segments. In an exemplary embodiment, a unique word (UW) is inserted before each of the code segments as a pilot block. The preamble and pilot blocks serve as an instruction block. The carrier synchronization process uses the command block to estimate the carrier frequency and phase and reset the phase tracking loop for each new segment. The frequency acquisition process involves calculating an autocorrelation of a continuous wave (CW) signal with removed data. The carrier frequency of the received signal is estimated based on a weighted sum of the non-enveloped phase of the accumulated autocorrelation values. With respect to frequency tracking, a feedforward structure is implemented to generate estimates and update the carrier frequency once per LDPC frame based on the phase estimates from the instruction block (i.e., preamble and / or single word (UW)). For phase tracking, a two-scan phase locked loop (PLL) architecture with a maximum probability (ML) phase detector is used. The two-scan phase-locked loop (PLL) tracks carrier phase on a segment-by-segment basis to estimate carrier phase based on both past and future samples by sweeping the data segment in both forward and reverse directions. A segment
ES 2 340 552 T3 is a code segment. The above arrangement advantageously reduces the need to introduce additional auxiliary resource for carrier synchronization, and significantly reduces the cycle slip rate and limits its error propagation impact. The described arrangement also works well in low signal-to-noise ratio environments, providing good immunity against thermal noise and phase noise. Additionally, the frequency estimation process provides a large margin of frequency acquisition and short acquisition time. Accordingly, the above method advantageously provides fast and efficient carrier synchronization.
Although the present invention has been described in connection with a number of embodiments and implementations, the present invention is not so limited but rather includes the various modifications and obvious arrangements that are within the scope of the appended claims.
Contents9
36 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15 Sheet 16 Sheet 17 Sheet 18 Sheet 19 Sheet 20 Sheet 21 Sheet 22 Sheet 23 Sheet 24 Sheet 25 Sheet 26 Sheet 27 Sheet 28 Sheet 29 Sheet 30 Sheet 31 Sheet 32 Sheet 33 Sheet 34 Sheet 35 Sheet 36
58 members in 12 offices
Priority claims16
| Document | Office | Kind | Date |
|---|---|---|---|
| 47837603 | United States of America | P | |
| 47837603 | United States of America | P | |
| 48211103 | United States of America | P | |
| 48211103 | United States of America | P | |
| 48211703 | United States of America | P | |
| 48211703 | United States of America | P | |
| 81638504 | United States of America | A | |
| 81638504 | United States of America | A | |
| 478376P08007758 | – | – | – |
| 482111P | – | – | – |
| 482117P | – | – | – |
| 816385 | – | – | – |
| US20030478376P | – | – | – |
| US20030482111P | – | – | – |
| US20030482117P | – | – | – |
| US20040816385 | – | – | – |
Members58
| Document | Office | Kind | |
|---|---|---|---|
| CA2470546A1 | Canada | A1 | |
| CA2470782A1 | Canada | A1 | |
| EP1487146A1 | European Patent Office (EPO) | A1 | |
| EP1487166A2 | European Patent Office (EPO) | A2 | |
| US2004252229A1 | United States of America | A1 | |
| US2004252725A1 | United States of America | A1 | |
| KR20040107436A | Republic of Korea | A | |
| KR20040107437A | Republic of Korea | A | |
| EP1487166A3 | European Patent Office (EPO) | A3 | |
| JP2005006338A | Japan | A | |
| JP2005012794A | Japan | A | |
| CN1630280A | China | A | |
| CN1630281A | China | A | |
| HK1073747A | Hong Kong, China | A | |
| HK1073747A1 | Hong Kong, China | A1 | |
| HK1077440A | Hong Kong, China | A | |
| HK1077440A1 | Hong Kong, China | A1 | |
| KR100612804B1 | Republic of Korea | B1 | |
| JP3920876B2 | Japan | B2 | |
| KR100741629B1 | Republic of Korea | B1 | |
| JP4071743B2 | Japan | B2 | |
| JP2008099319A | Japan | A | |
| US7369633B2 | United States of America | B2 | |
| EP1942622A2 | European Patent Office (EPO) | A2 | |
| EP1942622A3 | European Patent Office (EPO) | A3 | |
| US2008181344A1 | United States of America | A1 | |
| EP1487146B1 | European Patent Office (EPO) | B1 | |
| AT447806T | Austria | T | |
| ATE447806T1 | Austria | T1 | |
| EP2124377A2 | European Patent Office (EPO) | A2 | |
| DE602004023896D1 | Germany | D1 | |
| EP2124377A3 | European Patent Office (EPO) | A3 | |
| EP2144395A1 | European Patent Office (EPO) | A1 | |
| EP1942622B1 | European Patent Office (EPO) | B1 | |
| ES2334229T3 | Spain | T3 | |
| AT458338T | Austria | T | |
| ATE458338T1 | Austria | T1 | |
| PT1942622E | Portugal | E | |
| DE602004025637D1 | Germany | D1 | |
| ES2340552T3This record | Spain | T3 | |
| DK1942622T3 | Denmark | T3 | |
| EP1487166B1 | European Patent Office (EPO) | B1 | |
| AT476043T | Austria | T | |
| ATE476043T1 | Austria | T1 | |
| CA2470546C | Canada | C | |
| DE602004028313D1 | Germany | D1 | |
| US7817759B2 | United States of America | B2 | |
| CA2470782C | Canada | C | |
| US2011033016A1 | United States of America | A1 | |
| CN1630280B | China | B | |
| EP2124377B1 | European Patent Office (EPO) | B1 | |
| AT529967T | Austria | T | |
| ATE529967T1 | Austria | T1 | |
| JP4851424B2 | Japan | B2 | |
| CN1630281B | China | B | |
| EP2144395B1 | European Patent Office (EPO) | B1 | |
| US8208499B2 | United States of America | B2 | |
| US8275081B2 | United States of America | B2 |
Numbers
- Publication, DOCDB
- 2340552
- Publication, EPODOC
- ES2340552T
- Application
- 8007758
- Application, DOCDB
- 08007758
- Application, EPODOC
- ES20080007758T
Titles2
- Spanish
- SINCRONIZACION DE PORTADORA UTILIZANDO UN PREAMBULO Y BLOQUES DE PILOTO DISPERSOS.
- English
- CARRIER SYNCHRONIZATION USING A PREAMBLE AND DISPERSED PILOT BLOCKS.
Classification
- CPC, 8
- H04L1/0057
- H04L7/048
- H04L27/2272
- H04L2027/0028
- H04L2027/0055
- H04L2027/0067
- H04L2027/0093
- H04L2027/0095
- IPC, 3
- H04L27 227
- H04L7 04
- H04L27 00