Digital baseband receiver including a high pass filter compensation module for suppressing group delay variation distortion incurred due to analog high pass filter deficiencies

ES 2 294 517 T3

DESCRIPTION

Digital baseband receiver that includes a high pass filter compensation module to suppress group delay distortion suffered due to deficiencies in analog high pass filters.

Field of the invention

The present invention relates generally to receiver design in wireless communication systems. More particularly, the present invention relates to digital signal processing (DSP) techniques that are used to compensate for group delay variation distortion introduced into an analog radio receiver.

Background

Existing wireless system architecture or structural configurations place severe constraints on the system designer in receiving communication signals. In addition, such configurations often provide low-reliability communication links, high operating costs, and an undesirably low level of integration with other system components.

As shown in Figure 1, a conventional radio frequency (RF) receiver 100 includes an analog radio receiver 105, at least one analog to digital converter (ADC) 110, a controller 115 and a modem [modulator-demodulator] 120. The analog radio receiver 105 is a direct conversion receiver that includes an antenna 125 intended to receive a wireless communication signal, a band pass filter 130, a low noise amplifier (LNA) 135, an optional second filter 140 (for example, a band pass filter), a demodulator 145, which has two outputs 150, 155, a phase-locked loop (PLL) 160, a 165A low pass filter (LPF) of analog real signal path, as well as an LPF 165B of analog imaginary signal path, a first stage real signal path amplifier 170A, a 170B amplifier of first stage imaginary signal path, a 175A high pass filter (HPF) of first stage analog real signal path, a first stage analog imaginary signal path HPF 175B, a second stage real signal path amplifier 180A, a second stage imaginary signal path amplifier 180B, a second stage analog real signal path HPF 185A, and a second stage analog imaginary signal path HPF 185B . Each of amplifiers 170A, 170b, 180A, 180B includes a high gain stage resident in the analog domain of RF receiver 100.

The modem 120 controls the switching of the LNA 135. The PLL 160 generates a local oscillator signal (LO - "local oscillator") to control the two outputs 150, 155 of the demodulator 145. The output 150 is an in-phase (I) output of demodulator 145, adapted to output a real signal component of the wireless communication signal. Output 155 is a quadrature (Q - "quadrature") output of demodulator 145, intended to output an imaginary signal component of the wireless communication signal. The analog LPFs 165A, 165B selectively control the bandwidth of the I and Q outputs, 150 and 155, respectively. The outputs of the analog LPFs 165A, 165B are then amplified by the first and second stage amplifiers, 170A, 170B, 180A, 180B, respectively.

Due to the high gain requirements, the first and second stage analog HPFs, 175A, 175B, 185A, 185B, are included in the analog radio receiver 105 in order to provide capacity after each of the first and second stages. 170A, 170B, 180A, 180B of amplifier, respectively, so the first and second gain stages are connected in AC [alternating current - "alternate current"], and any residual direct current (DC - “DC (“ direct current ”)) is eliminated in order to avoid DC offset. Each of the analog HPFs 175A, 175B, 185A, 185B has a signal input, a signal output, at least one capacitor (C), which connects the signal output to the signal input, and at least one resistor ( R), which connects the capacitor output to ground, thereby forming an RC filter. Analog HPFs 175A, 175B, 185A, 185B alter the spectral shape (i.e. reduce energy) of the lower portion (for example, below 50 kHz) of the frequency domain response, associated with the components real and imaginary signal.

In the conventional RF receiver 100 of Figure 1, the ADC 110 is connected to the output of the second stage analog HPFs 185A, 185B. The ADC 110 outputs digital I and Q outputs 190, 195. Controller 115 maintains control over all active components of an analog radio receiver 105 and ADC 110.

In the analog radio receiver 105, the analog HPFs 175A, 175B, 185A, 185B are used to guarantee the spectral shape of the wireless communication signal received through the antenna 125, before it is sampled by the ADC. 110. Typically, the specifications about analogue HPFs 175A, 175B, 185A, 185B are very stringent, such that implementation requires higher order filtering. Specifically, one such specification is the error vector magnitude (EVM - "error vector magnitude"), which is a normalized mean squared error (MSE) measurement. Implementing higher order filter designs for the 175A, 175B, 185A, 185B analog HPFs can be complicated and expensive. Thus, tolerances on certain parts for analogue HPFs 175A, 175B, 185A, 185B can lead to unacceptable production performance. Reducing the design complexity of the 175A, 175B, 185A, 185B analog HPFs can be carried

ES 2 294 517 T3 performed with a lower order filter design with less stringent specifications. However, the use of such a filter design on the 175A, 175B, 185A, 185B analog HPFs will result in distortion in the group delay variation if no compensation is introduced after the 175A, 175B analog HPFs, 185A, 185B, thus degrading the behavior of the RF receiver 100.

Since the costs of HPFs that process or treat analog RF signals are higher than those of components that use DSP, it is desired to provide a digital baseband (DBB - "digital baseband") system, including a receiver of low cost with low noise and minimal power requirements, using DSP techniques to compensate for distortion in group delay variation caused by analog HPFs.

US 2002/0990924 describes an RF tuner and tuning method employing quadrature analog mixing with a coarse tunable local oscillator, for a near baseband, bandpass region, followed by a conversion A / D [analog to digital] of I and Q signals, correction of phase errors, group delay and amplitude, image rejection and translation to the baseband. It describes subsampling or decimation filters 34 and 36, one of which includes a group delay correction. Decimation filters are designed using lookup tables, among others.

Summary

The present invention consists of a DBB receiver to adjust the response in the frequency domain of at least one of the real and imaginary signal components of a wireless communication signal, in order to suppress the distortion in the variation of the delay group caused by the use of low cost analog HPFs in the receiver. The receiver includes a demodulator, a digital high pass filter compensation (HPFC) module, at least one analog real signal path HPF, and at least one analog imaginary HPF. The HPFC digital module reduces a cutoff frequency (that is, a vertex frequency), established by the analog HPFs for the frequency-domain responses of real and imaginary signal components, by providing a first offset signal that has a first default value (K₁). The HPFC digital module adjusts the gain of the high-pass response of the frequency domains of real and imaginary signal components, by providing a second offset signal that has a second signal of predetermined value (K₂).

The present invention can be incorporated into a DBB receiver, a wireless transmit / receive unit (WTRU), an integrated circuit (IC), a system and a method of wireless communication, or any other communication mechanism that is desired.

The demodulator has real and imaginary signal outputs. The demodulator receives the communication signal and outputs real and imaginary signal components of the communication signal at the real and imaginary signal outputs. The real analog HPF is in communication with the real signal output of the demodulator and with the real signal path of the digital HPFC module. The imaginary analog HPF is in communication with the imaginary signal output of the demodulator and with the imaginary signal path of the digital HPFC module. The HPFC digital module suppresses distortion in group delay variation caused by at least one of the real and imaginary analog HPFs. The HPFC digital module can be selectively enabled or disabled.

The HPFC digital module may include a real signal input to receive the real signal component, as well as a real compensated signal output, intended to output a real compensated output signal. The HPFC digital module may additionally include first and second multipliers, first, second and third adders, as well as a first sample delay unit. The first multiplier can have first and second inputs, and one output. The first input of the first multiplier may receive a first compensation signal having a first predetermined value (Ki). The first adder can have first and second inputs, and one output. The first input of the first adder can be connected to the real signal input of the HPFC digital module, and the output of the first adder can be connected to the second input of the first multiplier. The second adder can have first and second inputs, and one output. The first input of the second adder may be connected to the output of the first multiplier. The first sample delay unit may have an input and an output. The input of the first sample delay unit may be connected to the output of the second adder. The second multiplier can have first and second inputs, and one output. The first input of the second multiplier can receive a second offset signal having a second predetermined value (K₂). The second input of the second multiplier may be connected to the output of the first sample delay unit, to the second input of the second adder, and to the second input of the first adder. The third adder can have first and second inputs, and one output. The first input of the third adder may be connected to the first input of the first adder. The second input of the third adder may be connected to the output of the second multiplier. The output of the third adder may be connected to the actual compensated signal output of the HPFC digital module.

The output of the second multiplier can be subtracted from the real signal component by means of the third adder. The output of the first sample delay unit can be subtracted from the actual signal component by means of the first adder.

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The HPFC digital module may further include an imaginary signal input to receive the imaginary signal component, as well as an imaginary compensated signal output, to output an imaginary compensated output signal. The HPFC digital module may additionally include third and fourth multipliers, fourth, fifth and sixth adders, as well as a second sample delay unit. The third multiplier can have first and second inputs, as well as one output. The first input of the third multiplier can receive the first offset signal, which has the first predetermined value (K |). The fourth adder can have first and second inputs, and one output. The first input of the fourth adder can be connected to the imaginary signal input of the HPFC digital module, and the output of the fourth adder can be connected to the second input of the third multiplier. The fifth adder can have first and second inputs, and one output. The first input of the fifth adder may be connected to the output of the third multiplier. The second sample delay unit may have an input and an output. The input of the second sample delay unit may be connected to the output of the fifth adder. The fourth multiplier can have first and second inputs, and one output. The first input of the fourth multiplier can receive the second offset signal, which has the second predetermined value (K₂). The second input of the fourth multiplier may be connected to the output of the second sample delay unit, to the second input of the fifth adder, and to the second input of the fourth adder. The sixth adder can have first and second inputs, and one output. The first input of the sixth adder may be connected to the first input of the fourth adder. The second input of the sixth adder may be connected to the output of the fourth multiplier. The output of the sixth adder may be connected to the imaginary compensated signal output of the HPFC digital module.

The output of the fourth multiplier can be subtracted from the imaginary signal component by means of the sixth adder. The output of the second sample delay unit can be subtracted from the imaginary signal component by means of the fourth adder.

Brief description of the drawing (s)

A more detailed understanding of the invention can be had from the following description of a preferred example, given by way of example and to be understood in conjunction with the accompanying drawings, in which:

Figure 1 is a block diagram of a conventional RF receiver that includes an analog radio receiver;

Figure 2 is a block diagram of a DBB RF receiver with a digital high-pass filter compensation module, configured in accordance with a preferred embodiment of the present invention;

Figure 3 shows an exemplary configuration of the digital high-pass filter compensation module in the DBB RF receiver of Figure 2; Y

Figure 4 is a graph illustrating how the compensation values ​​K | and K2 used in the DBB RF receiver high pass filter compensation module of Figure 2 affect the frequency domain response of the real and imaginary signal components.

Detailed description of the preferred embodiments

Figure 2 is a block diagram of a DBB RF receiver, configured in accordance with a preferred embodiment of the present invention. While reference will be made to the invention in terms of being implemented in a receiver 200, it is also to be understood by those skilled in the art that the invention also pertains to a transceiver, or transceiver.

Preferably, the method and system described herein are incorporated into a wireless transmit / receive unit (WTRU). In the following, a WTRU includes user equipment, a mobile station, a fixed or mobile subscriber unit, a paging device, or any other type of device capable of operating in a wireless environment. The features of the present invention can be incorporated into an integrated circuit (IC) or configured in a circuit comprising a plurality of interconnected components.

The present invention is applicable to communication systems using time division duplex communication (TDD - "time division duplex"), time division multiple access (TDMA - "time division multiple access"), communication frequency division duplex (FDD), code division multiple access (CDMA), CDMA 2000, synchronous time division CDMA (TDSCDMA), and orthogonal frequency division multiplexing (OFDM). However, it is contemplated that the present invention is applicable to other types of communication systems as well.

As shown in Figure 2, the DDB 200 RF receiver includes a digital high pass filter compensation (HPFC) module 205, which has real (I) and imaginary signal paths. (Q),

ES 2 294 517 T3 connected to the digital signal outputs I and Q, 190, 195. The HPFC digital module 205 additionally includes offset outputs 280, 290 and can be controlled by a controller 115.

Figure 3 shows an example configuration of the HPFC digital module 205 in the DDB 200 RF receiver. The HPFC 205 digital module includes digital circuitry that expands the low frequency components (for example, between 5 and 50 kHz) and reduces the cutoff frequency (that is, the vertex frequency) set by the analog HPFs 175A, 175B , 185A, 185B, such that the spectral shape of the frequency response domain, altered by the analog HPFs 175A, 175B, 185A, 185B, is restored. In this way, the distortion introduced by the analog HPFs 175A, 175B, 185A, 185B is suppressed. One or more additional 205 HPFC digital modules can be connected in series with the 205 HPFC digital module in order to provide additional compensation for distortion due to the 175A, 175B, 185A, 185B analog HPFs.

The HPFC digital module 205 includes real (I) and imaginary (Q) signal paths, through which the real and imaginary signal components from the digital outputs 190, 195 of the ADC 110 are passed, respectively. The HPFC 205 digital module is a digital filter that has characteristics that have been selected such that the frequency domain response of the HPFC 205 digital module will restore the frequency characteristics distorted by the 175A, 175B, 185A analog HPFs. , 185B, on the analog radio receiver 105. When the frequency response of the HPFC digital module 205 is convoluted with the frequency response of the analog HPFs 175A, 175B, 185A, 185B, the distortion caused by the analog HPFs 175A, 175B, 185A, 185B is suppressed. On the other hand, the low-frequency components that are filtered out by the analog HPFs 175A, 175B, 185A, 185B, are reconstructed by providing a digital filter that has a low-pass frequency response that adds or adds to the response. in high pass frequency of the analog HPFs 175A, 175B, 185A, 185B. The real and imaginary signal paths of the HPFC 205 digital module have the same frequency characteristics to eliminate the distortion that occurs in each of the I and Q signal paths due to the variation in group delay caused by the HPFs. analog 175A, 175B, 185A, 185B. Thus, the compensated real and imaginary signals output by the compensated real and imaginary outputs 280, 290 of the HPFC digital module 205 do not include distortion. The HPFC digital module can be selectively enabled or disabled, as determined by controller 115.

As shown in Figure 3, the HPFC digital module includes adders 210A, 210B, 230A, 230B, accumulator circuits 215A, 215B, and multipliers 220A, 220B, 225A, 225B. The adders 230A, 230B subtract the real and imaginary HPF compensation signals 245A, 245B from the real and imaginary signal components, respectively, in order to provide real and imaginary compensated outputs 280, 290 with expanded high pass frequency responses.

The accumulator circuit 215A includes a sample delay unit 235A and an adder 240A. An output of adder 240A is connected to an input of sample delay unit 235A. An output of the sample delay unit 235A is connected to a first input of the adder 240A. The accumulator circuit 215A outputs an accumulator output signal 250A, which is subtracted from the actual signal component by means of the adder 210A, in order to generate a feedback signal 255A to the accumulator. A first compensation signal, which has a Ki value and which is received by an input 260A of the multiplier 220A, is multiplied by the accumulator feedback signal 255A to generate a compensated accumulator feedback signal 265A, which is supplied as input to a second input of adder 240A. In this way, the adder 240A provides a sample signal 270A to the input of the sample delay unit 235A. The signal sample 270A consists of the sum of the compensated accumulator feedback signal 265A and the accumulator output signal 250A. A second offset signal, which has a K value₂ and which is received at an input 275A of multiplier 225A, is multiplied by the accumulator output signal 250A in order to generate the actual HPF compensation signal 245A.

Still referring to Figure 3, the accumulator circuit 215B includes a sample delay unit 235B and an adder 240B. An output of adder 240B is connected to an input of sample delay unit 235B. An output of the sample delay unit 235B is connected to a first input of the adder 240B. The accumulator circuit 215B outputs an accumulator output signal 150B, which is subtracted from the imaginary signal component by means of the adder 210B, in order to generate a feedback signal 255B to the accumulator. The first compensation signal, which has a Ki value and is received at an input 260B of the multiplier 220B, is multiplied by the accumulator feedback signal 255B in order to generate a compensated accumulator feedback signal 265B, which is supplied as input to a second input of adder 240B. In this way, the adder 240B provides a sample signal 270B to the input of the sample delay unit 235B. The signal sample 270B consists of the sum of the compensated accumulator feedback signal 265B and the accumulator output signal 250B. The second offset signal, which has a K2 value and is received at an input 275B of multiplier 225B, is multiplied by the accumulator output signal 250B to generate the imaginary HPF offset signal 245B.

In summary, the HPFC digital module 05 includes a real signal input (ADC 11 output 190) to receive the real signal component (I), and a real compensated signal output 280 to output a compensated output signal. real. The HPFC digital module 205 further includes first and second multipliers 220A, 225A, first, second, and third adders 210a, 240A, 230A, and a first sample delay unit 235A. The first multiplier 220A has first and second inputs, and one output. The first entry

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260A from the first multiplier 220A receives a first compensation signal having a first predetermined value (K₁). The first adder 210A has first and second inputs, and one output. The first input of the first adder 210A is connected to the real signal input (output 190 of the AdC 110) of the digital HPFC module 205, and the output of the first adder 210A is connected to the second input of the first multiplier 220A. The second adder 240A has first and second inputs, and one output. The first input of the second adder 240A is connected to the output of the first multiplier 220A. The first sample delay unit 235A has an input and an output. The input of the first sample delay unit 235A is connected to the output of the second adder 240A. The second multiplier 225A has first and second inputs, and one output. The first input 275A of the second multiplier 225A receives a second compensation signal having a second predetermined value (K₂). The second input of the second multiplier 225A is connected to the output of the first sample delay unit 235A, to the second input of the second adder 240A, and to the second input of the first adder 210A. The third adder 230A has first and second inputs, and one output. The first input of the third adder 230A is connected to the first input of the first adder 210A. The second input of the third adder 230A is connected to the output of the second multiplier 225A. The output of the third adder 230A is connected to the actual compensated signal output 280 of the HPFC digital module 205.

The output of the second multiplier 225A is subtracted from the real signal component by means of the third adder 230A. The output of the first sample delay unit 235A can be subtracted from the actual signal component by means of the first adder 210A.

On the other hand, the HPFC digital module 205 includes an imaginary signal input (output 195 of the ADC 110) to receive the imaginary signal component (Q), as well as an imaginary compensated signal output 290, in order to supply as output an imaginary compensated output signal. The HPFC digital module 205 further includes third and fourth multipliers, 220B, 225B, fourth, fifth and sixth adders 210B, 240B, 230B, as well as a second sample delay unit 235B. The third multiplier 220B has first and second inputs, as well as one output. The first input 260B of the third multiplier 220B receives the first compensation signal, which has the first predetermined value (K₁). The fourth adder 210B has first and second inputs, and one output. The first input of the fourth adder 210B is connected to the imaginary signal input (output 195 of the ADC 110) of the HPFC digital module 205, and the output of the fourth adder 210B is connected to the second input of the third multiplier 220B. The fifth adder 240B may have first and second inputs, and one output. The first input of the fifth adder 240B is connected to the output of the third multiplier 220B. The second sample delay unit 235B has an input and an output. The input of the second sample delay unit 235B is connected to the output of the fifth adder 240B. The fourth multiplier 225B has first and second inputs, and one output. The first input 275B of the fourth multiplier 225B receives the second offset signal, which has a second predetermined value (K2). The second input of the fourth multiplier 225B is connected to the output of the second sample delay unit 235B, to the second input of the fifth adder 240B, and to the second input of the fourth adder 210B. The sixth adder 230B has first and second inputs, and one output. The first input of the sixth adder 230B is connected to the first input of the fourth adder 210B. The second input of the sixth adder 230B may be connected to the output of the fourth multiplier 225B. The output of the sixth adder 230B is connected to the imaginary compensated signal output 290 of the HPFC digital module 205.

The output of the fourth multiplier 225B is subtracted from the imaginary signal component by means of the sixth adder 230B. The output of the second sample delay unit 235B is subtracted from the imaginary signal component by means of the fourth adder 210B.

The cutoff frequency of the responses in the frequency domain of the real and imaginary signal components is lowered in response to fit the first predetermined value (K₁) of the first offset signal received at the first inputs 260A, 260B of the first and third multipliers 220A, 220B, respectively. The gain of the high-pass response of the frequency domains of the real and imaginary signal components is adjusted in response to the reception of the second predetermined value (K2) of the second offset signal at the first inputs 275A, 275B of the second and fourth multipliers 225A, 225B, respectively.

The behavior of the HPFC digital module 205 is based on the values ​​of K1 and K2. Figure 4 illustrates how the values ​​of K1 and K2 affect the spectral shape of the response in the frequency domain of the real and imaginary signal components. Adjusting the value of K1 changes the cutoff frequency of the I and Q signal components of F_c1 to F_c2. Setting the K value₂ changes the gain of the frequency domain high pass response provided by the HPFC digital module 205, by dividing the accumulator output signals 250A, 250B by 1-K2.

It is to be understood that the compensation of the I and Q signal components can be implemented by the HPFC module 205 at a sample rate substantially higher than the bit rate (for example, ten times the rate of the transmission of bits). bits).

While this invention has been shown and described particularly with reference to preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail can be made therein without departing from the scope of the invention described herein at the above.