Data processing apparatus that identifies a communication clock frequency

ES 2 294 366 T3

DESCRIPTION

Data processing apparatus that identifies a communication clock frequency.

The invention relates to a data processing apparatus with an input port for receiving a communication signal.

In data processing equipment, serial bit streams of data are frequently used to communicate data between different devices. The successively received bits are formed into data words of, for example, 8 bits. During reception, the sampling of the different bits from the stream is usually carried out under the control of a clock signal. A clock signal with a predetermined fixed frequency is frequently used for this purpose, but selection between alternative frequencies is also known. For example, from the patent application PCT (Patent Cooperation Treaty) No. WO9960760, a clock circuit is known that adapts the divider, with which the sampling clock signal is obtained from a master clock, to measured characteristics of the communication sign.

Document US 2002/101884 describes a method and apparatus for operating a bus according to the Local Interconnect Network (LIN) specification, in which the slave (slave) devices do not need prior knowledge about the speed in baud rate before receiving transmissions. The method provides for the synchronization of the slave devices, where an interrupt search is initiated after the communication bus has been idle. In addition, a new interrupt search is initiated on bus reset, power-up, or wake-up from a sleep (sleep) mode.

Another example of processing equipment that uses adaptive bit periods is equipment that uses the so-called local interconnect network (LIN) bus protocol. The Local Interconnection Network (LIN) protocol provides what is necessary for the transmission of a communication signal containing messages, without transmission of a separate clock signal. The clock signals are produced locally in a receiver of the communication signal. Each message contains a sync field that defines a time interval in which an electronic toggle bit pattern is transmitted. This bit pattern has the bit period that will be used during the message. The sync field allows a receiver circuit to generate a local clock with a correct bit period, usually by selecting one of a number of available bit frequencies.

According to the Local Interconnection Network (LIN) protocol, the sync field is preceded by a so-called sync break that allows the receiver to identify the beginning of a message and the sync field, which immediately follows the sync break. The sync break contains a unique bit pattern that cannot occur elsewhere in messages: a continuous low-level signal that lasts longer than the spacing between successive bytes in the rest of the message. Thus, the sync interrupt functions as a detection interval to determine whether or not to follow a synchronization field, and the synchronization field functions as a measurement interval to measure a period of bits.

Such equipment works well when predictable clock signal frequencies are used, with frequencies within a predetermined limited range or within a small number of frequency ranges, as in conventional local interconnect network (LIN) receivers. Problems arise when the clock signal frequency is allowed to vary substantially continuously over a wide range. In this case, the duration of a synchronization interruption interval at a high clock frequency may be equal to the duration of a low level of the communication signal at a low clock frequency. When the clock frequency is not previously known with sufficient precision, the sync break intervals cannot be reliably distinguished from normal message data. Consequently, it has been necessary to use end-of-a-message detection before looking for a next sync break interval, that is, to integrate message processing and frequency selection. This makes the receiver circuits more expensive.

Among others, an object of the invention is to provide a data processing apparatus that supports the detection of synchronization fields when a communication clock frequency can vary over a wide range, without requiring information about the end of messages.

Among others, a further object of the invention is to provide continuous monitoring for the beginning of a message, in parallel with the reception of the message.

The invention provides a data processing apparatus according to claim 1. According to the invention, the apparatus looks for combinations of potential sync breaks and sync fields identified by those potential sync breaks, and subsequently verifies whether the potential sync break, which typically precedes its identified sync field, has had a duration that it is appropriate for the bit period that is specified by its sync identified field. A sample clock signal, with a bit period adapted to the sync field, is applied to sample bits from the message only if the duration of the potential sync interruption has been found to be appropriate for the bit period which is specified by its identified sync field. Thus, any period of bits can be used.

In the local interconnection network (LIN) protocol, the sync interrupt interval identifies the sync field interval in the sense that the sync field interval immediately follows

ES 2 294 366 T3 to the sync break interval in the communication signal, so that the position of the sync field gap is clear once the sync break has been found. However, without departing from the invention, other ways of identifying the sync field interval with the sync interrupt interval can be provided, such as transmitting the sync field interval immediately before the sync interrupt interval, or transmit the sync field interval after a predetermined number of pulses before or after the sync interrupt interval in the communication signal, provided that the sync field interval can be located on the basis of the position of the sync interval. sync break.

In one embodiment, a further check is performed by checking whether the internal timing of the sync field corresponds to the adapted period of bits. Thus, even more reliable detection of the beginning of a message is ensured.

Preferably, the clock source circuit operates in parallel with the receive circuit, continuing said search while said receive circuit is sampling bits from the communication signal. This reduces the risk of missing synchronization interruptions. Preferably, the reception is terminated when a new synchronization interruption is detected during the reception of a message.

These and other objects and advantageous aspects of the invention described using the following figures.

Figure 1 shows a data processing apparatus.

Figure 2 shows instruction execution bursts.

Figure 3 shows a timer circuit.

Figure 4 shows a timing part of an input signal.

Figure 5 shows an additional timer circuit.

Figure 6 shows a processor circuit.

Figure 1 shows a data processing apparatus with an input processor 10 and a further processor 12. The input processor 10 contains an instruction processor 100, an instruction memory 102, a clock circuit 104, a control circuit 106 timer and a handshake (hello) circuit 108. A communication input 14 of the data processing apparatus is coupled to the instruction processor 100 and to the timer circuit 106. Clock circuit 104 is coupled to timer circuit 106 which, in turn, is coupled to instruction processor 100 via handshake circuit 108. Instruction processor 100 is coupled to instruction memory 102, handshake circuit 108, and additional processor 12.

Figure 2 shows a trigger signal 26 with pulses 28, instruction cycle bursts 22 and bit periods 21, and a data word cycle 20 as a function of time. Although Figure 2 only shows a group of bit periods 21 for the bits in a single data word, it should be understood that messages may contain a succession of such groups, each for a successive data word and each with its own data word cycle 20.

In operation, a signal representing temporally successive bits in different bit periods 21 is applied to input 14. Timer circuit 106 generates trigger pulses 28 each time at times when bits are available at input 14. The timing of the firing pulses 28 is critical only insofar as each of the firing pulses 28 is generated somewhere within the period in which the corresponding bit is known to be stable at input 14. Furthermore, the pulses they should have sufficient distance from each other to allow each burst 22 to be completed before the next firing pulse 28. A receive hold circuit can be provided to hold the input bits; in this case, the trigger pulses can even be generated outside the periods in which the bits are stable.

In response to firing pulses 28, instruction processor 100 fetches a series of instructions from instruction memory 102 and executes each series of instructions in a respective burst 22 of instruction cycles. After a number of such bursts 22, all the bits of a data word have arrived at input 14 and have been processed by instruction processor 100. In the last of said bursts 22, the instruction processor 100 extracts the data word to the additional processor 12 in the data word cycle 20. This can be done by extracting all the bits received in parallel, or in series of bits, in which any clock signal can be used to synchronize successive bits of the bits.

Depending on the demands of the context, various types of processing can be performed during bursts 22. In one example, a plurality of parity bits are potentially updated in each burst 22 by successively executing respective instructions to update various parity values ​​in each burst 22 , depending on the value of a bit received and the formulas for the different parity bits (the formulas determine how, if at all

In this way, a bit at a certain position in a data word contributes to respective parity bits; typically, previous value exclusive-OR functions of respective parity bits and received bit are calculated if the formula for the particular parity bit indicates that the particular received bit contributes to the particular parity bit). A typical series of instructions is

<td>f = inpRXD</td><td>Read the input bit inside the f register</td>

<td>m1 = f</td><td>Store the input bit in position m1</td>

<td>m2 = f + m2</td><td>Update the first parity bit at position m2</td>

<td>m3 = f + m3</td><td>Update the second parity bit in position m3</td>

<td>wait</td><td>Suspend operation until next bit</td>

(Depending on the sequence number of the bit in the data word, different parity bits may be updated or the parity bits at positions m2, m3 may not be updated). When all instructions in a burst 22 have been processed, instruction processing is suspended until the next burst 22 is fired. Preferably, no or substantially no internal signal transitions occur in the instruction processor 100 during sleep in order to minimize power consumption. When all the input bits have been processed, the parity bits can be extracted to the additional processor 12 or they can be used by the instruction processor 100 to correct for signal errors.

The handshake (hello) is used to control the operation of the instruction processor 100. Initially, the timer circuit 106 generates a request signal (typically, raising the trigger signal 26). In response to the request signal, the instruction processor 100 begins processing a first of a series of instructions in a burst 22. The instruction processor 100 returns an acknowledgment signal to the timer circuit 106 which denies the request signal in response to it (typically, reducing the trigger signal 26). Once the instruction processor 100 has indicated that it is ready to receive a next request signal, the timer circuit 106 may generate a new request signal but will do so generally with a delay at a time when a new input bit available. Following the trigger signal from the timer circuit 106, the instruction processor 100 generates a series of request signals to itself trigger the execution of subsequent instructions in the series in burst 22. This is repeated until the series of instructions has ended (as indicated by the "wait" instruction in the programming example), after which no further request signals are generated by the instruction processor 100. .

Internally in the instruction processor 100, in principle, handshakes (greetings) can be passed so that any subcircuits that are involved in the execution of instructions are activated by handshakes and, in turn, activate more involved subcircuits. with communication establishments (greetings). Thus, power consumption is reduced since no subcircuit needs to produce signal transitions unless this is necessary for the execution of a particular instruction. Of course, the invention is not limited to establishing communication (greeting) to ensure suspension of operation. For example, a synchronized instruction processor can be used in combination with some form of electronic gate clock control, which ensures that no clock signals are applied to the instruction processor 100 outside of burst 22. This also reduces power consumption. of energy, to be less than with establishment of communication (greeting).

Although the invention has been described in terms of bit reception by instruction processor 100, it will be understood that, without deviating from the invention, instruction processor 100 may also be arranged to transmit data back on communication input 14 in any or all of the 21 bit periods. For example, the instruction processor 100 may return an acknowledgment in a 21 bit period, or it may transmit data in a plurality of 21 bit periods once it has identified, from the information in preceding 21 bit periods , that it is necessary to do so.

Figure 3 shows an example of a timer circuit 106. This example contains a counter / controller 30, a frequency divider 32, a sync field start detector 34, and a sync field stop detector 36. Sync field start detector 34 and sync field stop detector 36 are coupled to input 14 and have outputs coupled to counter / controller 30. Counter / controller 30 has one input coupled to clock circuit 104 and one output coupled to divider 32. Divider 32 has inputs coupled to clock circuit 104 and counter / controller 30 and one output coupled to handshake circuit 108 .

Figure 4 shows an example of a sync part of an input signal from the input

14. This synchronization part corresponds to the synchronization part of the Local Interconnection Network (LIN) protocol that is publicly known per se. This sync part precedes the bit periods 21 of Figure 2. The sync part contains a sync break interval 50 and a sync field interval 52. In sync interruption interval 50, the input signal becomes low

ES 2 294 366 T3 for a first time interval, after which the signal rises to a high level. The length of the sync break interval 50 has been chosen so that it is greater than the length of low levels that can be caused by any bit pattern elsewhere in the message (greater than a zero-filled byte). In the sync field interval 52, the input signal contains four pulses 54 in which the input signal goes low first and then high. Synchronization field 52 is followed by a subsequent message interval in which the 21 bit periods (not shown) occur. The length of the bit periods has a predetermined relationship to the length of the sync field interval 52.

In operation, the input signal is generated by a transmitter (not shown) and processed by timer circuit 106. The start of sync field detector 34 detects the beginning of the sync field interval 52 on the input signal from input 14. Synchronization field start detector 34 sends a signal to counter / controller 30 to reset a count and begin counting clock pulses from clock circuit 104 in response to detection. The sync field stop detector 36 detects the end of the sync field interval 52 and sends a signal to the counter / controller 30 to detect the count. The counter / controller 30 then applies a divider value determined from the counted number of clock pulses to divider 32 which divides the clock frequency by the divided frequency to handshake (hello) circuit 108 to initiate bursts. 22.

In divider 32, a counter circuit (not shown) can be used that generates a pulse each time a set number of clock pulses from clock circuit 104 have been counted. In this case, the set number corresponds to the number of pulses counted by the counter / controller 30 divided by a predetermined factor representing the number of bit periods in the sync field. But the invention is not limited to this type of divider 32.

When the sync field contains more than one bit period, it is possible to determine the number of clock pulses of the clock circuit 106 with a fractional error less than plus or minus one clock pulse. For example, when eight bit periods occur in a sync field, the length of the bit period can be determined to within 1/8 of a clock period. When the divisor 30 uses a simple counter, the fractional precision is discarded. In a further example, fractional precision is exploited by using a digital oscillator that allows the number of clock periods of the clock circuit 106 to vary per bit period so that, on average, the length of the bit period corresponds more approximately to the period bit that has been measured with fractional precision.

For example, such a digital oscillator can be implemented as an adder circuit that adds an increment to a count value in each clock period of clock circuit 104 and generates a pulse indicating a period of bits each time the count value exceeds a threshold, while simultaneously reducing the count at the threshold. In this case, the threshold and / or increment can be set corresponding to a count from counter / controller 30, so that the average number of clock periods of clock circuit 104 per bit period equals the duration fractionally. precise bit period determined from sync field by counter / controller 30. As a result, the number of clock pulses per bit period can vary so that, on average, the length of the bit period equals the fractionally precise bit period required.

The clock circuit 106 is preferably designed so that the frequency of the clock pulses from the clock circuit 106 is high enough so that the errors in the frequency of the trigger signal pulses 28 are so small that they are not Fails during sampling of bits from input signal. Typically, the errors include timing errors due to unpredictable relative timing of transitions in the clock signal from clock circuit 106 and transitions in the input signal. The maximum cumulative effect of these errors is an error that is a predetermined number of times (eg, 10) the duration of the clock period of the clock signal from the clock circuit 106. Given a desired precision (e.g., no greater than 1.5% error at the end of a 9-bit data word transmitted at 20 kilobits per second), a minimum supported frequency can be obtained from the clock circuit 104 (e.g. , 1.4 MHz in this case).

Thus, the timer circuit 104 adapts the frequency of the trigger pulses 28 to a measured characteristic of the input signal at input 14, to allow the instruction processor 100 to process the incoming bits with a short burst 22 of execution runs. instructions.

Furthermore, other characteristics of the input signal can be used to detect whether a data word is supplied, that is to determine whether trigger pulses should be generated. To this end, detection of the synchronization break interval 50 and / or detection of the correct number of pulses 54 with appropriate duration in the synchronization field interval 52 may be used. The low signal level 53 in the sync break interval 50 persists for a certain minimum duration. This minimum duration remains in a predetermined relationship to the duration of the sync field interval 52. As well as for setting the divider value, therefore the timer circuit 106 can be arranged to generate successive firing pulses 28, as controlled by the timing interval, only after a corresponding timing break has been detected.

ES 2 294 366 T3

Timer circuit 106 is capable of performing sync interrupt monitoring in parallel with normal message processing by input processor 10. Thus, continuous monitoring of synchronization interruptions is possible. Synchronization interruptions will not be missed because the input processor 10 is busy processing a message.

Figure 5 shows an embodiment of a timer circuit that checks the duration of one or more of the intervals and pulses 54. In addition to the components of Figure 3, the embodiment of Figure 5 contains a sync interrupt counter 60, a sync break end detector 64 and a ratio comparison circuit 62. Sync interrupt counter 60 has a clock input coupled to clock circuit 104, a start input coupled to start detector 34, and a stop input coupled to an output of sync interrupt end detector 64. The outputs of counter / controller 30 and sync interrupt counter 60 are coupled to ratio comparison circuit 62 which has a control output coupled to divider 32.

This embodiment addresses the problem that the minimum duration of the sync break interval 50 cannot be checked when the clock frequency is not known with sufficient precision in advance. When only small variations in bit rate are allowed, it is possible to set a threshold duration for the sync break interval 50 that is greater than the duration of a low level as a result of any normal data model even at the frequency of minimum possible clock, but less than the minimum duration of the sync interrupt for the maximum possible clock frequency. However, such a threshold duration cannot be found when too much variation in clock frequency can occur.

In the embodiment of Figure 5, the timer circuit 106 detects the presence of a sync interrupt 50 subsequently in combination with a clock frequency measurement. Synchronization interrupt counter 60 counts the number of clock pulses from clock circuit 104 in time intervals when the signal goes to low level 53, indicating that such interval could be a synchronization interruption interval 50. The counter / controller 30 counts the number of clock pulses during the sync field interval 52. Counts from sync interrupt counter 60 and counter / controller 30 are applied to ratio comparison circuit 62 which checks whether successively determined inter-account relationships from sync interrupt counter 60 and counter / controller 30 are within of a predetermined interval corresponding to a specified minimum duration of the sync break interval 50, taking into account sampling errors and clock frequency fluctuations. Only if ratio comparison circuit 62 detects such a combination does it send a signal to divider 32 to assume the divider value determined by counter / controller 30.

The relationship comparison circuit 62 may implement the comparison, for example, multiplying both counts from a combination by appropriate factors, followed by a comparison of the products. Preferably, the ratio comparison circuit 62 uses pipeline, that is, has storage elements for storing a number of successively determined counts from sync interrupt counter 60 and compares the oldest quantum (corresponding to a low signal interval preceding the end of sync field 52 by a predetermined number of sync intervals). low signal as shown in Figure 4) with the count coming from the counter / controller 30. Thus, a sync break can be detected using more recent counts from sync break counter 60 if detection fails. However, such channeled storage is not necessary, for example, when very short intervals (such as the intervals between pulses 54) can be previously eliminated as intervals 50 of synchronization interruptions based on a threshold of minimum duration, of so that the counts for these intervals do not need to be stored.

As well as setting the divider value, the timer circuit 106 in this embodiment may be arranged to generate successive firing pulses 28, as controlled by the timing interval, only after a corresponding timing break has been detected.

Although a separate sync interrupt counter 60 and a separate counter / controller 30 have been shown, it will be understood that the same counter could be used for both ways of counting, provided that storage is provided to store clock counts of the timing intervals. different interested times and to combine these counts to detect the relationship between the sync break interval 50 and the sync field interval 52.

Also, the timer circuit 106 can be constructed to perform further checks on the input signal and make the generation of the trigger pulses 28 dependent on a positive result of such a test. Thus, for example, the timer circuit 106 may check for the presence of sufficient signal level changes due to pulses 54 with the appropriate relative timing in the sync field interval 52. If such level changes are absent, synchronization break detection is suppressed, the divisor value is not updated, and no message is received.

Of course, there are many alternative embodiments of the timer circuit 106. For example, when the length of the bit periods 21 is very predictable, fixed timing of the firing pulses can be used. Other characteristics of the incoming signal can also be used to adjust the timing, for example a loop

ES 2 294 366 T3 phase lock could be used to synchronize the clock signal with the communication signal. By allowing the adaptation of the frequency of the firing pulses to the incoming signal, it becomes possible to adapt the transmission speed to the amount of data that needs to be communicated, so that the power consumption by the instruction processor 100 can be minimized. .

Figure 6 shows an example of a one bit wide operand processor that can be used as an instruction processor 100. The instruction processor 100 contains a logic unit 42, a one-bit register 40, a data memory 44, a program counter 48, and a data word memory 46. Logic unit 42 is coupled to input 14, one-bit register 40, data memory 44, program counter 48, and data word memory 46. Without deviating from the invention, more than one one-bit register 40 may be provided. The program counter 48 has an output coupled to an address input of the instruction memory 102 which, in turn, has an instruction output coupled to the logic unit 42. The data word memory 46 is coupled to the additional processor 12 (not shown). The data memory 44 can be of any type. In one example, a cyclic shift register can be used as a data memory, which shifts the stored bit addresses by one step each time a data bit is stored or each clock cycle. In this case, it may not be necessary to address data memory 44; instead, data from a predetermined address can be used. The appropriate data can be accessed using the appropriate loop in which the necessary data is placed at the predetermined address.

In operation, instruction processor 100 executes a series of instructions using one-bit operands from register 40, from input 14, and / or from data memory 44 and extracts bits to data word memory 46. (from which data words are supplied to the additional processor 12). The content of the program counter 48 addresses the instructions to be executed and is normally incremented after each instruction to address a subsequent instruction. Instruction memory 102 supplies the addressed instruction to logic unit 42. The instructions that the logic unit 42 is capable of executing include instructions to load one-bit data into register 40 from various sources, store instructions for one-bit store data, logic instructions such as AND, OR, and Exclusive OR instructions with one-bit operands from various sources, and branching instructions, which can be conditional, to change the contents of the program counter 48 by an amount specified in the branching instruction.

Instructions that are supplied from instruction memory 102 during operation in a burst 22 include an instruction to read an input bit from input 14 and an instruction to extract a bit to data word memory 46. Once all the input bits for a data word have arrived and been retrieved into data word memory 46, data word memory 46 supplies the data word to further processor 12 (not shown). Computed parity bits can be added to the data word. In principle, all the bits of the data word can be supplied from the data word memory 46 to the additional processor 12 in parallel but, of course, serial transport can be used as an alternative.

A one bit wide operand processor has the advantage that it provides the flexibility of programming at the expense of relatively small circuitry. This comes at the cost of low processing power, making it necessary to execute a relatively large number of instructions to perform specific operations compared to the number of instructions required by multibit operand processors. However, as the processing is spread over bursts 22, for each incoming bit it is only necessary to execute a relatively small number of instructions at a time in each burst 22. Thus, it is possible to process the incoming data programmatically with a data processor. one-bit operands.

Of course, the invention is not limited to the use of the one-bit operand programmable processor of Figure 6. Other types of one-bit operand programmable processors may be used or even multi-bit operand processors, although the latter will increase the complexity of the process. circuit.