Phase detector for a programmable clock synchronizer

ES 2 265 718 B2

DESCRIPTION

System and method for compensating an obliquity between a first clock signal and a second clock signal.

Priority under section 119 of title 35 of the United States code and section 1.78 of chapter 37 of the code of federal regulations

This non-provisional application claims priority on the basis of the following earlier provisional US patent application entitled: "Programmable Clock Synchronizer and Controller Arrangement Therefor", Application No: 60 / 469,120, filed March 9, 2003, in the name of from: Richard W. Adkisson, which is incorporated by reference herein.

Reference to related application (s)

This application describes a subject related to the subject matter described in the following common property patent applications co-pending: (i) "Programmable Clock Synchronizer", filed_; No. of

Application_ (File No. 200207722-2), in the name of: Richard W. Adkisson; (ii) "Controller Arrangement for a Programmable Clock Synchronizer", filed_; Application No._ (File No. 2002077231), in the name of: Richard W. Adkisson; (iii) "System and Method for Synchronizing Multiple Synchronizer Controllers", filed_; Application No._ (File No. 200207724-1), in the name of: Richard W. Adkisson;

(iv) "System and Method for Maintaining a Stable Synchronization State in a Programmable Clock Synchronizer", filed_; Application No._ (File No. 200208008-1), in the name of: Richard W. Adkisson; and (v) "Phase Detector for a Programmable Clock Synchronizer", filed_; Application No._ (File No. 200208010-1), in the name of: Richard W. Adkisson, all of which are incorporated by reference herein.

Background of the invention

Often times, digital electronic systems, for example computer systems, need to communicate using different interfaces, each operating at a speed optimized for improved performance. Typically, multiple clock signals having different frequencies are used to provide proper timing to the interfaces. Furthermore, generally the frequencies of this type of clock signal are related to each other in a predetermined way. For example, a central or system clock operating at a frequency (F_C) in particular, can be used as a master clock in a typical computer system to provide a time base with respect to a specific part of its digital circuits. Other parts of the digital circuits of the computer system (such as a bus segment and the logic circuits arranged therein) can be timed using timing signals received from the master clock, whereby the frequencies (F_D) obtained meet the relationship: F_C/F_D > 1.

Due to the asynchronous, yet related, nature of the constituent parts of digital circuits, synchronizer circuits are commonly employed in computer systems to synchronize data transfer operations across a boundary of a clock domain in order to avoid timing-related data errors. Typically, such synchronizer circuits are required to have low latency (requiring precise control of the asynchronous clocks that respectively time the circuit parts in two different clock domains). Typically, in conventional synchronizer circuit arrangements, phase locked loops (PLLs) are used to produce clocks of different but related frequencies. PLLs can have a great deal of input / output (I / O) phase jitter that results in a low-frequency phase difference, or skew, between the different clocks in the synchronizer circuits. . Therefore, it is essential to provide skew compensation between the various clocks of the synchronizer circuits.

Summary

A system and method are described that provide skew compensation in a programmable clock synchronizer to effect data transfer between first circuits arranged in a first clock domain and second circuits arranged in a second clock domain. In one embodiment of the system, a phase detector is provided for detecting a phase between the first and second clock signals. A skew state detector in communication with the phase detector is capable of operating to generate a skew state signal that tracks a phase relationship between the clock signals. A synchronizer control signal generator responds to the skew status signal by generating at least one control signal to compensate for skew between the first clock signal and the second clock signal.

Brief description of the drawings

Figure 1 represents a block diagram of an embodiment of a programmable synchronizer system for effecting data transfer across a boundary between clocks;

Figure 2 represents a timing diagram associated with the transfer of data from the circuits of the

ES 2 265 718 B2 bus clock domain to the central clock domain circuits, the domains having a frequency ratio of 5: 4, whereby the programmable synchronizer of Figure 1 can be used;

Figure 3 depicts a block diagram of an embodiment of a central clock synchronizer controller for effecting data transfer across a boundary between clocks;

Figure 4 represents a block diagram of a part of the central clock synchronizer controller of Figure 3 illustrating in more detail an embodiment of a system for compensating skew between different clocks of the synchronizer circuits;

Figure 5 depicts a schematic diagram of one embodiment of a portion of a skew state detector employed in conjunction with the teachings described herein;

Figure 6 depicts a flow chart of one embodiment of a method for compensating for skew between a first clock signal and a second clock signal;

Figure 7 depicts an embodiment of a state machine effected by a skew state detector associated with the system to compensate for skew between a first clock signal and a second clock signal having a frequency ratio of 5: 4; and Figure 8 shows a timing diagram of two clock domains having a frequency ratio of 5: 4, in which the clock signals associated with the skew state transitions of Figure 7 are illustrated in more detail.

Detailed description of the drawings

In the drawings, the same or similar elements are designated by identical reference numerals in the various views thereof, and the various elements depicted are not necessarily drawn to scale. Referring now to Figure 1, there is depicted an embodiment of a programmable synchronizer system 100 for effecting data transfer across a boundary between clocks between a first clock domain (ie, "the fast clock domain "), Which has N clock cycles, and a second clock domain (for example, the" slow clock domain "), which has M clock cycles, such that N / M> 1. Typically, M = (N-1) and, by way of exemplary implementation, the synchronizer system 100 may be provided as part of a computer system to transfer data between a faster core clock domain (e.g., operating on a signal from the 250 MHz core clock) and a slower bus clock domain (for example, operating on a 200 MHz bus clock signal), with a 5: 4 frequency ratio. Accordingly, for the purposes of this present patent application, the terms "first clock" and "central clock" will be used interchangeably with respect to a fast clock domain; similarly, the terms "second clock" and "bus clock" will be used with respect to a slow clock domain.

A phase locked loop (PLL) circuit 104 is capable of operating to generate a SINC pulse 110 and a bus clock signal 108 (designated as clock_bus) (i.e. second clock) based on a signal 106 (designated as central clock). ) of central clock (i.e. first clock) supplied to it. As will be seen below, the SYNC pulse 110 provides a reference point for coordinating data transfer operations and rises when the clock_bus and central_clock signals have matching rising edges. The two clock signals 106, 108 and the SYNC pulse 110 are provided to a synchronizer / controller block 102 that extends on either side of the boundary between clocks, between a first clock domain (i.e., the central clock domain). and a second clock domain (ie, the bus clock domain) to effect data transfer across the boundary. Reference numerals 103A and 103B refer to circuits arranged in the first and second clock domains, respectively, for example, a central clock domain logic and a bus clock domain logic, that transmit and receive data between these as provided through synchronizers 105A and 105B, which will be described in more detail hereinafter.

Each of the core_clock and bus_clock signals 106, 108 is first supplied to a respective clock distribution tree block to generate a distributed clock signal that is supplied to various parts of the synchronizer / controller block 102. Reference numeral 112 refers to the clock distribution tree capable of operating with the core_clock signal 106 to generate the distributed core_clock signal, which in Figure 1 is designated as "c" and is shown at reference numeral 106 '. Also, reference number 114 refers to the clock distribution tree 114 capable of operating with the clock_bus signal 108 to generate the distributed clock_bus signal, which in Figure 1 is designated as "b" and is shown by reference number 108 '. As one of ordinary skill in the art should readily recognize, the distributed clock signals are essentially the same as the input clock signals. Accordingly, the central_clock signal 106 and its distributed counterpart c 106 'are hereinafter treated in an equivalent manner. Similarly, also the clock_bus signal 108 and its distributed counterpart b 108 'are considered equivalent.

A SINC sampling logic block 116 is capable of operating in response to distributed clock signals 106 ', 108' and SINC pulse signal 110 to generate a pair of sampled SINC pulses that are sent to appropriate synchronizer driver circuits. In one embodiment, the sampled SINC pulses are obtained

ES 2 265 718 B2 as follows. The SINC pulse 110 is sampled twice by two flip flops (flip flop - FF) (not shown in FIG. 1) that are clocked on the rising edge of the distributed core_clock signal, c 106 '. As can be appreciated, sampling by two FF elements is effective in eliminating the metastability associated with SINC pulse 110 (possibly arising due to skew between the input signal, core_clock 106, and the output signal, SINC 110). The twice-sampled SINC pulse is designated in FIG. 1 as a "sync" signal 118, which is supplied to a first synchronizer controller 124 (or core clock synchronizer controller) operating in the first clock domain.

With respect to the second clock domain (i.e., the bus clock domain), the SINC pulse 110 is sampled in the SINC sampling logic block 116 by a single FF element (not shown in this figure) that is clocked in the rising edge of the distributed clock_bus signal, b 108 '. To indicate that the sampling is performed using the clock_bus signal, the sampled SINC pulse is designated as "sync_B" signal 120, which is supplied to a second synchronizer controller 122 operating in the second clock domain, also referred to. in figure 1 as the bus clock synchronizer controller.

The bus clock synchronizer controller 122 is capable of operating in response to the distributed bus_clock signal, b 108 ', and the sampled sync_B pulse 120 to generate a plurality of synchronizer control signals, a portion of which is directed to a first synchronizer circuit means 105A, which operates to control the transfer of data from first circuits 103A (i.e. the core clock domain logic) to a few second circuits 103B (ie, the bus clock domain logic). Reference numeral 132 refers to the signal path of this portion of the control signals originating from the bus clock synchronizer controller 122. Another portion of the synchronizer control signals generated by the bus clock synchronizer controller 122 are directed (via signal path 134) to a second synchronizer circuit means 105B, which operates to control the transfer of data from the second circuits 103B to the first circuits 103A. In accordance with the nomenclature used in the present patent application, the first and second synchronizer circuits may also be referred to as center-to-bus synchronizer and bus-to-center synchronizer circuits, respectively. In addition, the bus clock synchronizer controller 122 also generates a set of control signals between controllers that are supplied to the first synchronizer controller 124 (i.e., the center clock synchronizer controller), so that both controllers can work together. . Reference numeral 128 refers to the signal path of the inter-controller clock ratio control serial (s) that is (are) provided to the central clock synchronizer controller 124.

Similar to the operation of the bus clock synchronizer controller 122, the core clock synchronizer controller 124 is capable of operating in response to the distributed core_clock signal, c 106 ', to the control signals between controllers and to the sampled sync pulse 118. to generate a plurality of synchronizer control signals, a part of which is directed to the first synchronizer circuit means 105A and another part of which is directed to the second synchronizer circuit means 105B. Reference numerals 138 and 140 refer to corresponding signal paths relative to these control signals. The central clock synchronizer controller 124 also generates data transmission / reception control signals that are supplied to the central clock domain logic 103A via signal path 136 so that the central clock domain logic 103A core clock knows when it can send data to bus clock domain logic 103B (i.e. valid transfer operations) and when it can receive data from the bus clock domain logic 103B (i.e., valid receive operations).

All control signals from the bus clock synchronizer controller 122 for the first and second synchronizers 105A, 105B are passed through one or more FF elements which are clocked with the distributed bus_clock signal, b 108 '. Also, the control signals from the central clock synchronizer controller 124 are passed through a series of FF elements timed with the distributed central clock signal, c 106 ', before being supplied to the various parts of the synchronizer system 100. Accordingly, as will be seen in more detail later, the various control signals associated with the synchronizer system 100 may be designated with a signal tag that is concatenated with a suffix "_ff" or "_ff_B" to indicate the registration process by the distributed central_clock signal or by the distributed clock_bus signal.

A phase detector 130 detects the phase differences (ie, skew) between the two clock signals by operating in response to the sampled clock_bus and core_clock signals. This information is provided to the central clock synchronizer controller 124, which can compensate for skew or determine appropriate moments to coordinate with the bus clock synchronizer controller 122.

If the bus clock signal is stable with respect to the SINC pulse, the inter-controller clock ratio control signals are generated by the bus clock synchronizer controller 122, which provide information regarding the frequency ratio of the controllers. first and second clock signals, the clock sequence information and the SINC delay, which are transmitted to the center clock synchronizer controller 124 for synchronization of its center clock signal accordingly. On the other hand, if the center clock signal is stable with respect to the SINC pulse, the control signals of the clock ratio between controllers are generated by the center clock synchronizer controller 124 for transmission to the clock synchronizer controller 122. so that both synchronizer controllers can be properly synchronized. In addition, a configuration interface 126, designated in Figure 1 as Config_SINC, is provided as part of the programmable synchronizer system 100 to configure the central clock synchronizer controller 124 so that it can be programmed for different

ES 2 265 718 B2 skew tolerances, skew latencies and modes of operation In one embodiment, the configuration interface 126 may be implemented as a register having a plurality of bits. In another embodiment, a memory-based setting may be provided, eg, settings stored in an EPROM, such as a SINC configuration interface.

Additional details regarding the various subsystems described hereinbefore can be found in the following commonly pending patent applications co-pending: (i) "Programmable Clock Synchronizer", filed_; Application No._ (File No. 200207722-2), in the name of: Richard W. Adkisson; (ii) "Controller Arrangement for a Programmable Clock Synchronizer", filed_;

Application No._ (File No. 200207723-1), in the name of: Richard W. Adkisson; (iii) "System and Method for Synchronizing Multiple Synchronizer Controllers", filed_; Application No._ (File No.

200207724-1), payable to: Richard W. Adkisson; (iv) "System and Method for Maintaining a Stable Synchronization State in a Programmable Clock Synchronizer", filed ____; Application No. ____ (File No. 2002080081), in the name of: Richard W. Adkisson; and (v) "Phase Detector for a Programmable Clock Synchronizer", (Phase Detector for a Programmable Clock Synchronizer) presented_; Application No._ (File No.

200208010-1), payable to: Richard W. Adkisson, all of which are incorporated by reference herein.

As discussed above, the timing system 100 can be programmed for different skew tolerances and latencies so that high speed data transfer can appropriately take place even when there is a high skew or low latency requirement. In addition, the synchronizer system 100 can operate with either of two clock domains having a ratio of N first clock cycles to M second clock cycles, where N / M> 1. For illustrative purposes, the following is detailed below. operation of an embodiment of the programmable synchronizer system 100 to transfer data from the bus clock domain to the central clock domain, the clock domains having a frequency ratio of 5: 4.

Figure 2 represents a timing diagram 200 of two clock domains having a frequency ratio of 5: 4, in which the programmable synchronizer system of Figure 1 can be used to effect data transfer across the boundary between clocks from the bus clock domain circuits to the core clock domain circuits. In particular, Figure 2 illustrates the temporal relationship of the various control signals associated with the synchronizer system 100 of Figure 1 and the effect of different skew tolerances and latencies. A cycle count 202 refers to the cycle numbering of the core_clock signal in a particular timing sequence. Two sequences [A, B, C, D] and [A2, B2, C2, D2] of bus data 204 are illustrated, each block having a width of k bits and being available for a particular clock cycle of 0 to 3. Different skew tolerance and latency factors can be programmed and, in particular, in a 5: 4 mode, for example, a multiplexer register block from a bus synchronizer circuit to the exchange (not shown), which is timed by the central clock, it can fetch data five times, but since only four data transfers can come from the bus domain, only four will be used (the extra cycle having an unused data part, marked with an X on Panels 206A-206C). Additional details on the data capture and load control functionality of a bus clock synchronizer circuit to the exchange by way of example can be found in the aforesaid co-pending US patent application entitled "Programmable Clock Synchronizer" , filed ____ Application No.____ (File No. 200207722-2), in the name of: Richard W. Adkisson.

In Panel A 206A, the transfer of data from the bus domain circuits is shown, the bus data being loaded, to be supplied as the data b0_ff 208A and b1_ff 208B, through a pair of multiplexer register blocks, in central domain circuits, such as captured data output 210 central_ff, where a condition is programmed involving a skew tolerance of 0.25 and an added latency of 0.625. The skew tolerance, which in this case is measured in center clock cycles, is defined as the minimum distance between data sample (ie, central_ff 210) and changing data input (ie, b0_ff 208A or b1_ff 208B). Added latency is also measured in core clock cycles, obtained by averaging the values ​​associated with the four data blocks (from the start of data entry, that is, b0_ff or b1_ff to core_ff). The actual latency is determined as one cycle of the clock_bus signal plus the added latency, which in 5: 4 mode translates to 1.25 cycles of the core_clock signal plus the added latency.

As shown in Panel A 206A, which illustrates the best latency condition but with the worst skew tolerance, the central clock synchronizer controller 124 generates the signal 212 b2c_valid_ff, so there is no valid receive operation during cycle 0 of the central_clock signal (that is, its first cycle). The output, that is, central_ff 210, includes block [A] of data from b1_ff 208B, then block [B] of data from b0_ff 208A, then block [C] of data from b1_ff 208B, and then , again the block [C] of data (in cycle 0 of the second sequence of the central_clock signal, which is the extra cycle not used, thus giving rise to the invalid block C or XC of data), and finally , the data block [D] of b0_ff: 208A. Since the valid block [C] was loaded into central_ff 210, coming from b1_ff 208B, 0.25 cycles of the central_clock signal after it was loaded by b1_ff 208B, the skew tolerance is 0.25 cycles of the central_clock signal.

Panel B 206B of FIG. 2 illustrates the programming mode with the next best latency condition (added latency = 0.875) having the next best skew tolerance (= 0.5 core clock signal cycles). Under these conditions, the core clock synchronizer controller 124 generates valid_ff_bac 212 so that it is reduced in the fifth cycle of the core clock signal (ie, cycle 4). The output, that is, central_ff 210, includes

ES 2 265 718 B2 block [A] of data from b1_ff 208B, then block [B] of data from b0_ff 208A, and again block [B] of data that is not used (in cycle 4 of the first sequence of the central_clock signal, which is the extra unused cycle, thus giving rise to block B or XB of invalid data), then block [C] of data from b1_ff 208B, and finally, block [ D] of data from b0_ff 208A. Since the valid block [B] was loaded into central_ff 210, from b0_ff 208A, 0.5 cycles from the central_clock signal after it appeared at b0_ff 208A, the skew tolerance is 0.5 cycles from the central_clock signal.

The programming mode with the worst latency (= 1.125) and the best skew tolerance (= 0.75 cycles of the core_clock signal) is shown in Panel C 206C of Figure 2. The core clock synchronizer controller 124 generates bac_valid ff 212 so that it is decremented in the fourth cycle of the central_clock signal (ie cycle 3). The output, that is, central_ff 210, includes block [A] of b1_ff 208B (in cycle 2 of the first sequence of the central_clock signal), and again the block [A] of data that is not used (in the cycle 3 of the first sequence of the central_clock signal, which is the unused extra cycle, thus giving rise to block A or XA of invalid data), and then block [B] of data from b0_ff 208A, then block [C] data from b1_ff 208B, and finally the block [D] of data from b0_ff 208A. Since the valid block [A] was loaded into central_ff 210 from b1_ff 208A, 0.75 cycles from the central_clock signal after appearing at b0_ff 208A, the tolerance is 0.75 cycles from the central_clock signal. As noted above, the added latency is the average of the time (in cycles of the central_clock signal) from b0_ff or b1_ff to central_ff for all data used. Therefore, no latency value is displayed anywhere in the data with an X.

Based on the above discussion, it should be appreciated that the embodiment of the synchronizer of the present invention can be programmed for different latencies and skew tolerances, for data transfer across a clock boundary between any two clock domains that have a Known N: M ratio (eg, M = N-1). However, it should be noted that regardless of the programmed latency and skew tolerance, the center clock may lag sufficiently behind the bus clock that the coincident edges shift to the next edge of the bus clock. Alternatively, the center clock can go far enough ahead of the bus clock that the coincident edges are offset to the leading edge of the clock. The teachings described herein compensate for a variably large skew between the center clock signal and the bus clock signal, for example, greater than a difference of one clock period between the center clock signal and the bus clock signal. bus. Furthermore, as will be explained in more detail later herein, the teachings described herein can compensate for an infinite amount of skew.

Figure 3 depicts one embodiment of a central clock synchronizer 124 for effecting data transfer across a boundary between clocks. The central clock synchronizer comprises several interconnected logic components, including a synchronizer ratio (sync) sampler block 300, a sequence sampler block 302, a precision sequence detector block 304, a sincb0 sampler block 306, a detector block 308 of synchronizer pulses, a stable state detector block 310, a cycle and sequence generator block 312, a skew state detector block 314, and a synchronizer control signal generator block 316. As set forth in more detail in co-pending US patent application entitled "Controller Arrangement for a Programmable Clock Synchronizer," filed_; Application No._ (File No. 200207723-1), in the name of: Richard W. Adkisson, various clock ratio control signals between controllers, namely, sync_ratio_B 320, sequence_B 322, and syncb0_B 332 are provided as inputs to the central clock synchronizer controller circuits from the corresponding bus clock synchronizer controller. As further described herein, these control signals between controllers are used in conjunction with timing setup information supplied through the SINC setup interface 126 (shown in Figure 1) to generate additional internal control signals. within the central clock synchronizer controller, to carry out the functionality of the various constituent modules thereof. Accordingly, only certain salient features of the center clock synchronizer controller 124 will be described below.

Synchronizer ratio sampler block 300 generates an M-bit wide sync_rate signal 318 by sampling M-bit wide sync_rate_B signals 320 from the bus block domain. The sequence sampler block 302 samples signal 322 sequence_B at the rising edge of the center clock to produce a signal 324 sequence_ra. Additionally, sequence sampler block 302 samples signal 322 sequence_B at the falling edge of the center clock to produce a signal 326 sequence_rd. The precision sequence detector 304 generates a signal 328 state_sec and a signal 330 sequence in response to the signal 324 sequence_ra and the signal 324 sequence_rd. The core clock synchronizer controller 124 synchronizes a sincb0B signal 332 using the sincb0 sampler block 306, which produces a sincb0_ra signal 334 and a sincb0_rd signal 336 using a similar sampling technique. Synchronizer pulse detector block 308 generates a sync_border signal 338 in response to a sync signal 340, eg, sync 118 provided by the SINC sampling logic 116 (shown in FIG. 1).

As will be discussed in more detail hereinafter, the central clock synchronizer controller 124 employs the precision sequence detector 304, the steady state detector 310, the cycle and sequence generator 312, and skew state detector 314 to provide use of the entire skew range in modes where the skew tolerance is greater than one-half of the central clock and where skew between clocks cannot initially be counted on. central and bus is less than half

ES 2 265 718 B2 of the central clock. The stable state detector block 310 receives the sync_ratio signal 318 provided by the sync ratio sampler block 300, a config_sinc signal 342 provided by the synchro configuration interface 126 of FIG. 1, a sync_locked signal 344, and a pd_c signal 346 provided by the skew state detecting block 314, and a cycle signal 348 and a cycle_has_loaded signal 350 provided by the cycle and sequence generator 312. Based on the above input signals, the steady state detector block 310 generates a steady_synchronizer signal 352 that can be transmitted to the core clock domain logic circuitry 103A (shown in FIG. 1). A steady-state signal 354 is also generated which is used internally to generate other internal control signals of the central clock synchronizer controller circuits.

Cycle and sequence generator block 312 receives signal 318 sync_relation from synchronizer ratio sampler block 300, signal 342 config_sinc from synchro configuration interface 126 of FIG. 1, signal 354 stable_state from block 310 stable state detector, signals 324 and 326 sequence_ra and sequence_rd from sequence sampler block 302, signal 338 sync_borders from synchronizer pulse detector block 308, signal 356 skew state from block 314 skew state detector, signal 330 sequence from block 304 precision sequence detector, signals 334 and 336 sincb0_ra and sincb0_rd from the sincb sampler block 306, and the signals 358 and 360 pd_b_ra and pd_b_rd from the phase detector block 130 of FIG. 1. In response to the input signals, cycle and sequence generator 312 asserts signal 350 cycle_has_loaded, signal 348 cycle, and signal 362 sequence.

As illustrated, skew state detector 314 receives signal 318 sync_rate from synchronizer ratio sampler block 300, signal 342 config_sinc from synchro configuration interface block 126 of FIG. 1, signal 354 stable_state from the steady state detector 310, the signal 348 cycle from the cycle and sequence generator 312, signal 338 sync_borders from synchro pulse detector 308, signals 358 and 360 pd_b_ra and pd_b_rd from phase detector 130 of FIG. 1, and signal 328 state_sec from precision sequence detector 304. In response to the received signals, skew state detector 314 asserts signal 344 blocked sync, signal 346 pd_c, and signal 356 skew_state.

Synchronizer control signal generator block 316 receives synch_rate signal 318 from synchro ratio sampler block 300, synchro config signal 342 from synchro configuration interface 126, cycle and sequence signals 348 and 362 from block 312 loop and sequence generator, and signal 356 skew_state from skew state detector block 314. In response to the input signals, the generator control signal generator block 312 asserts a signal 362 c0_sel, a signal 364 c1_sel, a central signal 366 sel, a signal 368 bac_valid, a signal 370 cab_valid, and a signal 372 cab_valid_m. . In the foregoing co-pending US patent application entitled "Controller Arrangement for a Programmable Clock Synchronizer", filed_; Application No._ (File No. 200207723-1), in the name of: Richard W. Adkisson, additional details regarding signs 362-372 can be found.

FIG. 4 depicts a logic portion 400 of the central clock synchronizer controller 124 of FIG. 3 for the purpose of highlighting in more detail one embodiment of a system that provides skew compensation. The phase detector block 130 is capable of operating to sample the second clock signal using the first clock signal and enforces signal 358 pd_b_ra and signal 360 pd_b_rd. In the aforesaid, co-pending US patent application entitled "Phase Detector for a Programmable Clock

Synchronizer ”, (Phase Detector for a Programmable Clock Synchronizer) presented_; Application No._ (File No. 200208010-1), payable to: Richard W. Adkisson, additional information on the phase detector can be found. Signal 358 pd_b_ra and signal 360 pd_b_rd are received in digital logic portion 400 of central clock synchronizer controller block 124 by skew state detecting block 314, which is located in communication with phase detecting block 130. The skew state detecting block 314 determines a skew state signal, that is, the skew state signal 356 capable of operating to track a phase relationship between the first and second clock signals, which the control signal generator block 316 used to generate a plurality of synchronizer control signals (for example, control signals 402) at particular times that compensate for the difference in skew between the clock signals. In particular, when the core clock synchronizer controller block 124 components are in an infinity mode, the system described herein can provide skew tolerance and compensation, even over a full core clock period or more. , between the first clock signal and the second clock signal.

More specifically, with respect to the operation of the skew state detecting block 314, the skew state detector block 314 employs a variety of signals in combination with the pd_b_ra signal 358 and the pd_b_rd signal 360 to generate the skew-state signal 356. In particular, the synchronization configuration interface block 126 of FIG. 1 supplies the signal 342 config_sinc to the skew state detector block 314 in order to establish the different latencies, modes of operation, and skew tolerances. For example, the 342 config_sinc signal can be used to set the skew tolerance in 0.75 mode, as previously described in connection with Figure 2. Additionally, the obliquity state detector block 314 receives the signal 348 cycle from the block 312 generator of cycles and sequences, the signal 318 ratio_sinc from the block 300 sampler of synchronizer ratios, the signal 328 state_sec from the block

ES 2 265 718 B2

304 precision sequence detector, signal 338 sync_borders from synchronizer pulse detector block 308, and signal 354 steady-state from stable state detector block 310. Using the aforementioned signals, the skew state detector block determines the skew state by determining the position of the coincident edges of the bus clock and the central clock relative to the bus clock. The skew state is treated as a "C state" by detecting the matching, rising edges of the bus clock and center clock at the zero point, ie, cycle 0 of the bus clock timing window. If the rising edge of the central clock is detected to lag behind the rising edge of the bus clock, then the skew state is a positive skew state. For example, if the rising edge of the central clock is a quarter cycle lag from the bus clock, then the state is P1, that is, plus one. Similarly, if the rising edge of the central clock is half a cycle ahead of the bus clock, then the state is M2, that is, minus two. Once the central clock signal is ahead or behind the bus clock by a full bus clock period, the skew state detector returns the skew state to its original state, C. In this way, you can an arbitrarily large and potentially infinite amount of skew be traced and compensated for.

In one embodiment, when the correct phase is being detected for the first time, the skew state detector block 314 may not initially employ the phase detector block 130 of FIG. 1, since a jagged effect (aliasing) may be present. . For example, with the frequency ratio of 5: 4, the central clock signal behind the bus clock signal by one quarter of the central clock is identical to the central clock ahead of the bus clock signal. three-quarters of the central clock. Thus, initially, when the stable_state signal 354 is not fully enforced, the change (plus or minus) of state is only detected in one cycle when the synchronizer pulse detector block 308 detects the edge and the phase detector block 130 detects a change, or if the synchronizer pulse detector block 308 detects that the edge has moved to another clock. After the signal is blocked, the change, more or less, is detected in cycle 0 if the phase detector block 130 detects a change or if the synchronizer pulse detector block 308 detects a large edge movement (for example, two clocks ). In one embodiment, to avoid stability problems due to time lag, signal 356 skew_state only changes if it has been in the same state for at least two cycles. After two stability cycles, for example, if a change in the skew state has been detected, then the change is stored but only implemented in the last sequence.

More specifically, with respect to the operation of the synchronizer control signal generator block 316, the synchronizer control signal generator block 316 employs a variety of signals to generate the control signals 402, which include signal 362 c0_sel, the signal 364 c1_sel, signal 366 central_sel, signal 368 bac_valid, signal 370 cab_valid and signal 372 cab_valid_m, sent to the synchronizer circuits including the center-to-bus synchronizer 105A and the bus-to-center synchronizer 105B. As previously alluded to, in the aforementioned pending US patent application, entitled "Programmable

Clock Synchronizer ”, presented_; Application No._ (File No. 200207722-2), in the name of: Richard

W. Adkisson, additional information can be found on the control signals 402. However, one of ordinary skill in the art should recognize that other types of synchronizer controllers generating different control signals may be employed to practice the invention disclosed herein.

Still referring to synchronizer control signal generator block 316, in addition to signal 356 status_obliquity, synchronizer control signal generator block 316 receives signal 342 config_sinc from synchronizer configuration interface 126, signal 318 sync_relation from synchronizer ratio sampler block 300, and the cycle signal 348 and the sequence signal 362 from the cycle and sequence generator block 312. The synchronizer control signal generator block 316 decodes the sync ratio 318, the config_sinc signal 342, the cycle signal 348, the sequence signal 362, and the signal 356 wobble_state to initiate the control signals 402 at the appropriate times.

For example, for a frequency ratio of 5: 4, that is, signal 318 sync ratio = 5: 4, when the skew state equals C, that is, signal 356 skew_state equals C, generator block 316 of synchronizer control signals enforces the pattern "tol skew = 0.75", in which the 368 bac_valid signal is enforced reduced in cycle 3. However, when signal 356 skew_state = P1, synchronizer control signal generator block 316 enforces signal 318 bac_valid reduced in cycle 4. When signal 356 skew_state = P2, synchronizer control signal generator block 316 Synchronizer asserts reduced signal 318 bac_valid reduced in cycle 0. When signal 356 skew_state = M1, synchronizer control signal generator block 316 asserts signal 318 bac_valid reduced in cycle 2. Signal 370 valid_cap performs a similar progression from cycle 1 to cycle 2 and finally back to cycle 2. cycle 1. In addition, signal 362 c0_sel, signal 364 c1_sel, and signal 366 central_sel are compensated in a similar manner to allow a skew tolerance of 0.75 center clock cycles in the new skew states. In one embodiment, the alternating states represented by signal 362 c0_sel and signal 364 c1_sel change relative to signal 370 cab_valid, and the value of central signal 366 sel changes relative to the value of signal 370 cab_valid. Furthermore, the value of signal 372 cab_valid_m can be viewed as an early indication of the value of signal 370 valid_ca and the various transitional states, for example C_P1.

FIG. 5 depicts an embodiment of a portion of a skew state detector 500 employed in conjunction with the teachings described herein. Phase detector 130 asserts signal 358 pd_b_ra and signal 360 pd_b_rd, which are received by a first circuit part 502 that determines coincident edges.

ES 2 265 718 B2

The first part 502 of the circuit includes a series of three registers that sample the 358 pd_b_ra signal, and a series of two registers that sample the 360 ​​pd_b_rd signal. The two sampled signals are cross-fed to a pair of AND gates (AND) whose outputs are provided to an OR gate (OR). The first part 502 of the circuit is able to function to detect the first edge, which is a 1-to-0 transition in the rising signal, that is, the 358 pd_b_ra signal, and a 0-to-1 transition in the falling signal , that is, the 360 ​​signal pd_b_rd. When it detects a current condition (either a 0 on the rise, or a 1 on the descent) and the previous two conditions (1 on the rise and 0 on the descent), the first part of the circuit asserts a signal indicative of the coincident edge detected to a second part 504 of the circuit that determines the skew state and associated signaling.

More specifically, within the second circuit portion 504, a series of registers 506 operates to provide a plurality of taps to a first set of MUX blocks 508. The skew state signal 356 provides control to the MUX blocks 508, which determine the skew state transition for each ratio. Once the skew state transition has been determined, a second set of MUX blocks 510 controlled by sync_rate signal 318 determines the appropriate skew transition that corresponds to the timing ratio of the clock signals employed. It should be appreciated that only a portion of the second circuit portion 504 is depicted. In particular, an embodiment of the second part 504 of the complete circuit would include a MUX block 510 for each skew transition (ie, more, less, or none) and a MUX block 508 for each frequency ratio. As illustrated, 510 MUX blocks are shown for each of the illustrated skew pd_c (none) and pd_p1 (plus one) transitions, and 508 MUX blocks are shown for each frequency ratio, 5: 4 and 4: 3 . Also, MUX blocks 510 and 508 are provided with respect to other transitions, eg, pd_p2 (plus 2), pd_m1 (minus 1), and pd_m2 (minus 2).

During operation, the second circuit portion 504 of the skew state detector block 314 asserts the signal 346 pd_c when the phase detector block 130 detects coincident rising edges of the bus clock and central clock at the zero point, i.e. , the position in which the synchronizer pulse detector block 308 establishes that the matching edge is positioned. With signal 342 config_sinc set to infinity mode, signal pd_c is active when signal 356 skew_state compensates for skew.

Figure 6 depicts a method of compensating for skew between a first clock signal and a second clock signal. In one embodiment, this method can be practiced in conjunction with a phase detector that is capable of operating to sample one clock (eg, a second clock signal) using another clock (eg, a first clock signal), to determine a phase difference between them. The method begins at block 600, in which the position of the coincident edges relative to the first clock signal and the second clock signal is determined. The matching edges can be either matching rising edges or matching falling edges. At block 602 a determination is made as to whether and if a skew transition is necessary and, if so, by how much, which is based on tracking the phase relationship between the clock signals. In response to the determination at block 602, the transition from the current skew state to a new skew state is effected, for example, in a state machine (block 604). Then, at block 606, a signal indicative of the new skew state is generated, which the controller circuits employ to appropriately adjust the output of their synchro control signals, thus compensating for skew between the first and second clock signals. clock sign. One of ordinary skill in the art should appreciate that the present method can provide compensation for skew ranging from 1/8 of a cycle to a full clock period or more.

Figure 7 depicts an embodiment of a state machine 700 effected by the skew state detector associated with the system to compensate for skew between a first clock signal and a second clock signal for a frequency ratio of 5: 4. Referring to the state machine 700 transition state diagram, the bold ovals illustrate the states, P1, P2, M1, M2, and C, which, in turn, represent multiples of a quarter of the skew of the central clock. . In particular, state P1 (plus 1) represents +1/4 of the skew of the clock, state P2 (plus 2) represents +1/2 of the skew of the clock, state M1 (minus 1) represents -1 / 4 of the clock skew, the M2 (minus 2) state represents -1/2 of the clock skew and the C (zero) state represents 0 of the clock skew. As described above, the skew state is C when coincident, rising edges of the bus clock and center clock are detected at the zero point, that is, cycle 0 of the bus clock timing window. If the rising edge of the central clock is detected to be lagging behind the rising edge of the bus clock, then the skew state is a positive skew state, such as P1 or P2. On the other hand, if the rising edge of the central clock is detected to be ahead of the rising edge of the bus clock, then the skew state is a negative skew state, such as M1 or M2, depending on the amount in the skew. that the rising edge of the central clock is ahead of the rising edge of the bus clock. Ovals, such as C_P1 and M2_M1, illustrate intermediate transitional states. For example, the C_P1 transition indicates a positive transition from the C state to the P1 state, and the M1_M2 transition indicates a negative transition from the M1 state to the M2 state. The skew state detector 314 dynamically detects, determines, and tracks the skew state in order to compensate for the phase difference between the core clock and bus clock signals. Furthermore, in order to provide an infinite amount of skew tolerance, the skew state detector provides for the transition from the skew state back to C when a full skew clock period is detected.

Figure 8 depicts a timing diagram of two clock domains having a frequency ratio of 5: 4, illustrating in more detail one embodiment of the skew state transitions of Figure 7. The 810 count of cycles refers to the numbering of the cycles of the clock_bus signal in a sequence of tempori9

ES 2 265 718 B2 particularization. The central clock signal 106 'and the bus clock signal 108' are illustrated in a time period represented by a series of panels, i.e., Frame A 802, Frame B 804, Frame C 806, Frame D 808 and Frame E 810. The skew status 812 of the system in each panel 802-810 is indicated to the right of the panel. For example, in Frame A 802, the skew state 812 is C, and in Frame D 808, the skew state is M1. The coincident edges 814 (bc) indicate the coincident rising edges of the center clock signal 106 'and the bus clock signal 108'. As illustrated, in Frame A 802 m, the skew state 812 is equivalent to C since the coincident edges 814 are in cycle 0. In Frame B 804, when the central clock is behind the clock bus on 1/4 center clock, the skew state passes from C to P1 through a C_P1 transition. In this panel, the coincident edges 814 are located on the rising edge of the second cycle, that is, cycle 1. As illustrated in Frame C 806, as the central clock lags further back (i.e. 1 / 2 of the skew of the central clock), the coincident edges 814 are located at the rising edge of the third cycle, that is, cycle 2. At this time, the skew state 812 at P2, or two more. During Frame D 808, the central clock is delayed with respect to the bus clock by another quarter of a cycle, so that the skew state 812 goes to M1, which is equivalent to P3 in a frequency ratio synchronization scheme. 5: 4, through a P2_M1 transition. In Frame E 810, an additional skew difference (ie, 1/4 cycle more) causes the skew state to pass from M1 to C, through the M1_C transition. At this time, a full central clock period of skew is present and the skew state has returned to the skew state C again. As will be appreciated, this could occur an arbitrarily large number of times. Therefore, although the amount of skew can be arbitrarily large or infinite, the skew can be tracked and compensated.

As mentioned above, Figures 6 and 8 have represented a method to compensate for the skew between two clock domains, that is, between the said first clock signal and the second clock signal, and a timing diagram of two clock domains, such that said first clock signal and said second clock signal are spaced at least a quarter of a cycle apart, that is, 1/4 of the skew of the central clock.

Although the invention has been particularly described with reference to certain illustrations, it should be understood that the forms of the invention shown and described are to be treated only as exemplary embodiments. Various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention as defined in the appended claims.