RF receiver AGC incorporating time domain equalizer circuity

DESCRIPTION

Scope.

The present invention is generally oriented to the field of electronics and more specifically to automatic gain control circuits. Even more specifically, it is aimed at automatic gain control circuits used in relation to radio receivers with quadrature amplitude modulation that incorporate equalization in the time domain. Background.

If an equalizer is used in the time domain in a radio receiver such as a quadrature amplitude modulation (QAM) radio, an automatic gain control circuit is typically already incorporated within the equalizer in the time domain. According to the state of the technique, the solution for automatic gain control for the entire circuit was to detect the signal, in the form supplied to the downward frequency converter and finally the equalizer in the time domain, and filter this signal in a band pass filter, detect it, linearize it, filtered in a low pass filter, perform a threshold detection, linearize it and feed back the resulting signal as a control tendon to a variable gain amplifier. The low pass filter, the detector, and the linearizer detector can be eliminated using the signal already existing in the equalizer in the time domain for both the stabilization of the amplitude of the equalization signal in the time domain and for the control of Global gain of the traditionally used variable gain amplifier. This automatic gain control signal may come from one of the automatic gain control circuits used for each of the signals in phase or quadrature, or it may be a combined signal derived from the phase and quadrature signals. In any case, the complete circuit is considerably simplified and in addition, the almost constant amplitude signal that appears in the A / D converter reduces the possibility of errors and the complete circuit adapts easily to changes in RF bandwidth and base band

It is therefore an object of the present invention to achieve an improved automatic gain control circuit.

Other objectives and advantages of the present invention will be deduced from the reading of the specification and claims together with the drawings in which:

- Figure 1 is a block diagram of the circuit according to the state of the technology incorporating an automatic gain control in equalization in the time domain;

- Figure 2 is a block diagram of the present invention that obtains the same final result as that provided by Figure 1, but with improved reliability and accuracy under marginal conditions;

- Figure 3 shows more details of a part of the equalizer in the time domain of Figure 2; Y

- Figures 4 and 5 are used to explain the operation of the equalizer parts in the time domain of Figures 2 and 3. Detailed description of the invention.

In Figure 1 an input signal 10 is applied to a variable gain amplifier 12 whose output 20 feeds a phase 14 mixer, a quadrature phase mixer 16 and a separator amplifier 18. This input signal can be RF , IF or baseband according to the equalization requirements of a given application. The output of the phase 14 mixer feeds a baseband filter 22 which in turn feeds an equalizer block in the time domain 24 that obtains a set of digital output senaks 26. The quadrature phase mixer output senaks 16 feed a baseband filter 28 which in turn feeds a second equalizer input in the time domain 24. The signals from the separator amplifier 18 pass through a bandpass filter 30, a detector 32, a linearizer detector 34, a low pass filter 36, a threshold detector 38 and a linearizer amplifier 40 to a control input of the amplifier variable gain 12.

An automatic gain control circuit of this type, for use in RF systems, is described in more detail in many references of the state of the art such as Microwaves and RF, August 1989, pages 85-93. Although the circuit shown in the referenced article is not configured exactly as shown in Figure 1, it illustrates that many of the components shown are of the standard type.

In Figure 2 an RF / IF input signal feeds input 50 of a variable gain amplifier 52 whose output 54 feeds a phase 56 mixer and a quadrature phase mixer 58. An output signal from the phase 56 mixer feeds, through a baseband filter 60, a first input of an analog-digital (A / D) converter and an equalizer in the time domain 62, while a signal from Quadrature phase mixer output 58 feeds, through a baseband filter 64, to a second equalizer input in the time domain 62. Block 62 has a set of digital output senaks designated by 66 and has an automatic gain control output 68 that is connected to the input of a separating amplifier 70. The output of the separating amplifier 70 is fed by means of a low pass filter 72, a threshold detector 74 and a linearizer amplifier 76 to a control structure of the variable gain amplifier 52.

The equalizer in the time domain 62 of Figure 2 is divided into two parts, the top part being in charge of the phase senaks and the bottom part being in charge of the quadrature phase senaks. Figure 3 shows a block diagram of one of the two parts of block 62 in which a signal 80 from one of the filters feeds an adder circuit 82 whose output feeds an analog-digital converter 84. Block 84 provides a plurality of senaks to a combinational laser circuit 86. The digital inputs provide an output 88 to an integrator 90 with a laser value dependent on the digital inputs. In other words, it provides a logical "0" when the input signal is

056 743 less than a reference value and a logical "1" when it is higher. These signals adjust the output of the integrator in a feedback way. The output of integrator 90 is set as 92 and is an automatic gain control voltage. Blocks 86 and 90 comprise a signal detector for this section of the equalizer in the time domain. Signal 92 feeds the implied section of the equalizer in the time domain, the equalizer being in the time domain designated as 94. The equalizer in the time domain 94 supplies the automatic gain control signals, to the connection of the connection. 96, to a second entry of adder 82. Connection 92 could be the same as connection 68 in Figure 2, but Ι0.> Ηο.ιιι <ίιΙ <', the automatic gain control signals of the upper and lower sections of the equalizer in the time domain are combined in a way that effectively comprises a central or average stage of the two senates and this average is used as a feedback signal through connection 68. The automatic gain control of the equalizer in the time domain 62 provides only, for each of the sections, a comparatively limited range of adjustment of the input signal 80.

Figure 4 is a representation of a constellation of a quadrature amplitude modulation of value sixteen, the sixteen data positions being coded as words two bits for each of the senates in phase and quadrature. As illustrated, the lower left corner of the constellation receives the designation 00 and represents the two most significant bits that are supplied to the combinatorial block Ioóíco 86.

d2 dl d0 Level

0 0 +3

0 1+2 0 10+1 0 11+0 10 0-0 10 1-1 110-2 111-3

Table 1

Table 1 illustrates how each of the sixteen data positions in Figure 4 are further divided into eight more levels. In this way, the complete constellation is divided into a five-bit representation of 32 levels in each of the addresses in phase (I) and phase in quadrature (Q). The nominal position for the data was at levels +0 and -0. All other levels are considered erroneous with respect to the nominal levels, but are not considered data bit errors.

The time domain equalizer uses these error levels to determine the necessary correction factors and therefore, the automatic gain control information. Figure 5 is a summary of the data in Table 1, as indicated above. If only the Q dimension is observed, the +0, +1, +2 and +3 levels should be considered as positive error levels. Levels -0, -1, -2 and -3 should be considered as negative error levels. Above axis I, the positive error levels would correspond to a signal above the nominal reception level and negative error levels would correspond to a signal below the nominal reception level. Below the axis I, the opposite is true. The combinational loóíca block 86 includes lóoíca to determine if a signal is greater or less than a nominal level and then sets an Ioóico "1" if it is greater than the nominal one and an Ioóico "0" if it is smaller. This signal is supplied, through connection 88, to an integrator 90 where it is converted to an anti-beam voltage that represents the relative level of the signal entering the A / D converter. This voltage is used in the feedback loop represented by connection 92, the equalizer in the time domain 94 and the connection 96 to control the equalizer in the time domain and to supply the detector voltage to control the automatic control loop of gain shown in figure 2.

As will be understood, a similar set of senates in dimension I or in phase will also be required to specify which of the columns was being detected at a given time. The Q dimension can only define the specific row. The combination of these two signals defines, therefore, which of the 16 data positions is treated at any given time.

Functioning.

In the state of the spring to stabilize the level of the senates that appear in connection 10 of Figure 1, whose amplitude varies strongly, a gain control circuit is used. It may be a variable gain or a variable attenuator, but it necessarily has to be something similar to Figure 1. In this way the level of the signal in connection 20 is relatively stable compared to the level of signal in connection 10 . In any case, there may still be changes in mixers 14 and 16 as well as in filters 22 and 28. In any case, the state of the art circuit required, topically, a separator to prevent the load of the output signal from the amplifier 12, a bandpass filter 30 to limit the frequencies to be fed back to those of int ^^ i ^^ s, a detector 32 and then a linearizer to compensate for the nonlinearities in the detector 32. Only the low frequency or DC control signal at the output of the detector 32 is of interest and therefore, that would require the low pass filter 36 together with a threshold detector 38 and a linearizer amplifier 40. The linearizer amplifier 40 serves to compensate non-linearities in the response of the variable gain amplifier 12. The present invention serves to eliminate part of the circuit. shown in Figure 1 as well as to provide improved stability of the + 's signals for the A / D converters in the two parts of the equalizer in the time domain 24.

Figure 2 shows the present concept where it will be observed that a detector and a linearizing detector are not required in the feedback loop since there is already a detector within the equalizer in the time domain used to stabilize the internal signals to the equalizer in

056 743 the domain of time. In Fig. 3 the detector essentially consists of blocks 86 and 90. A separator 70 is still required to prevent the loading of the circuit in the equalizer in the time domain and a low pass filter is still used for pro [.> Orc ¡Onar caciicialne'iile only the continuous component of the signal detected as a control signal. The threshold detector 74 makes use of a reference voltage to establish the control voltage for a given gain. This is necessary to displace the requirements of the variable gain amplifier 52. An embodiment of the invention did not require a linearizer amplifier because the characteristics of the amplifier were linear.

The circuit of Figure 3 provides more details about the contents of the equalizer in the time domain, although the contents of an equalizer in the time domain are reasonably well known to those skilled in the QAM receiver technology. The digital output signals at terminals 26 or 66 of Figures 1 and 2 are essentially the outputs of the two A / D converters such as converter 84 of Figure 3. The 5 bits of the quadrature component and the phase component are logically combined in a subsequent circuit to define not only which of the 16 data positions is being represented by the incoming signal, but the phase of the component in which it is represented They position it. The method in which these senatas are combined is beyond the objective of the present invention which only refers to automatic gain control.

As mentioned previously, the five bits combined in the combinational logic 86 provide a “0” log if the signal is smaller than the I axis and a “1” Motao if the signal is greater than the I axis. If the signal It has the nominal level, the feedback makes the system work within a very small margin. If it is greater than the nominal level in both the positive and negative margin of error, the signal is shifted so that it falls within the nominal level. From the diagrams of Figures 4 and 5, and from Table 1 it follows that the most significant bit or d4 defines is ^ t ^ éh above or below an axis such as axis I for the Q phase senatas, while bit d3 defines whether it is at the top or bottom of that side of axis I. Bits d0, d1 and d2 define the level of amplitude of the error signal even though the integrator 90 sees "1" and "0" lotícos. Although this system could certainly be designed and is within the concept of the present invention, the circuit for this solution is simpler.

From the above, it follows that the feedback loop of the state of the tentaa of Figure 1 has performance limitations related to the signal level in the A / D converter 84. This level may change with the gain variations between the variable gain amplifier 52 and the A / D converter. In addition, the out-of-band power in the loop is limited by the aceta of the band pass filter 30. The present invention has the advantages that the level remains constant at the input of the A / D converter 84. Because the detector of the present invention, comprising blocks 86 and 90, has a digital input, the detector is linear and You do not need the required limo ain in block 34 of the state of Tentaa. The loop adapts to changes in RF bandwidths / baseband while the state of the state of the fabric requires design changes in the 30 band pass filter with different baseband frequencies. In addition, the detector of the present invention receives only the »^ ñ signal of intofés and does not have to distinguish or ignore foreign senatas as required by detector 32 of the teemea state.

As I will be known to those experts in teemea, the function of equalizer in the time domain 62 is to limit the effects of interference between seiibols. In a QAM system, the equalizer in the time domain also contains a record of the relative frequency of the receiver with respect to the transmitter as well as the degree of quadrature of the consi ^ ehu ^ so received from data. The central stage of a typical equalizer in the time domain can also contain circuits that measure the power level of the signal in the A / D converter. The equalizer in the time domain uses all this information to control the multipliers that adaptively shape the impulses received to correct the previous errors. Therefore, the equalizer in the time domain has a limited capacity for automatic gain control, usually no more than 3-6 dB of margin. The circuit recently mentioned in standardizing in equalizer designs in the time domain and does not require the use of the inventive concept of using the automatic gain control detector existing in the equalizer in the time domain to provide the signal for the entire control loop automatic gain, including the variable gain amplifier, and to eliminate the circuit typically used in the state of the ^ πίοα.

Therefore, an automatic gain control of a receiver circuit is claimed that uses an equalizer in the time domain as the source of the automatic gain control signal. While the invention has been discussed with respect to conventional radio receivers, the concept can also be used in many other applications that incorporate equalizers such as a digital AM (amplitude modulated) radio.

056 743