Integrated telecommunication system with improved digital voice response.

DESCRIPTION

The present invention relates to an integrated human voice response system, to handle a large number of telephone lines. This integrated telecommunication system provides a multiplex telephone line treatment and response system that offers a logical and flexible platform for the integration of all major aspects of the telephonic industry, including voice response, voice recognition Dependent and independent of who speaks, and identification followed the voice and the elocution of texts. In addition, it connects to the T1 digital telephone network (“digital”) such as that provided by MC1, AT&T, Sprint, etc. It facilitates the simultaneous traffic and data traffic, and has the possibility of being configured in medium to large applications. The system exposed here is capable of handling up to 192 lines but, of course, it can be configured to handle much larger systems.

The invention is made up of several layers of treatment units (processors), each with its own program and communication channel. Each interface processor includes one or more T1 connection interface circuits and a control microprocessor, and each numerical signal processor circuit includes a crossover point switch for link data interface (interface) and its own processor Signal number to perform signal analysis and data compression. This data is communicated to the main control microprocessor of the system, which puts it in buffer ("buffer") and sends signals to the central system (which can be a usual personal computer or small system) indicating that there is data present , and then transfers that data to the central system. In addition, a control microprocessor in the interface circuit provides the dioalogo in T1 and acts as a progress monitor or calls development in connection with the interface circuit that takes care of the fossil connections to the T1 system and the management of all its corresponding traffic.

Among the objects of the invention is the provision of a perfected integrated telecommunications system, capable of handling all the main aspects of the telephonic industry.

The indicated ones and other objects, advantages and characteristic features of the invention became detached from the study of the Descriptive Memory that follows and the accompanying drawings, in which:

- figures 1. . . 4 offer, in broad perspective, a summary of the functional aspects of the system, and of them;

- Figure 1 is a functional or block diagram of a multiple and automated telephone response and treatment system that incorporates the invention;

- Figure 2 is a functional scheme of the T1 interface processor indicated in Figure 1;

- figure 3 is a functional scheme of the number signal processor indicated in fig. one;

- figure 4 is a functional scheme of the control processor indicated in fig. one;

- Figures 5 ... 8 are more detailed schematics of the system, and of them,

- figure 5 corresponds to fig. 1 and more detailed exposition of the global system;

- Figure 6 shows the interconnection between the components of the numerical interface circuitry and the numerical signal processor;

- Figure 7 is a functional illustration of the system memory that is controlled by the main system microprocessor, and illustrates the particular situation of each of these respective elements in the interface circuitry and in the numerical switching circuitry and in the additional memory represented in fig. one; Y

- Figure 8 is a functional detail scheme of an individual number module of the digital signal processor, indicated in fig. one.

With reference now to figs. 1 ... 4, the system, in its broadest and most general aspects, was designed and designed to meet various requirements, including those of: provide a logical and flexible platform for the integration of all the main aspects of the telephone industry, such as voice response, voice recognition dependent and regardless of who speaks, identification, followed voice and speech elocution, connected to the T1 numerical network, provision of simultaneous traffic and data traffic control and possibility of being configured in medium to large size applications. It is also able to behave as an analog or numerical switch for each T1 channel. In fig. 1 several layers of processors are illustrated, each with its own program and its communication paths. Each element of T1 (or extension or "vain" of T) consists of a multitude of lines or telephonic channels. (Each “vain of T” that comes from the telephonic company can be four-wire or optic fibers, and in it there are 24 channels (or maos) or 24 data exchanges or simultaneous conversations). In this form of execution there are two spans of T -or telephone lines of T1-, each of which has 24 channels so that there are 48 channels managed by each interface processor 10-1, 10-2, 10-3, ..., 10-N. Each interface processor 10 is illustrated in a functional scheme shown in fig. 2, and includes a tablet ("chip") of microcircuits of T1 interface, which in this form of execution is a Mitel 89760 (whose details are given in the book "Microelectronics Data Book" published by the Mitel Corporation in 1988 and incorporated hereby by reference). Each processor includes a high-speed microprocessor - which

016 188 in this case is an Intel 80188 (described in the Intel Manual) and includes 64K of selective or direct access memory (RAM) to store program information and data. This high-speed microprocessor detects a telephone call on one of the channels and sends a signal to the main microprocessor of the system, which in turn sends a signal to a particular module 13 of a numerical signal processor to answer the call, and then sends signals, to the interface circuit, if the mission to answer the call and connect the calling channel to process and respond to all the signals (including those of conversation) that are in it have been assigned. It also includes a serial diagnostic terminal door.

It should be noted that the multi-busbar for transporting access and data information between the various units is indicated in Figure 1 as a numbered element 11. At the same time, a secondary busbar 12 interconnects the interface processors 10-1 and the 13-1, 13-2, 13-3, ..., 13-N processors of numerical signals. The bar 12 was indicated in fig. one globally in block form, but can be seen in greater detail, with the various interconnections between the units, represented in fig. 6. As shown in fig. 6, the busbar 12 has a plurality of lines - eight in this embodiment - designated 15-1, 15-2, ..., 15-8, with the output of each interface unit 10-1 connected to Two of the lines. The different channels of each span of T, designated with the symbols T-span 0, T-span 1, T-span 2, ..., T-span 7, each with 24 individual channels, were provided with a path of communication to the busbar 12 and, therefore, to the individual circuits 13-1, 13-2, ... of a numerical signal processor. It should be noted that each of the numerical signal processing circuits is connected to all lines of the busbar 12, so that any circuitry 13-1, 13-2, ..., 13-N of treatment can be used Numeric signals to treat (“process”) the signals that are in any of the channels of the T-channels connected to the 10-1, 10-2, ..., 10-N interface circuits.

With reference again to fig. 2, it will be noted that the busbar 12 was indicated as a high-speed main data conduit to the digital signal processors (DSP). The functions performed by the interface processors 10 include the demultiplexing of T1, numerical call management, network signaling, the ground principle, the loop and E and M, the power supply in ups and downs, the support of ISDN networks and the logic of self-diagnosis and reposition. The twenty-four channels of each of the T1 inputs, typically, were multiplied in time division and are multiplied by this processor. Each of these functions is performed by the program stored in a programmable fixed memory (ROM) 54 - indicated in fig. 5- that can be in a physical equipment module that includes installable ROM capsules. Each of the digital signal processors 13 is illustrated in detail in fig. 8, and would be described in greater detail below, in relation to that figure.

However, it should be noted that, in general terms, this circuit includes the digital signal processor pads and receives data packets for its analysis from the interface circuits 10. Each numerical signal processor 13, which is multi-tasking, then performs the data analysis and compression with these data packets and communicates the compressed data, or the dual tone frequency modulations (DTMF), to the central computer system 74 which, in this case, can be a personal computer (PC-AT). Send signal of the presence of data and transfer this data to the central computer system 74. In addition, a high-speed control microprocessor 63 (in the interface circuits 10 indicated in Fig. 5) acts as a dialogue and call development monitor, in combination with the line interface circuit. The functions performed by each of the numeric signal processor elements 13 include the interface between the processors T1 and 80386, generation and detection of DTMF and MF, vocal I / O ADPCM, PCM, LPC, the text for speech, recognition of voice, the identification of the speaker and the numerical modem.

The control processor 15 contains the main microprocessor 60 and is shown in detail in fig. 5. The functional scheme of the control processor indicated in fig. 4 illustrates a high-speed microprocessor 60 (Intel 80386 20 MHz) capable of controlling up to 16 megabytes of bits (megabytes) of direct access memory. These 16 megabytes of stain direct access memory are schematically illustrated in fig. 7, where the system memory model is schematically represented. As it would be observed, each of the numerical signal processors 13 has its memory indicated as controlled by the main control microprocessor 15 of the system: each program RAM 20 and each data RAM 21 of the numerical signal processors 13 are represented as part of the memory controlled by the main processor. At the same time, the direct access memories (RAM) and fixed memories (ROM) contained in the interface units 10 are also illustrated as being part of the accessible memory, or controlled by the main microprocessor 60. This also has access to his own memories 70 and 71. In other terms, there are up to 16 megabytes of memory - they are already fossically stored in the interface circuits 10, or in the signal processor circuits 13, or in the central computer 74 accessible for control by the CPU system 15, of main microprocessor, by means of the main manifold busbar 11. In fig. 4 a connection for the SCSI busbar to the central processor and a serial diagnostic connection that goes to a serial diagnostic terminal door is provided for system diagnosis.

The functions performed by the main control processor 15 include the assignment and call development, conversation data management, central system interface management, external, local and remote diagnosis, automatic (internal) self diagnosis and monitoring3

016 188 cia and statistics across the system. As will be appreciated, the fixed memory (ROM) indicated in fig. 6 may contain these programs, which are downloaded at the start of system operation to control the operation of the central processor through these programs. Several of the programs can be requested or selected from the ROM, or they can be loaded separately through the SCSI from permanent memory 76.

The overall aspects of the system revealed are those of offering a flexible platform for the integration of all the main aspects of the human voice response system described above. The system consists of several layers of microprocessors, each with its own program and its own communication channels, but each controlled by a main central microprocessor 60. In the connections of T1, microprocessor pads of those obtainable in the market are used to handle the phase connection to the telecommunication channels (the T1) and the management of all their corresponding traffic. Then, the data packets are provided to the digital signal processor for analysis. The numerical signal processor then performs the analysis of the signals and the compression of the compressed data or the DTFMs to the main system control microprocessor that puts them in buffer and signals to the central system if data is present, and transfers that data to the central computer. In addition, the microprocessor contained in the interface processor provides the functions of dialogue of telephone channels and monitoring (monitor) of call development, in combination with those of the interface provided by the microprocessor interface pads.

This system, therefore, offers effective means of distributing the high-speed processing (processing) requirements of the handling of the 192 channels of T1 data circuits, which effectively perform those required functions while leaving the communication functions and data storage by the main systemic microprocessor, able to address effectively for access to large volumes of data and to manage or attend to the central system interface.

With reference now to fig. 5, a more detailed functional scheme of the system is shown therein in which the interface processors 10, the digital signal processors 13 and the main control processor system 15 are represented in their arrangements interrelated with the preferred microelectronic circuit pickups in which its manufacturer has been identified (e.g., in reference 51, Mitel 89760 is a Mitel circuit component for interfacing with a T1 telephanic channel and is described in detail for example, from page 4263 to page 4-288 of the "Microelectronics Data Book", 5^to edict, 1988 of the Mitel Corporation and which is incorporated herein by reference). The coupling of the individual telephone line channels to the Mitel circuit element is of the usual type and is illustrated on page 4-286 of said Mitel manual, so it does not need to be discussed here in detail.

As described above, the control microprocessor 50 (which is an Intel 80188) is responsible for controlling and monitoring the line interface controller 51 (a Mitel 89760) and the associated circuitry. Specifically, it manages the SF or ESF signaling of AB oriented in bities; the FDL UI box to report the execution; layer 2 and layer 3 of ISDN D-channel signaling; the manifold busbar interface for communications with the main central processor 60 of the central processing unit 15 of the system; and also performs the functions of initialization and diagnostic tests for this unit.

The call development unit 52 ("progress") (a Mitel 8920) is coupled to the line interface unit 51 of DS1 and is controlled by the control microprocessor 50. The control microprocessor 50 is initially loaded with its program from fixed memory (ROM) 54. The line interface element 51 is also coupled to the data transmission medium 55 of the installation (which is a Mitel 8952 unit) which usually serves as a controller for the data transmission of the installation. Finally, the line interface unit 51 is also coupled by means of the parallel input / output terminal door 56, also controlled by the high speed control processor 50. The coupling between the manifold busbar 11 and the high-speed control processor 50, in the interface circuitry, will be compensated by a direct access buffer (RAM) 56 that stores both the data and the program and is coupled to and from the microprocessor 60 of the central processor by means of the manifold bar 11.

The busbar 12 is generally indicated as having three lines but, as will be appreciated, these are multiple lines for input / output (I / O), and the third line is a synchronization line. Thus, in the digital signal processor 13, the line 60 is a synchronization line and the lines 61 and 62 can constitute input lines and output lines respectively. The synchronization line 60 is connected to synchronize the operation of the high speed microprocessor 63 (an Intel 320C25 unit) by means of the synchronization line 64.

A crossover switch 65 (illustrated and described in greater detail in relation to Fig. 8) is controlled by the high-speed microprocessor 63 and supplies digital signals to a direct access memory (RAM) 66 of data and another RAM 67 of programs which, as described hereinbefore, are controlled by the main central processor 60. The high-speed numerical signal processor 63 is programmed to analyze and encode and decode functions with the data that is passed from the interface circuitry 10 contained in the main central microprocessor 15. Each of these circuits 13 is responsible for the treatment of six channels of the telephone circuits T1, requiring a complement of four processors 13 of digital signals to treat all 24 channels of the component T1

016 188 of telephone lines.

The high speed microprocessor 63 is therefore responsible for the handling (manipulation) of data communications that come and go from the line interface system 10; of the execution of compression from ADPCM to PCM and from PCM to ADPCM; of the execution of DTMF and MF awards; of the execution of the DTMF and MF tone generation; of the management of compensation of data in buffer memory, of the functions of sequence control, monitoring of the development of calls, preparatory operations (housekeeping) of the system and the execution of functions of channel management. All these functions are achieved under program control, received from the central processor by means of program RAM 67.

The main central processing unit 15 is illustrated as having the central processor 60, a direct access memory (RAM) 70, a fixed memory 71 (ROM) that can be in a hardware node that includes installable ROM capsules, a serial input / output terminal 72 and a small computer systems (SCSI) interface 73 that is coupled to a central or "cozy" system 74, which may include another small computer systems (SCSI) interface 75, a large or mass permanent memory 76 (for registration or archival purposes) and the small central computer (PC-AT) referred to above. The main central processor 60 includes programs to perform supervisory control functions on the digital signal processors and the interface circuitry 10 and its high-speed microprocessor 50 and the communications that go to the central system 74 and the memory management functions (such as It has been noted before, all the different memory elements identified here are controllable from the central microprocessor 60), Serial communications to a search engine monitor and error corrector and sequence controller functions. Specifically, this central microprocessor manages the interactions between the two high-speed microprocessors 50 and 63, by means of the busbars 11 and 12 and the central system 74 (through the SCSI bar). It also governs your local memory, loading the phrases from the central PC 74, transferring the recorded and decisive conversation to where to store this data in memory. It also manages the queued door of messages to and from the central computer drive device 74. In addition, it takes over the management of call development data from the two high-speed microprocessors 50 and 63, and handles the call assignment when the high-speed microprocessor 50 signals an incoming call, assigning it to a certain processor Particular 63 of high speed of the group of processors 13-1, 13-2, ..., 13-N of numerical signals. It also monitors (e.g., provides sequence controller or “watchdog” functions) of the status of each channel, and “wakes up” the blocked channels, or puts them out of service. In addition, it was programmed to handle the physical control of the SCSI interface 73 with the SCSI actuator. It can also handle universal asynchronous reception / transmission (UART) communications with the front panel and processing instructions (processes) from the central computer 74 (e.g., those of sending DTMF, recording in minutes, playing a phrase, etc. ). The central computer 74 can exercise functional control over the entire system, because it downloads (reverse load) parametric information at the beginning, and communicates individual instructions.

With reference now to fig. 8, there is a detailed scheme of the circuits of an individual numbering signal treatment unit that has the invention incorporated. Each of the individual connection lines of fig. 8 has a number, with a transverse line beside it, which indicates the number of lines or information channels. The crossover switch 65 is used to provide 8-line and 32-octet channel inputs to the numeric signal processor 13 and connection to the busbar 12. The numeric signal processor circuitry 13 has four modules, each of which of course includes the code memory 67, the data memory 68, the crossover switch 65 and the high speed microprocessor 63. The inputs to the code memory 67 and the data memory 68 are controlled by access multipliers 80 and 81, respectively, which receive inputs from the high-speed microprocessor 63 and the multi-bar access lines 83A. The high-speed microprocessor 63 is a 320C25 chip chip of TI TMS having an execution cycle of 120 ns, in order to fit into a double terminal gate memory without the need for busbar arbitrations. It has a 16-bit external busbar (indicated in the figure) with an internal 32-bit bar (not indicated), a 544-word direct access memory with the ability to access 64K data memory words and 64K words of code memory, and has a 16-bit multiplier and a serial terminal door timer. The data memory 68 is a double terminal gate memory and the main central processor 60 (fig. 5) You can download data in data memory 68 and activate a flag (“flag”) in memory to signal to high speed memory 63 the fact that the data transfer has been completed. The first half of the 120 ns cycle is assigned to access the data memory, and the second half of that cycle is used by the main microprocessor 60. In this way, difficulties will never arise due to litigation of use of busbar and, consequently, busbar arbitration is not required. As an example, four 32K x 8 RAM pads with access time and 35 ns cycle time can be used. Thus, the total data memory of 64K 16-bit words is obtained.

The code memory 67 of the digital signal processor is also a double terminal gate memory. Now, in this case, the only data can be loaded by the main central microprocessor 60 when the high-speed memory 63 is stopped and, therefore, it is assumed that the code memory 67 is only ne5

016 188 basket to be loaded during initialization. In this way a total of code memory is obtained that amounts to 64K 16-bit words. The circulation of data from the data lines 83D of the multiple bar to the direct access memory (RAM) 68 is made by means of usual data coupling circuits 82 (the designations for this exemplary embodiment are given ), and to the RAM of codes 67 by means of the data coupling circuit 83, circuits both which are illustrated as bidirectional couplers in opposition (inverse parallel), one of these circuits being available for each of the 16 individual lines indicated. In addition, the high-speed microprocessor 63 monitors the operation of these units by means of customary data coupling units 84 and 85 (with tablet designations F244x2) that put the flow of data and code information information in buffer or buffer memory with with respect to the high speed microprocessor 63.

In summary, the invention offers a flexible platform for the integration of all the main aspects of the telephone industry, including vocal response, recognition of the voice dependent and regardless of who speaks, and identification followed the voice and elocution of texts. It also offers connection to the T1 telephone network, facilitates simultaneous traffic and data traffic with the possibility of being configured and performed in medium to large-sized applications. It consists of several layers of microprocessor units, each with its own program and communications step. The telephonic telephonic phosphorus connection of T1 and corresponding traffic management is regulated by means of interface controllers. The interface system provides data packets for its analysis, to a numerical signal processor that has its own individual high-speed microprocessor. The high-speed microprocessor executes the signal analysis and data compression and then communicates the compressed data to a main or central microprocessor that puts them in buffer and sends a signal to the central system of having data present, and then transfers that data to the central computer. The system offers an efficient means of distributing high-speed processing requirements for handling 92 channels of T1 telephone data to tablets (“chips”) that effectively execute the required functions, while leaving the storage and storage functions at the same time. data communication to a single central microprocessor capable of effectively targeting access to large volumes of data and managing the SCSI interface.

Although a preferred form of embodiment of the invention has been shown and described, as was appreciated, there are various modifications and adaptations of the invention that were readily apparent to persons skilled in the art, and it is intended that such modifications and adaptations Obviously they fall within the scope of the following claims.

List of reference symbols

<td>PT1</td><td>= interface processor T1;</td>

<td>$</td><td>= signal processor;</td>

<td>P.S.</td><td>= serial diagnostic door;</td>

<td>SCSI</td><td>= SCSI bar;</td>

<td>S</td><td>= system;</td>

<td>DS1's</td><td>= from other DS1;</td>

<td>DSP's</td><td>= to other DSPs;</td>

<td>AND</td><td>= plate;</td>

<td>AND'</td><td>= board / system;</td>

<td>M</td><td>= switch;</td>

<td>P</td><td>= program;</td>

<td>D</td><td>= data;</td>

<td>RR</td><td>= multiplex bar memory;</td>

<td>IN</td><td>= 80386 memory space;</td>

<td>ADBr's</td><td>= access in multiple bar.</td>

016 188