EP3920005A4
Electrical design rule checking method and device for integrated circuit
4 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4
Every citation, both waysCites: the store holds 3 of 4
| Document | Relation | Office | Cited during |
|---|---|---|---|
| US2009187866A1 | Cites | United States of America | Search report |
| US9223912B1 | Cites | United States of America | Search report |
| US9436795B2 | Cites | United States of America | Search report |
| See also references of WO 2020155290A1 | Non-patent | – | Search report |
6 members in 4 offices
Priority claims3
| Document | Office | Kind | Date |
|---|---|---|---|
| 201910081729 | China | A | |
| 201910081729 | China | – | |
| 2019077021 | China | W |
Members6
| Document | Office | Kind | |
|---|---|---|---|
| CN111291531A | China | A | |
| WO2020155290A1 | World Intellectual Property Organization (WIPO) | A1 | |
| EP3920005A1 | European Patent Office (EPO) | A1 | |
| US2022100946A1 | United States of America | A1 | |
| EP3920005A4This record | European Patent Office (EPO) | A4 | |
| US12086527B2 | United States of America | B2 |
11 legal events, as 2 offices reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | Office | |
|---|---|---|---|
| Supplementary search report drawn up and despatchedA4 | A4 | EP | |
| Information provided on ipc code assigned before grantRIC1 | RIC1 | EP | |
| Information provided on ipc code assigned before grantRIC1 | RIC1 | EP | |
| Amendment of ipc main classPREVIOUS MAIN CLASS: H99Z9999999999R079 | R079 | DE | |
| Request for validation of the european patent (deleted)DAV | DAV | EP | |
| Request for extension of the european patent (deleted)DAX | DAX | EP | |
| Request for examination filed17P | 17P | EP | |
| Designated contracting statesAK | AK | EP | |
| Public reference made under article 153(3) epc to a published international application that has entered the european phaseORIGINAL CODE: 0009012PUAI | PUAI | EP | |
| Information on the status of an ep patent application or granted ep patentGrantedSTATUS: REQUEST FOR EXAMINATION WAS MADESTAA | STAA | EP | |
| Information on the status of an ep patent application or granted ep patentGrantedSTATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADESTAA | STAA | EP |
Numbers
- Publication
- 3920005
- Application
- 19913417
Titles3
- German
- ELEKTRISCHES DESIGNREGELPRÜFVERFAHREN UND VORRICHTUNG FÜR INTEGRIERTE SCHALTUNG
- English
- ELECTRICAL DESIGN RULE CHECKING METHOD AND DEVICE FOR INTEGRATED CIRCUIT
- French
- PROCÉDÉ ET DISPOSITIF DE VÉRIFICATION DES RÈGLES DE CONCEPTION ÉLECTRIQUE POUR CIRCUIT INTÉGRÉ
Classification
- CPC, 4
- G06F30/398
- G06F30/367
- G06F30/392
- G06F30/323
- IPC, 2
- G06F30 367
- G06F30 398
Designated states1
- Contracting states, 1
- Türkiye
