Semiconductor device including resonant tunneling diode structure having a superlattice and related methods

<u>Technical Field</u>

0001The present disclosure generally relates to semiconductor devices and, more particularly, to double barrier resonant tunneling diodes having a superlattice barrier layer and related circuits and methods.

<u>Background</u>

0002Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by enhancing the mobility of the charge carriers. For example, <patcit id="pcit0001" dnum="US20030057416A" dnum-type="L"><text>U.S. Patent Application No. 2003/0057416 to Currie et al.</text></patcit> discloses strained material layers of silicon, silicon-germanium, and relaxed silicon and also including impurity-free zones that would otherwise cause performance degradation. The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices. Published <patcit id="pcit0002" dnum="US20030034529A" dnum-type="L"><text>U.S. Patent Application No. 2003/0034529 to Fitzgerald et al.</text></patcit> discloses a CMOS inverter also based upon similar strained silicon technology.

0003<patcit id="pcit0003" dnum="US6472685B2"><text>U.S. Patent No. 6,472,685 B2 to Takagi </text></patcit>discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility.

0004<patcit id="pcit0004" dnum="US4937204A"><text>U.S. Patent No. 4,937,204 to Ishibashi et al.</text></patcit> discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fractional or binary or a binary compound semiconductor layer, are alternately and epitaxially grown. The direction of main current flow is perpendicular to the layers of the superlattice.

0005<patcit id="pcit0005" dnum="US5357119A"><text>U.S. Patent No. 5,357,119 to Wang et al.</text></patcit> discloses a Si-Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice. Along these lines, <patcit id="pcit0006" dnum="US5683934A"><text>U.S. Patent No. 5,683,934 to Candelaria</text></patcit> discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutionally present in the silicon lattice at a percentage that places the channel layer under tensile stress.

0006<patcit id="pcit0007" dnum="US5216262A"><text>U.S. Patent No. 5,216,262 to Tsu </text></patcit>discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternate layers of SiO2/Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.

0007An article entitled "<nplcit id="ncit0001" npl-type="s"><text>Phenomena in silicon nanostructure devices" also to Tsu and published online September 6, 2000 by Applied Physics and Materials Science &amp; Processing, pp. 391-402</text></nplcit> discloses a semiconductor-atomic superlattice (SAS) of silicon and oxygen. The Si/O superlattice is disclosed as useful in a silicon quantum and light-emitting devices. In particular, a green electroluminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS. The disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density. One SAS structure included a 1.1 nm thick silicon portion that is about eight atomic layers of silicon, and another structure had twice this thickness of silicon. An article to <nplcit id="ncit0002" npl-type="s"><text>Luo et al. entitled "Chemical Design of Direct-Gap Light-Emitting Silicon" published in Physical Review Letters, Vol. 89, No. 7 (August 12, 2002</text></nplcit>) further discusses the light emitting SAS structures of Tsu.

0008Published International Application <patcit id="pcit0008" dnum="WO02103767A1"><text>WO 02/103,767 A1 to Wang, Tsu and Lofgren</text></patcit>, discloses a barrier building block of thin silicon and oxygen, carbon, nitrogen, phosphorous, antimony, arsenic or hydrogen to thereby reduce current flowing vertically through the lattice more than four orders of magnitude. The insulating layer/barrier layer allows for low defect epitaxial silicon to be deposited next to the insulating layer.

0009Published Great Britain Patent Application <patcit id="pcit0009" dnum="GB2347520A"><text>2,347,520 to Mears et al.</text></patcit> discloses that principles of Aperiodic Photonic Band-Gap (APBG) structures may be adapted for electronic bandgap engineering. In particular, the application discloses that material parameters, for example, the location of band minima, effective mass, etc., can be tailored to yield new aperiodic materials with desirable band-structure characteristics. Other parameters, such as electrical conductivity, thermal conductivity and dielectric permittivity or magnetic permeability are disclosed as also possible to be designed into the material.

0010Furthermore, <patcit id="pcit0010" dnum="US6376337B"><text>U.S. Pat. No. 6,376,337 to Wang et al.</text></patcit> discloses a method for producing an insulating or barrier layer for semiconductor devices which includes depositing a layer of silicon and at least one additional element on the silicon substrate whereby the deposited layer is substantially free of defects such that epitaxial silicon substantially free of defects can be deposited on the deposited layer. Alternatively, a monolayer of one or more elements, preferably comprising oxygen, is absorbed on a silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon forms a barrier composite.

0011The paper "<nplcit id="ncit0003" npl-type="s"><text>Parametric study of AlAs/GaAs superlattice double-barrier diodes", Paulus et. al., Applied physics letters 53, No. 3, pages 207-209, 18.07.1998</text></nplcit> discloses a III-V double barrier resonant tunneling diode comprising AlAs/GaAs superlattice barrier layers.

0012<patcit id="pcit0011" dnum="US4851886A"><text>U.S. Pat. No. 4,851,886</text></patcit> discloses a III-V double barrier resonant tunneling diode comprising AlGaAs/GaAs superlattice barrier layers.

0013A silicon- based double barrier resonant tunneling diode is known from <patcit id="pcit0012" dnum="US5466949A"><text>U.S. Pat. No. 5,466,949</text></patcit>.

0014Despite the existence of such approaches, further enhancements may be desirable for using advanced semiconductor materials and processing techniques to achieve improved performance in semiconductor devices.

<u>Summary</u>

0015A semiconductor device according to the present invention includes at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD includes a first doped semiconductor layer and a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions are chemically bound together, with the chemical bonds traversing the at least one intervening non-semiconductor monolayer therebetween The at least one DBRTD further includes an intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the intrinsic semiconductor layer, and a second doped semiconductor layer on the second barrier layer.

0016In accordance with one example embodiment, the first and second doped semiconductor layers may comprise silicon, and the intrinsic layer may comprise at least one of silicon and germanium. Furthermore, the second barrier layer may also comprise a superlattice, and the second doped semiconductor layer may accordingly comprise a single crystal semiconductor layer. In accordance with another example, the second barrier layer may comprise an oxide layer, and the second doped semiconductor layer may comprise a polycrystalline semiconductor layer.

0017In one example implementation, the first and second doped semiconductor layers may have the same dopant conductivity type. In another example implementation, the first and second doped semiconductor layers may have opposite dopant conductivity types. The at least one DBRTD may be a pair of DBRTDs connected in series to define a monostable-bistable transition logic element (MOBILE). By way of example, the at least one non-semiconductor monolayer may comprise oxygen, and the semiconductor monolayers may comprise silicon.

0018The present invention provides also a method for making a semiconductor device including forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and forming a first barrier layer on the first doped semiconductor layer and comprising a superlattice. The superlattice includes a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions are chemically bound together, with the chemical bonds traversing the at least one intervening non-semiconductor monolayer therebetween. The method further includes forming an intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the intrinsic semiconductor layer, and forming a second doped semiconductor layer on the second barrier layer.

0019More particularly, the first and second doped semiconductor layers may comprise silicon, and the intrinsic layer may comprise germanium. In accordance with one example embodiment, the second barrier layer may also comprise a superlattice. Moreover, the second doped semiconductor layer may comprise a single crystal semiconductor layer. In accordance with another example, the second barrier layer may comprise an oxide layer, and the second doped semiconductor layer may comprise a polycrystalline semiconductor layer.

0020By way of example, the first and second doped semiconductor layers may have the same dopant conductivity type. In accordance with another example, the first and second doped semiconductor layers may have opposite dopant conductivity types. The at least one non-semiconductor monolayer may comprise oxygen, and the semiconductor monolayers comprise silicon, for example.

<u>Brief Description of the Drawings</u>

0021<ul id="ul0001" list-style="none" compact="compact"><li><figref idref="f0001">FIG. 1</figref> is a greatly enlarged schematic cross-sectional view of a superlattice for use in a semiconductor device in accordance with an example embodiment.</li><li><figref idref="f0002">FIG. 2</figref> is a perspective schematic atomic diagram of a portion of the superlattice shown in <figref idref="f0001">FIG. 1</figref>.</li><li><figref idref="f0003">FIG. 3</figref> is a greatly enlarged schematic cross-sectional view of another embodiment of a superlattice for use in a semiconductor device in accordance with an example embodiment.</li><li><figref idref="f0004">FIG. 4A</figref> is a graph of the calculated band structure from the gamma point (G) for both bulk silicon as in the prior art, and for the 4/1 Si/O superlattice as shown in <figref idref="f0001 f0002">FIGS. 1-2</figref>.</li><li><figref idref="f0005">FIG. 4B</figref> is a graph of the calculated band structure from the Z point for both bulk silicon as in the prior art, and for the 4/1 Si/O superlattice as shown in <figref idref="f0001 f0002">FIGS. 1-2</figref>.</li><li><figref idref="f0006">FIG. 4C</figref> is a graph of the calculated band structure from both the gamma and Z points for both bulk silicon as in the prior art, and for the 5/1/3/1 Si/O superlattice as shown in <figref idref="f0003">FIG. 3</figref>.</li><li><figref idref="f0007">FIG. 5A</figref> is a schematic cross-sectional diagram of an N-type double barrier resonant tunneling diode (DBRTD) including superlattice barrier layers in accordance with an example embodiment.</li><li><figref idref="f0007">FIG. 5B</figref> is an energy band diagram for the DBRTD of <figref idref="f0007">FIG. 5A</figref>.</li><li><figref idref="f0007">FIG. 6A</figref> is a schematic cross-sectional diagram of a P-type double barrier resonant tunneling diode (DBRTD) including superlattice barrier layers in accordance with an example embodiment.</li><li><figref idref="f0007">FIG. 6B</figref> is an energy band diagram for the DBRTD of <figref idref="f0007">FIG. 6A</figref>.</li><li><figref idref="f0008">FIG. 7A</figref> is a schematic cross-sectional diagram of an N-type DBRTD including superlattice and SiO₂ barrier layers in accordance with an example embodiment.</li><li><figref idref="f0008">FIG. 7B</figref> is an energy band diagram for the DBRTD of <figref idref="f0008">FIG. 7A</figref>.</li><li><figref idref="f0008">FIG. 8A</figref> is a schematic cross-sectional diagram of a P-type DBRTD including superlattice and SiO₂ barrier layers in accordance with an example embodiment.</li><li><figref idref="f0008">FIG. 8B</figref> is an energy band diagram for the DBRTD of <figref idref="f0008">FIG. 8A</figref>.</li><li><figref idref="f0009">FIG. 9A</figref> is a schematic cross-sectional diagram of a P-type DBRTD including superlattice barrier layers and a germanium intrinsic layer in accordance with an example embodiment.</li><li><figref idref="f0009">FIG. 9B</figref> is an energy band diagram for the DBRTD of <figref idref="f0009">FIG. 9A</figref>.</li><li><figref idref="f0009">FIG. 10A</figref> is a schematic cross-sectional diagram of a P-type DBRTD including superlattice and SiO₂ barrier layers and a germanium intrinsic layer in accordance with an example embodiment.</li><li><figref idref="f0009">FIG. 10B</figref> is an energy band diagram for the DBRTD of <figref idref="f0009">FIG. 10A</figref>.</li><li><figref idref="f0010">FIG. 11A</figref> is a schematic cross-sectional diagram of an inter-band DBRTD including superlattice barrier layers and oppositely-doped contact layers in accordance with an example embodiment.</li><li><figref idref="f0010">FIG. 11B</figref> is an energy band diagram for the DBRTD of <figref idref="f0010">FIG. 11A</figref>.</li><li><figref idref="f0010">FIG. 12A</figref> is a schematic cross-sectional diagram of an inter-band DBRTD including superlattice and SiO₂ barrier layers and oppositely-doped contact layers in accordance with an example embodiment.</li><li><figref idref="f0010">FIG. 12B</figref> is an energy band diagram for the DBRTD of <figref idref="f0010">FIG. 12A</figref>.</li><li><figref idref="f0011">FIG. 13A</figref> is a schematic cross-sectional diagram of an inter-band DBRTD including superlattice barrier layers and oppositely-doped contact layers with an intrinsic germanium layer in accordance with an example embodiment.</li><li><figref idref="f0011">FIG. 13B</figref> is an energy band diagram for the DBRTD of <figref idref="f0010">FIG. 11A</figref>.</li><li><figref idref="f0012">FIG. 14</figref> is a schematic cross-sectional diagram of an N-type DBRTD including superlattice barrier layers and electron mean free path control layers in accordance with an example embodiment.</li><li><figref idref="f0012">FIG. 15</figref> is a schematic cross-sectional diagram of a P-type DBRTD including superlattice barrier layers, an intrinsic germanium layer, and electron mean free path control layers in accordance with an example embodiment.</li><li><figref idref="f0013">FIG. 16</figref> is a schematic cross-sectional diagram of an inter-band DBRTD including superlattice barrier layers with oppositely doped contact layers and electron mean free path control layers in accordance with an example embodiment.</li><li><figref idref="f0014">FIG. 17</figref> is a cross-sectional diagram of a FINFET including one or more DBRTD devices in accordance with an example embodiment.</li><li><figref idref="f0014">FIG. 18</figref> is schematic circuit diagram of a monostable-bistable transition logic element (MOBILE) including a DBRTD in accordance with an example embodiment.</li><li><figref idref="f0015">FIG. 19</figref> is a flow diagram illustrating a process flow for making a semiconductor device including one or more DBRTD structures in accordance with an example embodiment.</li></ul>

<u>Detailed Description</u>

0022Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which the example embodiments are shown. The embodiments may, however, be implemented in many different forms and should not be construed as limited to the specific examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like numbers refer to like elements throughout, and prime notation is used to indicate similar elements in different embodiments.

0023Generally speaking, the present disclosure relates to tunneling diode devices, including RTD devices, having an enhanced semiconductor superlattice therein which may provide desired potential barrier and dopant confinement features and enabling integration of such devices in standard CMOS processes. The enhanced semiconductor superlattice is also referred to as an "MST" layer or "MST technology" in this disclosure and the accompanying Appendix A. Further background on the use of MST technology to provide dopant blocking features in semiconductor devices may be found in <patcit id="pcit0013" dnum="US9275996B"><text>U.S. Pat. No. 9,275,996 to Mears et al.</text></patcit>.

0024More particularly, the MST technology relates to advanced semiconductor materials such as the superlattice <b>25</b> described further below. Applicant theorizes, without wishing to be bound thereto, that certain superlattices as described herein reduce the effective mass of charge carriers and that this thereby leads to higher charge carrier mobility. Effective mass is described with various definitions in the literature. As a measure of the improvement in effective mass Applicant's use a "conductivity reciprocal effective mass tensor", <maths id="math0001"><math display="inline"><msubsup><mi mathvariant="bold">M</mi><mi>e</mi><mrow><mo>−</mo><mn>1</mn></mrow></msubsup></math><img file="EP3494599B1_D0001.tif" /></maths> and <maths id="math0002"><math display="inline"><msubsup><mi mathvariant="bold">M</mi><mi>h</mi><mrow><mo>−</mo><mn>1</mn></mrow></msubsup></math><img file="EP3494599B1_D0002.tif" /></maths> for electrons and holes respectively, defined as: <maths id="math0003"><math display="block"><msubsup><mi mathvariant="bold">M</mi><mrow><mi>e</mi><mo>,</mo><mi mathvariant="italic">ij</mi></mrow><mrow><mo>−</mo><mn>1</mn></mrow></msubsup><mfenced><msub><mi>E</mi><mi>F</mi></msub><mi>T</mi></mfenced><mo>=</mo><mfrac><mstyle displaystyle="true"><munder><mo>∑</mo><mrow><mi>E</mi><mo>></mo><msub><mi>E</mi><mi>F</mi></msub></mrow></munder><mstyle displaystyle="true"><mrow><munder><mo>∫</mo><mrow><mi>B</mi><mo>.</mo><mi>Z</mi><mo>.</mo></mrow></munder><mrow><msub><mfenced><msub><mo>∇</mo><mi mathvariant="normal">k</mi></msub><mi>E</mi><mfenced><mi mathvariant="bold">k</mi><mi>n</mi></mfenced></mfenced><mi>i</mi></msub><msub><mfenced><msub><mo>∇</mo><mi mathvariant="normal">k</mi></msub><mi>E</mi><mfenced><mi mathvariant="bold">k</mi><mi>n</mi></mfenced></mfenced><mi>j</mi></msub><mfrac><mrow><mo>∂</mo><mi>f</mi><mfenced><mi>E</mi><mfenced><mi mathvariant="bold">k</mi><mi>n</mi></mfenced><mo>,</mo><msub><mi>E</mi><mi>F</mi></msub><mo>,</mo><mi>T</mi></mfenced></mrow><mrow><mo>∂</mo><mi>E</mi></mrow></mfrac><msup><mi>d</mi><mn>3</mn></msup><mi mathvariant="bold">k</mi></mrow></mrow></mstyle></mstyle><mstyle displaystyle="true"><munder><mo>∑</mo><mrow><mi>E</mi><mo>></mo><msub><mi>E</mi><mi>F</mi></msub></mrow></munder><mstyle displaystyle="true"><mrow><munder><mo>∫</mo><mrow><mi>B</mi><mo>.</mo><mi>Z</mi><mo>.</mo></mrow></munder><mrow><mi>f</mi><mfenced><mi>E</mi><mfenced><mi mathvariant="bold">k</mi><mi>n</mi></mfenced><mo>,</mo><msub><mi>E</mi><mi>F</mi></msub><mo>,</mo><mi>T</mi></mfenced><msup><mi>d</mi><mn>3</mn></msup><mi mathvariant="bold">k</mi></mrow></mrow></mstyle></mstyle></mfrac></math><img file="EP3494599B1_D0003.tif" /></maths> for electrons and: <maths id="math0004"><math display="block"><msubsup><mi mathvariant="bold">M</mi><mrow><mi>h</mi><mo>,</mo><mi mathvariant="italic">ij</mi></mrow><mrow><mo>−</mo><mn>1</mn></mrow></msubsup><mfenced><msub><mi>E</mi><mi>F</mi></msub><mi>T</mi></mfenced><mo>=</mo><mfrac><mrow><mo>−</mo><mstyle displaystyle="true"><munder><mo>∑</mo><mrow><mi>E</mi><mo><</mo><msub><mi>E</mi><mi>F</mi></msub></mrow></munder><mstyle displaystyle="true"><mrow><munder><mo>∫</mo><mrow><mi>B</mi><mo>.</mo><mi>Z</mi><mo>.</mo></mrow></munder><mrow><msub><mfenced><msub><mo>∇</mo><mi mathvariant="normal">k</mi></msub><mi>E</mi><mfenced><mi mathvariant="bold">k</mi><mi>n</mi></mfenced></mfenced><mi>i</mi></msub><msub><mfenced><msub><mo>∇</mo><mi>k</mi></msub><mi>E</mi><mfenced><mi mathvariant="bold">k</mi><mi>n</mi></mfenced></mfenced><mi>j</mi></msub><mfrac><mrow><mo>∂</mo><mi>f</mi><mfenced><mi>E</mi><mfenced><mi mathvariant="bold">k</mi><mi>n</mi></mfenced><mo>,</mo><msub><mi>E</mi><mi>F</mi></msub><mo>,</mo><mi>T</mi></mfenced></mrow><mrow><mo>∂</mo><mi>E</mi></mrow></mfrac><msup><mi>d</mi><mn>3</mn></msup><mi mathvariant="bold">k</mi></mrow></mrow></mstyle></mstyle></mrow><mstyle displaystyle="true"><munder><mo>∑</mo><mrow><mi>E</mi><mo><</mo><msub><mi>E</mi><mi>F</mi></msub></mrow></munder><mstyle displaystyle="true"><mrow><munder><mo>∫</mo><mrow><mi>B</mi><mo>.</mo><mi>Z</mi><mo>.</mo></mrow></munder><mrow><mfenced><mn>1</mn><mo>−</mo><mi>f</mi><mfenced><mi>E</mi><mfenced><mi mathvariant="bold">k</mi><mi>n</mi></mfenced><mo>,</mo><msub><mi>E</mi><mi>F</mi></msub><mo>,</mo><mi>T</mi></mfenced></mfenced><msup><mi>d</mi><mn>3</mn></msup><mi mathvariant="bold">k</mi></mrow></mrow></mstyle></mstyle></mfrac></math><img file="EP3494599B1_D0004.tif" /></maths> for holes, where <i>f</i> is the Fermi-Dirac distribution, E_F is the Fermi energy, T is the temperature, E(<b>k</b>,n) is the energy of an electron in the state corresponding to wave vector <b>k</b> and the n^th energy band, the indices i and j refer to Cartesian coordinates x, y and z, the integrals are taken over the Brillouin zone (B.Z.), and the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.

0025Applicant's definition of the conductivity reciprocal effective mass tensor is such that a tensorial component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor. Again Applicant theorizes without wishing to be bound thereto that the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport. The inverse of the appropriate tensor element is referred to as the conductivity effective mass. In other words, to characterize semiconductor material structures, the conductivity effective mass for electrons/holes as described above and calculated in the direction of intended carrier transport is used to distinguish improved materials.

0026Applicant has identified improved materials or structures for use in semiconductor devices. More specifically, Applicant has identified materials or structures having energy band structures for which the appropriate conductivity effective masses for electrons and/or holes are substantially less than the corresponding values for silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in such a manner that they provide piezoelectric, pyroelectric, and/or ferroelectric properties that are advantageous for use in a variety of different types of devices, as will be discussed further below.

0027Referring now to <figref idref="f0001">FIGS. 1</figref> and <figref idref="f0002">2</figref>, the materials or structures are in the form of a superlattice <b>25</b> whose structure is controlled at the atomic or molecular level and may be formed using known techniques of atomic or molecular layer deposition. The superlattice <b>25</b> includes a plurality of layer groups <b>45a-45n</b> arranged in stacked relation, as perhaps best understood with specific reference to the schematic cross-sectional view of <figref idref="f0001">FIG. 1</figref>.

0028Each group of layers <b>45a-45n</b> of the superlattice <b>25</b> illustratively includes a plurality of stacked base semiconductor monolayers <b>46</b> defining a respective base semiconductor portion <b>46a-46n</b> and an energy band-modifying layer <b>50</b> thereon. The energy band-modifying layers <b>50</b> are indicated by stippling in <figref idref="f0001">FIG. 1</figref> for clarity of illustration.

0029The energy band-modifying layer <b>50</b> illustratively includes one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. By "constrained within a crystal lattice of adjacent base semiconductor portions" it is meant that at least some semiconductor atoms from opposing base semiconductor portions <b>46a-46n</b> are chemically bound together through the non-semiconductor monolayer <b>50</b> therebetween, as seen in <figref idref="f0002">FIG. 2</figref>. Generally speaking, this configuration is made possible by controlling the amount of non-semiconductor material that is deposited on semiconductor portions <b>46a-46n</b> through atomic layer deposition techniques so that not all (i.e., less than full or 100% coverage) of the available semiconductor bonding sites are populated with bonds to non-semiconductor atoms, as will be discussed further below. Thus, as further monolayers <b>46</b> of semiconductor material are deposited on or over a non-semiconductor monolayer <b>50</b>, the newly deposited semiconductor atoms will populate the remaining vacant bonding sites of the semiconductor atoms below the non-semiconductor monolayer.

0030In other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that reference herein to a non-semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as silicon, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.

0031Applicant theorizes without wishing to be bound thereto that energy band-modifying layers <b>50</b> and adjacent base semiconductor portions <b>46a-46n</b> cause the superlattice <b>25</b> to have a lower appropriate conductivity effective mass for the charge carriers in the parallel layer direction than would otherwise be present. Considered another way, this parallel direction is orthogonal to the stacking direction. The band modifying layers <b>50</b> may also cause the superlattice <b>25</b> to have a common energy band structure, while also advantageously functioning as an insulator between layers or regions vertically above and below the superlattice.

0032Moreover, this superlattice structure may also advantageously act as a barrier to dopant and/or material diffusion between layers vertically above and below the superlattice <b>25</b>. These properties may thus advantageously allow the superlattice <b>25</b> to provide an interface for high-K dielectrics which not only reduces diffusion of the high-K material into the channel region, but which may also advantageously reduce unwanted scattering effects and improve device mobility, as will be appreciated by those skilled in the art.

0033It is also theorized that semiconductor devices including the superlattice <b>25</b> may enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present. In some embodiments, and as a result of the band engineering achieved by the present invention, the superlattice <b>25</b> may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example.

0034The superlattice <b>25</b> also illustratively includes a cap layer <b>52</b> on an upper layer group <b>45n</b>. The cap layer <b>52</b> may comprise a plurality of base semiconductor monolayers <b>46</b>. The cap layer <b>52</b> may have between 2 to 100 monolayers of the base semiconductor, and, more preferably between 10 to 50 monolayers.

0035Each base semiconductor portion <b>46a-46n</b> may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors. Of course, the term Group IV semiconductors also includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.

0036Each energy band-modifying layer <b>50</b> may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon and carbon-oxygen, for example. The non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example

0037It should be noted that the term monolayer is meant to include a single atomic layer and also a single molecular layer. It is also noted that the energy band-modifying layer <b>50</b> provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied (i.e., there is less than full or 100% coverage). For example, with particular reference to the atomic diagram of <figref idref="f0002">FIG. 2</figref>, a 4/1 repeating structure is illustrated for silicon as the base semiconductor material, and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied in the illustrated example.

0038In other embodiments and/or with different materials this one-half occupation would not necessarily be the case as will be appreciated by those skilled in the art. Indeed it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments.

0039Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used. Accordingly, semiconductor devices incorporating the superlattice <b>25</b> in accordance with the invention may be readily adopted and implemented, as will be appreciated by those skilled in the art.

0040It is theorized without Applicant wishing to be bound thereto that for a superlattice, such as the Si/O superlattice, for example, that the number of silicon monolayers should desirably be seven or less so that the energy band of the superlattice is common or relatively uniform throughout to achieve the desired advantages. The 4/1 repeating structure shown in <figref idref="f0001">FIGS. 1</figref> and <figref idref="f0002">2</figref>, for Si/O has been modeled to indicate an enhanced mobility for electrons and holes in the X direction. For example, the calculated conductivity effective mass for electrons (isotropic for bulk silicon) is 0.26 and for the 4/1 SiO superlattice in the X direction it is 0.12 resulting in a ratio of 0.46. Similarly, the calculation for holes yields values of 0.36 for bulk silicon and 0.16 for the 4/1 Si/O superlattice resulting in a ratio of 0.44.

0041While such a directionally preferential feature may be desired in certain semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. It may also be beneficial to have an increased mobility for both electrons and holes, or just one of these types of charge carriers as will be appreciated by those skilled in the art.

0042The lower conductivity effective mass for the 4/1 Si/O embodiment of the superlattice <b>25</b> may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes. Of course, the superlattice <b>25</b> may further comprise at least one type of conductivity dopant therein, as will also be appreciated by those skilled in the art.

0043Indeed, referring now additionally to <figref idref="f0003">FIG. 3</figref>, another embodiment of a superlattice <b>25'</b> in accordance with the invention having different properties is now described. In this embodiment, a repeating pattern of 3/1/5/1 is illustrated. More particularly, the lowest base semiconductor portion <b>46a'</b> has three monolayers, and the second lowest base semiconductor portion <b>46b'</b> has five monolayers. This pattern repeats throughout the superlattice <b>25'</b>. The energy band-modifying layers <b>50'</b> may each include a single monolayer. For such a superlattice <b>25'</b> including Si/O, the enhancement of charge carrier mobility is independent of orientation in the plane of the layers. Those other elements of <figref idref="f0003">FIG. 3</figref> not specifically mentioned are similar to those discussed above with reference to <figref idref="f0001">FIG. 1</figref> and need no further discussion herein.

0044In some device embodiments, all of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.

0045In <figref idref="f0004 f0005 f0006">FIGS. 4A-4C</figref>, band structures calculated using Density Functional Theory (DFT) are presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. Hence all bands above the gap may be shifted by an appropriate "scissors correction." However the shape of the band is known to be much more reliable. The vertical energy axes should be interpreted in this light.

0046<figref idref="f0004">FIG. 4A</figref> shows the calculated band structure from the gamma point (G) for both bulk silicon (represented by continuous lines) and for the 4/1 Si/O superlattice <b>25</b> shown in <figref idref="f0001">FIG. 1</figref> (represented by dotted lines). The directions refer to the unit cell of the 4/1 Si/O structure and not to the conventional unit cell of Si, although the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, and, hence, shows the expected location of the Si conduction band minimum. The (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell. Those skilled in the art will appreciate that the bands of Si on the figure are folded to represent them on the appropriate reciprocal lattice directions for the 4/1 Si/O structure.

0047It can be seen that the conduction band minimum for the 4/1 Si/O structure is located at the gamma point in contrast to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point. One may also note the greater curvature of the conduction band minimum for the 4/1 Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.

0048<figref idref="f0005">FIG. 4B</figref> shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the 4/1 Si/O superlattice <b>25</b> (dotted lines). This figure illustrates the enhanced curvature of the valence band in the (100) direction.

0049<figref idref="f0006">FIG. 4C</figref> shows the calculated band structure from both the gamma and Z point for both bulk silicon (continuous lines) and for the 5/1/3/1 Si/O structure of the superlattice <b>25'</b> of <figref idref="f0003">FIG. 3</figref> (dotted lines). Due to the symmetry of the 5/1/3/1 Si/O structure, the calculated band structures in the (100) and (010) directions are equivalent. Thus the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (001) stacking direction. Note that in the 5/1/3/1 Si/O example the conduction band minimum and the valence band maximum are both at or close to the Z point.

0050Although increased curvature is an indication of reduced effective mass, the appropriate comparison and discrimination may be made via the conductivity reciprocal effective mass tensor calculation. This leads Applicant to further theorize that the 5/1/3/1 superlattice <b>25'</b> should be substantially direct bandgap. As will be understood by those skilled in the art, the appropriate matrix element for optical transition is another indicator of the distinction between direct and indirect bandgap behavior.

0051Turning to <figref idref="f0007">FIGS. 5A-6B</figref>, tunneling diode structures and associated devices including the above-described superlattice technology (also referred to as "MST" herein) are now described. By way of background, resonant tunneling diodes operate in a similar fashion to p-n junction diodes, in that the diode will conduct an "on" current with forward bias. Yet, in p-n junction diodes the bias current monotonically increases the forward current, whereas a resonant tunneling diode (RTD) exhibits negative differential resistance (NDR), in which the current level drops with increased bias. NDR characteristics increase operation points on load lines, and it is thus attractive for various circuit applications.

0052Generally speaking, most RTD devices utilize III-V materials, which makes integration into Si-based CMOS platforms very difficult. Moreover, a high doping level is typically desired at the contact regions for ohmic contacts. For example, doping levels may be at least 10x¹⁸/cm³, and levels of greater than 1x10²⁰/cm³ may be desired for lower contact resistance.

0053On the other hand, RTDs also typically use a relatively low doping level in the three regions immediately adjacent to and between the double barriers to prevent impurity scattering. The requisite doping level is generally determined based upon the electron mean free path vs. the dimensions of the double barrier and tunneling layer thicknesses. Typically, the doping level may be set at approximately 1x10¹⁶/cm³.

0054N-type and P-type MST double barrier (DB) RTD structures <b>110</b>, <b>110</b> and their associated band diagrams <b>101</b>, <b>102</b> are shown in <figref idref="f0007">FIGS. 5A, 6B and 5B, 6B</figref>, respectively. The N-type DBRTD structure <b>100</b> illustratively includes a stack of layers including (starting from the bottom) a bottom n+ Si contact layer <b>102</b>, a first superlattice barrier layer <b>103</b> (such as the superlattice layers <b>25</b>, <b>25'</b> described above - labeled MST in the drawings), an undoped (intrinsic) Si layer <b>104</b>, a second superlattice barrier layer <b>105</b>, and an upper n+ Si contact layer <b>106</b>. Similarly, the P-type DBRTD <b>110</b> illustratively includes a stack of layers including (starting from the bottom) a bottom p+ Si contact layer <b>112</b>, a first superlattice barrier layer <b>113</b>, an undoped (intrinsic) Si layer <b>114</b>, a second superlattice barrier layer <b>115</b>, and an upper p+ Si contact layer <b>116</b>.

0055The superlattice barrier layers <b>103</b>, <b>105</b> and <b>113</b>, <b>115</b> advantageously allow for the formation of potential barriers in the Si conduction band (CB) and valence band (VB) while maintaining Si epitaxy when forming the upper contact layers <b>106</b>, <b>116</b>. That is, the above-described superlattice structure advantageously allows semiconductor (e.g., silicon) bonds to propagate through the intervening oxygen atoms so that the epitaxy is not disrupted, allowing single crystalline semiconductor contact layers to be formed on top of the second superlattice barrier layers <b>105</b>, <b>115</b>.

0056The barrier height may advantageously be tuned for the given RTD application using the different structures and fabrication techniques described above. Simulations of a 4/1 repeating structure with a 15Å spacing between non-semiconductor (e.g., oxygen) monolayers projects approximately 0.6 eV for both the CB and VB. Furthermore, the potential barrier strength resulting from the MST barrier layers may be tuned based upon the oxygen concentration per monolayer, spacing between oxygen monolayers, and the number of oxygen monolayers used, for example, as will be appreciated by those skilled in the art.

0057However, another important characteristic of the superlattice film is that it may advantageously be used to block dopant diffusion from the highly doped contact layers <b>102</b>, <b>106</b> and <b>112</b>, <b>116</b> into the undoped/intrinsic layers <b>104</b>, <b>114</b>, as discussed further above. That is, the superlattice material advantageously allows the desired doping profiles to be created for an RTD structure, with a high concentration of doping near the contacts and little or no doping in RTD regions, with relatively precise process control. Moreover, the superlattice material also provides for strain buffer capability for hetero epitaxial film growth, as well as a strain buffer effect for lattice mismatch of hetero epitaxial films.

0058Referring additionally to <figref idref="f0008">FIGS. 7A-8B</figref>, other examples of N-type and P-type DBRTD structures <b>120</b>, <b>130</b> are shown along with their respective band diagrams <b>121</b>, <b>131.</b> In contrast to the DBRTD structures <b>100</b>, <b>110</b> described above, the DBRTD structures <b>120</b>, <b>130</b> illustratively include upper SiO₂ barrier layers <b>125</b>, <b>135</b> instead of upper superlattice barrier layers. More particularly, the N-type DBRTD <b>120</b> illustratively includes (starting from the bottom of the stack) a bottom n+ Si contact layer <b>122</b>, a superlattice barrier layer <b>123</b>, an undoped (intrinsic) Si layer <b>124</b>, the SiO₂ upper barrier layer <b>125</b>, and an upper n+ polysilicon contact layer <b>126</b>. Similarly, the P-type DBRTD <b>130</b> illustratively includes (starting from the bottom of the stack) a bottom p+ Si contact layer <b>132</b>, an superlattice barrier layer <b>133</b>, an undoped (intrinsic) Si layer <b>134</b>, an SiO₂ barrier layer <b>135</b>, and an upper p+ polysilicon contact layer <b>136</b>. The SiO₂ layers <b>125</b>, <b>135</b> may be formed in a similar fashion to the way in which oxygen monolayers are formed during the MST monolayer deposition, but with a longer exposure time and/or higher dosage so that more Si bonding sites are populated with O atoms to form SiO₂. In these examples, the upper n+ and p+ Si contact layers <b>126</b>, <b>136</b> are polysilicon because they are formed on SiO₂, as opposed to the single crystal Si layers <b>106</b>, <b>116</b> which may be epitaxially grown on the superlattice layers <b>105</b>, <b>115</b>, as described above.

0059Turning to <figref idref="f0009">FIGS. 9A-10B</figref>, example P-type DBRTD structures <b>140</b>, <b>150</b> are now described which are respectively similar to the P-type structures <b>110</b> and <b>130</b> shown in <figref idref="f0007">FIGS. 6A</figref> and <figref idref="f0008">8A</figref>, with the exception of a Ge tunneling layer <b>144</b>, <b>154</b> in place of the undoped (intrinsic) Si layers <b>114</b>, <b>134</b> in the previous embodiments. Integration of thin Ge film into Si advantageously allows for a VB offset for appropriate applications. In some embodiments, silicon germanium (e.g., a Si_1-xGe_x layer, where x=0∼1.0) may also be used for the layers <b>144</b>, <b>154</b>.

0060The P-type DBRTD <b>140</b> illustratively includes (starting from the bottom of the stack) a bottom p+ Si contact layer <b>142</b>, a first superlattice barrier layer <b>143</b>, an undoped (intrinsic) Ge tunneling layer <b>144</b>, a second superlattice barrier layer <b>145</b>, and an upper p+ Si contact layer <b>146</b>. In the second example, the P-type DBRTD <b>150</b> illustratively includes (starting from the bottom of the stack) a bottom p+ Si contact layer <b>152</b>, a superlattice barrier layer <b>153</b>, an undoped (intrinsic) Ge layer <b>154</b>, an SiO₂ layer <b>155</b>, and an upper p+ polysilicon Si contact layer <b>156</b>. These same structures may instead be formed with n+ contact layers as well, as will be appreciated by those skilled in the art.

0061Turning now to <figref idref="f0010 f0011">FIGS. 11A-13B</figref>, three examples of resonant inter-band tunneling diodes (RITDs) <b>160</b>, <b>170</b>, <b>180</b> are shown along with their respective band diagrams <b>161</b>, <b>171</b>, <b>181</b>, which respectively have layer structures similar to those shown in <figref idref="f0007">FIGS. 5A</figref>, <figref idref="f0008">7A</figref>, and <figref idref="f0009">9A</figref>, with the difference being that the upper and lower contact layers in the current examples are oppositely doped (i.e., doped with opposite conductivity type dopants). More particularly, in the first example the diode <b>160</b> illustratively includes (starting from the bottom of the stack) a bottom p+ Si contact layer <b>162</b>, a first superlattice barrier layer <b>163</b>, an undoped (intrinsic) Si layer <b>164</b>, a second superlattice barrier layer <b>165</b>, and an n+ Si upper contact layer <b>166</b>. In the second example, the diode <b>170</b> illustratively includes (starting from the bottom of the stack) a bottom p+ Si contact layer <b>172</b>, an superlattice barrier layer <b>173</b>, an undoped (intrinsic) Si layer <b>174</b>, a SiO₂ barrier layer <b>175</b>, and an upper n+ polysilicon contact layer <b>176</b>. The third example illustratively includes (starting from the bottom of the stack) a bottom p+ Si contact layer <b>182</b>, a first superlattice barrier layer <b>183</b>, an undoped (intrinsic) Ge layer <b>184</b>, a second superlattice barrier layer <b>185</b>, and an n+ Si upper contact layer <b>186</b>.

0062Turning now to <figref idref="f0012 f0013">FIGS. 14-16</figref>, and 23, three additional example RTD structures <b>190</b>, <b>210</b>, and <b>230</b> are provided which are respectively similar to the three examples shown in <figref idref="f0007">FIGS. 5A</figref>, <figref idref="f0009">9A and 10A</figref>, but which further include additional electron mean free path control layers. More particularly, the first example is an N-type DBRTD illustratively including (starting at the bottom of the stack) an n+ Si contact layer <b>191</b>, a first superlattice layer <b>192</b>, a first undoped Si layer <b>193</b>, a second superlattice layer <b>194</b>, a second undoped Si layer <b>195</b>, a third superlattice layer <b>196</b>, a third undoped Si layer <b>197</b>, a fourth superlattice layer <b>198</b>, and an upper n+ Si contact layer <b>199</b> (note that this structure may have p+ contact layers as well in different embodiments). The superlattice layers <b>194</b>, <b>196</b> serve as potential barrier layers, and the pairs of layers <b>192/193</b> and <b>197/198</b> respectively define electron mean free path control layers <b>200</b>, <b>201</b>.

0063The second example is a P-type DBRTD <b>210</b> illustratively including (starting from the bottom of the stack) a bottom p+ Si contact layer <b>211</b>, a first superlattice layer <b>212</b>, a first undoped Si layer <b>213</b>, a second superlattice layer <b>214</b>, an undoped Ge (or SiGe) layer <b>215</b>, a third superlattice layer <b>216</b>, a second undoped Si layer <b>217</b>, a fourth superlattice layer <b>218</b>, and an upper p+ contact layer <b>219</b> (note that this structure may have N-type contact layers in different embodiments). The superlattice layers <b>214</b>, <b>216</b> serve as potential barrier layers, and the pairs of layers <b>212/213</b> and <b>217/218</b> respectively define electron mean free path control layers <b>220</b>, <b>221.</b>

0064The third example is an RITD <b>230</b> which illustratively includes (starting from the bottom of the stack) a p+ Si bottom contact layer <b>231</b>, a first superlattice layer <b>232</b>, a first undoped Si layer <b>233</b>, a second superlattice layer <b>234</b>, a second undoped Si layer <b>235</b>, a third superlattice layer <b>236</b>, a third undoped Si layer <b>237</b>, a fourth superlattice layer <b>238</b>, and an upper n+ Si contact layer <b>239</b> (note that the conductivities of the bottom and upper contact layers may be reversed in other embodiments). The superlattice layers <b>234</b>, <b>236</b> serve as potential barrier layers, and the pairs of layers <b>232/233</b> and <b>237/238</b> respectively define electron mean free path control layers <b>240</b>, <b>241</b>.

0065Turning now to <figref idref="f0014">FIG. 17</figref>, one example application for replacing at least a portion of a tungsten (W) plug <b>271</b> in a CMOS FINFET device <b>270</b> with one or more of RTD structures <b>272</b> such as those described above is shown. It should be noted that RTD structure(s) <b>272</b> may be used in planar semiconductor devices as well.

0066Referring to <figref idref="f0014">FIG. 18</figref>, in another example embodiment a MOBILE device illustratively includes a DBRTD <b>281</b> as described above and a second diode <b>282</b> (which may also be a DBRTD as described above in some embodiments) coupled in series between a clock signal Clock and ground. Furthermore, a transistor <b>283</b> has its source and drain coupled to the first and second contacts of the diode <b>282</b>, and its gate coupled to an input signal IN. An output signal OUT is provided at the point where the diodes <b>281</b>, <b>282</b> are coupled together.

0067An example CMOS process flow in which a superlattice RTD module may be included to form the above-described superlattice RTD structures within CMOS devices is shown in the flow diagram <b>290</b> of <figref idref="f0015">FIG. 19</figref>. The process begins with a shallow trench isolation (STI) module <b>291</b>, followed by a well module <b>292</b>, a gate module <b>293</b>, a lightly doped drain (LDD) module <b>294</b>, a spacer and source/drain module <b>295</b>, a silicide module <b>296</b>, a contact/M1 module <b>297</b>, and a back end of line (BEOL) module <b>298</b>. More particularly, in the illustrated example, the DBRTD formation occurs within the silicide module <b>296</b>, in that after an oxide chemical vapor deposition (CVD), the MST RTD module is inserted, which includes another (optional) oxide CVD, chemical mechanical polishing (CMP), RTD contact patterning, and superlattice RTD epitaxy to create the desired RTD device (which may be done in either a blanket form across an entire wafer (MST1) or selectively at different locations on the water (MST2) with an optional CMP). The silicide module <b>296</b> further illustratively includes silicide block mask patterning which includes lithography, etching, and photoresist (PR) removal, then silicide metal physical vapor deposition (PVD) including a pre-clean and sputter, followed by silicide rapid thermal anneal(s) (RTA), and metal removal via wet etch, for example. It should be noted that certain steps and modules may be performed in different orders in different embodiments, depending upon the type of semiconductor device being created.

0068Various devices may be created using the above-described structures and processes. One such device is a tunneling-based SRAM (TSRAM) cell. Using the above-described techniques, a smaller than conventional 6T-SRAM cell (∼150F²) may be produced having less power consumption than conventional DRAM cells (4∼8F²). Applicability to multi-bit cells may be provided by increasing the number of RTDs, for example.

0069Other logic circuit elements in which the above-described DBRTDs may be implemented include FETs and BJTs. One potential benefit of such configurations may include high-speed operation, as tunneling time scale is within pico seconds. Another potential benefit is relatively low power operation, because transition currents during state change may be limited by valley current. For example, greater than 50% reduction of circuit elements may be realized in some instances for implementing a given function, and the I-V curve of NDR devices intersects with other device's load line (at least) twice.

0070As noted above, another advantageous application for the DBRTDs described herein is a MOBILE logic element. The RTD not only compacts the memory and logic circuitry, but it may also add new functionality. Moreover, integration of the DBRTD structures into standard Si CMOS may help change future circuit design from a system level. For example, this may enable "neuron network" logic replacing conventional Boolean logic. Moreover, this may allow for an immediate impact by hybrid integration with conventional logic (pipelined ripple carry adder, as an example).

0071Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.