Liquid crystal display apparatus

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a liquid crystal display apparatus.

Description of the Related Art

<patcit id="pcit0001" dnum="US6727872B"><text>U.S. Patent No. 6,727,872</text></patcit> discloses an image processing method for reducing a potential difference corresponding to a gradation level (or value) between black and white in the adjacent pixel so as to reduce disclination, which means a liquid crystal molecular orientation failure.

In order to restrain the disclination using the method disclosed in <patcit id="pcit0002" dnum="US6727872B"><text>U.S. Patent No. 6,727,872</text></patcit> to a permissible level, an adjustment is required to gradually change potential differences of several to dozens of pixels on edges of an image and thus makes dull the edge of the image (or lowers the sharpness of the image). This problem is conspicuous in a liquid crystal display apparatus of a micro display type, such as a projection-type display apparatus, because its pixel size is small. In addition, there is a demand for preventing the discontinuous or uneven brightness in an image.

SUMMARY OF THE INVENTION

The prevent invention provides a liquid crystal display apparatus that can reduce disclination as well as restraining image quality deterioration.

The present invention in its first aspect provides a liquid crystal display apparatus as specified in claims 1 to 6.

Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idref="f0001">FIG. 1</figref> is a perspective overview of a liquid crystal projector (liquid crystal display apparatus), to which the present invention is applicable.

<figref idref="f0001">FIG. 2</figref> is a block diagram of the liquid crystal projector illustrated in <figref idref="f0001">FIG. 1</figref>.

<figref idref="f0002">FIG. 3</figref> is a block diagram of a feature amount generator illustrated in <figref idref="f0001">FIG. 2</figref>.

<figref idref="f0003">FIGs. 4A-4C</figref> are views for explaining an operation of the feature amount generating circuit illustrated in <figref idref="f0002">FIG. 3</figref>.

<figref idref="f0004">FIGs. 5A and 5B</figref> are graphs for explaining a correction characteristic of a gradation value performed by a level corrector illustrated in <figref idref="f0001">FIG. 2</figref>.

<figref idref="f0005">FIG. 6</figref> is a flowchart for explaining an operation of a CPU illustrated in <figref idref="f0001">FIG. 2</figref> according to first, second, and third embodiments.

<figref idref="f0006">FIGs. 7A and 7B</figref> are correction value tables of S1103 illustrated in <figref idref="f0005">FIG. 6</figref> according to the first, second, and third embodiments.

<figref idref="f0007">FIGs. 8A and 8B</figref> are views for explaining image processing according to the third embodiment.

<figref idref="f0008">FIG. 9</figref> is a flowchart for explaining another operation of the CPU illustrated in <figref idref="f0001">FIG. 2</figref> according to a fourth embodiment.

<figref idref="f0008">FIG. 10</figref> is an explanatory view relating to a scan area when the feature amount generating circuit generates a feature amount.

<figref idref="f0009">FIG. 11</figref> is a flowchart of generating a feature amount.

DESCRIPTION OF THE EMBODIMENTS

<figref idref="f0001">FIG. 1</figref> is a perspective overview of a liquid crystal projector 100 (liquid crystal display apparatus) configured to display an input image signal using a liquid crystal display element, to which the present invention is applicable. An image signal output from a video player 2 is input into the liquid crystal projector 100 through a video cable 4. The liquid crystal projector 100 is an image projecting apparatus configured to project, as a projected image 8, light modulated by a liquid crystal display element, such as a liquid crystal panel, in accordance with an input image signal, onto a screen 6 (a surface to be projected).

<figref idref="f0001">FIG. 2</figref> is a block diagram of the liquid crystal display apparatus 100. The liquid crystal display apparatus 100 includes an image processor 10, a feature amount generator 20, a CPU 30, a level corrector 40, a liquid crystal driver 50, and an optical system 60.

The image processor 10 performs processing for an input image signal, such as a brightness correction, a contrast correction, a gamma correction, and a chromatic conversion.

The feature amount generator 20 is connected to the image processor 10, and generates a feature amount that numerically represents an incidence state of a disclination in the image signal output from the image processor 10.

<figref idref="f0002">FIG. 3</figref> is a block diagram of the feature amount generator 20. The feature amount generator 20 includes a delay circuit 22, a line memory 24, a feature amount generating circuit 26, and a random access memory ("RAM") 28.

The delay circuit 22 stores data of the input image signal into the line memory 24, delays it, and then reads it out. The line memory 24 stores data of the input image signal for maximum three horizontal lines. The delay circuit 22 reads gradation data for past two horizontal lines from the line memory 24, and inputs it into the feature amount generating circuit 26. The feature amount generating circuit 26 generates a feature amount, and stores it in the RAM 28. The feature amount stored in the RAM 28 contains information based on the number of pixel pairs that satisfy a correspondence relationship between a gradation value of a target pixel and a gradation value of a surrounding pixel around the target pixel. According to this embodiment, the feature amount is expressed in tables illustrated in <figref idref="f0003">FIGs. 4B and 4C</figref>.

Turning back to <figref idref="f0001">FIG. 2</figref>, the CPU 30 is connected to the feature amount generator 20 and the level corrector 40, and includes a memory (storage) (not illustrated) configured to store a correction value table illustrated in <figref idref="f0006">FIGs. 7A and 7B</figref> and a control method illustrated in <figref idref="f0005">FIG. 6</figref>, which will be described later. The CPU 30 is a microcomputer (processor) configured to read out a feature amount from the RAM 28 in the feature amount generator 20, to set the level correction amount (correction parameter) to the level corrector 40 in accordance with the feature amount, and to control a power or a condition of each component in the liquid crystal projector 100.

The level corrector 40 is connected to the feature amount generator 20 and the CPU 30. The level corrector 40 corrects a level in the image signal so as to reduce the disclination.

The liquid crystal driver 50 is connected to the level corrector 40, converts the image signal corrected by the level corrector 40 into a liquid crystal driving signal, and drives the liquid crystal display element 66 in the optical system 60.

The optical system 60 includes a lamp 62, an illumination optical system 64, a liquid crystal display element 66, and a projection optical system 68. The light emitted from the lamp 62 passes the illumination optical system 64, is modified by the liquid crystal display element 66, and is projected onto the screen 6 as the projected image 8 through the projection optical system (projection lens) 68. The liquid crystal display element 66 is connected to the liquid crystal driver 50, and modifies the incident light flux based on the liquid crystal driving signal from the liquid crystal driver 50.

FIRST EMBODIMENT

In the first embodiment, the CPU 30 commonly sets a disclination correcting amount to the overall image to the level corrector 40. <figref idref="f0003">FIG. 4A</figref> illustrates an arbitrary 3 x 3 pixel matrix in the image expressed by the image signal. <figref idref="f0003">FIG. 4B</figref> illustrates a table representative of a white-side feature amount (where "w" in Nw means white). <figref idref="f0003">FIG. 4C</figref> illustrates a table representative of a black-side feature amount (where "bk" in Nbk means black).

Since there are eight bits in this embodiment, a white's gradation level (gradation value) is 255, which corresponds to 8V. A black's gradation level is 0, which corresponds to 0V. The table representative of the white-side feature amount is a table used when the gradation value of the target pixel is close to 255. The table representative of the black-side feature amount is a table used when the gradation value of the target pixel is close to 0.

In the first embodiment, the feature amount generating circuit 26 compares the gradation value of the target pixel A illustrated in <figref idref="f0003">FIG. 4A</figref> with the gradation values of the surrounding pixels B₁ to B₈ around the target pixel A, and counts the number of feature amounts classified in matrices illustrated in <figref idref="f0003">FIGs. 4B and 4C</figref>.

There are eight surrounding pixels B₁ to B₈ in <figref idref="f0003">FIG. 4A</figref>, but one or more of pixels among these pixels B₁ to B₈ may be selected as a compared object according to the initial liquid crystal molecular orientation state and the driving mode. This embodiment sets two surrounding pixels B₂ and B₅ to the compared objects, and the feature amount is obtained by comparing the gradation values of these two surrounding pixels B₂ and B₅ with the gradation value of the target pixel.

<figref idref="f0008">FIG. 10</figref> is an explanatory diagram relating to a scan area when the feature amount generator 20 generates a feature amount, and illustrates a relationship between a display area of the liquid crystal display element and a coordinate of the target pixel A. <figref idref="f0008">FIG. 10</figref> illustrates the liquid crystal display element having a resolution comprised of H pixels in the horizontal direction and V pixels in the vertical direction. Herein, assume a coordinate system having an origin at the upper left corner pixel in the display area. The target pixel A is defined as a coordinate (Ax, Ay), which may be other than the outermost coordinates in the display area.

<figref idref="f0009">FIG. 11</figref> illustrates an operational flow of the feature amount generator 20.

S1501 is started with a trigger of a signal in synchronization with a frame of each input image. A first target pixel is set as (Ax, Ay)=(1, 1) which is retreated inside by one pixel each from the upper left corner pixel in the image.

In S1502, the gradation of the target pixel A is compared with that of B₂.

In S1503, when the conditions illustrated in <figref idref="f0003">FIGs. 4B and 4C</figref> are met, values made by adding 1 to the feature amounts Nw_ij and Nbk_ij that satisfy the condition are written down in the RAM 28 (where each of i and j is a natural number selected from 1 to 5).

Similar to S1502 and S1503, the qualified feature amounts are added in S1504 and S1505 after the gradation of the target pixel A is compared with that of B₅.

In S1506 and S1507, whether processing from S1502 to S1506 has been performed for the overall area for which the feature amount is generated.

A description will now be given of a calculative example of a specific feature amount. For instance, when the gradation value of the target pixel A is 215, the position is the uppermost row position in <figref idref="f0003">FIG. 4B</figref>, and when the gradation value of the surrounding pixel B₂ is 185, the feature amount generating circuit 26 adds 1 to the value of Nw_11. The feature amount generating circuit 26 adds 1 to the value of Nw_11 when the gradation value of the surrounding pixel B₅ is 185. The feature amount generating circuit 26 adds 1 to the value of Nw_12 when the gradation value of the surrounding pixel B₅ is 195. Another uncounted element, such as Nw_13, remains 0 in <figref idref="f0003">FIGs. 4B and 4C</figref> since nothing is added to it.

Similarly, the feature amount generating circuit 26 sequentially sets the target pixel A to each of all pixels in the image, produces data illustrated in <figref idref="f0003">FIGs. 4B and 4C</figref> in superimposed (added) states, and generates a feature amount of the disclination in the image signal. In other words, the feature amount generating circuit 26 generates the number of pixel pairs that satisfy the correspondence in the table, and the feature amount in this embodiment represents a relationship among the gradation value of the target pixel A and the gradation value of the surrounding pixel and the number of surrounding pixels.

This embodiment adopts two types of tables: One type is a table (matrix) illustrated in <figref idref="f0003">FIG. 4B</figref> which represents a combination between the white gradation (gradation 255) or almost white gradation and the intermediate gradation of the adjacent pixel level. The other type is a conditional matrix illustrated in <figref idref="f0003">FIG. 4C</figref> which represents a combination between the black gradation (gradation 0) or almost black gradation and the intermediate gradation of the adjacent pixel level. However, the classification of the condition is not limited to this embodiment. For example, the number of rows and the number of columns in the conditional matrix may be increased or three types or more of conditional matrices may be used.

The level corrector 40 is a circuit having an input/output characteristic illustrated in <figref idref="f0004">FIG. 5A</figref>, and a blacks-side offset amount 701 and a white-side offset amount 702 are configured independently settable from the outside. The level corrector 40 reduces a dynamic range of the driving voltage of the liquid crystal display element 66. The abscissa axis in <figref idref="f0004">FIG. 5A</figref> denotes a gradation value of the input image, and its ordinate axis denotes a gradation value of the output image. The offset amounts 701 and 702 serve as correction amounts. The dynamic range is reduced by decreasing the maximum value of the driving voltage used to drive the liquid crystal or by increasing the minimum value or by the combination thereof. Reducing of the dynamic range of the driving voltage means reducing of the dynamic range of the gradation value in the input image signal.

<figref idref="f0004">FIG. 5B</figref> is a graph illustrating a relationship between an input gradation value and display brightness in the general liquid crystal display element, and nonlinear characteristics can be seen near white (with brightness of 1) and near black (with brightness of 0) in which the brightness variation ratio to the input gradation is very small. Since the brightness variation of the displayed image is small, the influence upon the displayed image by the reduced dynamic range of the driving voltage is little recognized even when the dynamic range of the driving voltage is reduced by the black-side offset amount 701 and the white-side offset amount 702. In the meanwhile, although <figref idref="f0004">FIG. 5B</figref> illustrates the offset amounts 701, 702 are about 130 and 50, this embodiment sets the offset amount 701 to about 5 and the offset amount 702 to about 7.

The set values of the reducing offset amounts 701, 702 of the dynamic range of the driving voltage may be set based on the characteristic representative of the relationship between the input gradation and the brightness of the liquid crystal display element so that the black-side offset amount 701 can be larger than the white-side offset amount 702. This configuration can restrain the brightness variation and more effectively reduce the disclination.

<figref idref="f0005">FIG. 6</figref> is a flowchart for explaining an operation of the CPU 30 according to the first embodiment, and "S" stands for a step. The flowchart illustrated in <figref idref="f0005">FIG. 6</figref> is implemented as a computer executable program.

In the initial state, both of the offset amounts 701, 702 are set to 0, and stored in the memory (not illustrated). In other words, the correction value at the initial state is 0 and, in this case, the characteristic illustrated in <figref idref="f0004">FIG. 5A</figref> is a diagonal line of Out=In.

The CPU 30 first sets x=1 and y=1 (S1101), and reads the feature amounts illustrated in <figref idref="f0003">FIGs. 4B and 4C</figref> from the RAM 28 (S1102). Next, the CPU 30 determines whether the value of the white-side feature amount (Nw_11) illustrated in <figref idref="f0003">FIG. 4B</figref> is larger than or equal to or smaller than a first threshold 10,000 (S1103).

When the CPU 30 determines that the number of white-side feature amounts (Nw_11) is larger than the threshold of 10,000, the CPU 30 obtains a reference value by referring to the correction value table illustrated in <figref idref="f0006">FIGs. 7A and 7B</figref> (S1104). <figref idref="f0006">FIG. 7A</figref> is a table for the white-side correction value corresponding to the offset amount 702 illustrated in <figref idref="f0004">FIGs. 5A and 5B</figref>, and <figref idref="f0006">FIG. 7B</figref> is a table for the black-side correction corresponding to the offset amount 701 illustrated in <figref idref="f0004">FIGs. 5A and 5B</figref>. Since the correction value (offset amount) corresponding to Nw_11 is 1, the CPU 30 obtains this as a reference value.

Next, the CPU 30 determines whether the reference value is larger than the current correction value (S1105), and if so replaces the current value (S1106). As discussed above, in the initial state, the correction value is 0, and the reference value of 1 is larger. Thus, the CPU 30 sets and stores in the memory (not illustrated) the reference value of 1 as a current correction value.

After NO of S1103, NO of S1105 or S1106, the CPU 30 determines whether there is another non-investigated combination of x and y (where x=1 to 5 and y=1 to 5) (S1107). When there is another x and y combination, x or y is incremented (S1108) and the flow returns to S1102.

For example, when the CPU 30 determines the white-side feature amount (Nw_12) is larger than the first threshold 10,000 (S1103), the CPU 30 refers to the correction table illustrated in <figref idref="f0006">FIG. 7A</figref> and obtains the reference value 2 corresponding to Nw_12 (S1104). Then, the CPU 30 determines whether the reference value 2 is larger than the current correction value 1 (S1105), and since it is larger than the current correction value 1, the CPU 30 replaces it with the correction value 2 (S1106).

When the CPU 30 determines that it has obtained feature amounts for all combinations of x and y (S1107), the CPU 30 determines the white-side offset amount 702 (S1109). Herein, the maximum correction value is set for all the combinations of x and y, and this becomes the white-side offset amount 702.

The CPU 30 performs a similar flow for the black-side feature amount (Nbk_xy) so to as determine the black-side correction amount, and determines the black-side offset amount 701 (S1110 to S1118). Finally, the CPU 30 sets the determined correction amounts (offset amounts 701, 702) to the level corrector 40 (S1119).

The conventional process sets the correction value only for an edge of an image in which the disclination occurs rather than for the entire image, and an image deterioration problem occurs, such as reduced sharpness.

On the other hand, in this embodiment, the CPU 30 performs processing for the entire image so as to set a correction value that reduces the dynamic range of the gradation value of the input image signal when the feature amount is larger than the first threshold, and so as not to set the correction value when the feature amount is equal to or smaller than the first threshold. Therefore, the image deterioration can be reduced.

This embodiment can display an image in which the disclination is reduced without discontinuing a gradation value at an edge of an image (therefore without damaging the sharpness). Of course, an area of the image processing may be set to a rectangular shape having one hundred pixels or more in one side.

The CPU 30 may performs weighing based on image correcting priority by differently setting the thresholds of S1103 and S1112 in accordance with feature amount indices x and y. In addition, while S1105 and S1114 adopt the maximum correction value, these values may be weighed in accordance with the feature amount indices x and y.

The feature amount generating circuit 26 generates the feature amount by counting the number of pixel pairs that satisfy the combination of the table illustrated in <figref idref="f0003">FIGs. 4B and 4C</figref>, the method of generating the feature amount is limited to this embodiment. For example, the feature amount may be set to a value of an evaluation function that uses, as a variable, the existence of the pixel that satisfies the combinational condition of the table illustrated in <figref idref="f0003">FIG. 4B or 4C</figref>.

SECOND EMBODIMENT

The second embodiment divides the image into a plurality of rectangular areas, and commonly sets the correction amount of the disclination to each area to the level corrector 40. While the second embodiment thus divides the display image into a plurality of areas, one side of each area may be 100 pixels or more so as to maintain the sharpness.

The apparatus structure applied to the second embodiment is similar to that illustrated in <figref idref="f0001 f0002">FIGs. 1 to 3</figref> of the first embodiment. In addition, in the second embodiment, the feature amount illustrated in <figref idref="f0003">FIGs. 4B and 4C</figref> are generated for each area. The flow performed by CPU 30 is similar to that illustrated in <figref idref="f0005">FIG. 6</figref>. Nevertheless, the offset amounts 701, 702 set in S1109 and S1118 is the offset amount for the entire image in the first embodiment, whereas they are set for each area in the second embodiment.

This embodiment changes the dynamic range of the gradation value for each section having 100 pixels or more, and can display an image in which the sharpness is maintained to some extent and the disclination is reduced.

THIRD EMBODIMENT

The third embodiment is similar to the second embodiment in that the image is divided into a plurality of areas, each of which has 100 pixels in one side. However, in the second embodiment, the discontinuous brightness may occur at the boundary between an area in which the disclination is corrected and an area in which the disclination is not corrected. Therefore, the third embodiment is different from the second embodiment in that the third embodiment performs image processing so as to provide a smoothly continuous change of the brightness.

According to third embodiment, as illustrated in <figref idref="f0007">FIG. 8A</figref>, the displayed area is divided into a plurality of (16 x 10) areas, but the CPU 30 does not commonly set a disclination correcting amount to each area, to the level corrector 40.

The apparatus structure applied to the third embodiment is similar to that illustrated in <figref idref="f0001 f0002">FIGs. 1 to 3</figref> in the first embodiment. In addition, in the third embodiment, the feature amount illustrated in <figref idref="f0003">FIGs. 4B and 4C</figref> is generated for each area. The flow performed by the CPU 30 is similar to that illustrated in <figref idref="f0005">FIG. 6</figref>. Nevertheless, in the first embodiment, the offset amounts 701 and 702 set in S1109 and S1118 are offset amounts for the entire image, whereas they are set for the central coordinate of each area in the third embodiment.

In other words, according to the third embodiment, the offset amount for the central coordinate of each area is set by the flow of illustrated in <figref idref="f0005">FIG. 6</figref>, and another offset of the coordinate is set as illustrated in <figref idref="f0007">FIG. 8B</figref>.

In <figref idref="f0007">FIG. 8B</figref>, 801a to 804a denote central coordinates of areas 801 to 804 illustrated in <figref idref="f0007">FIG. 8A</figref>. of fset_a00 is a correction amount that contains information of the offset amounts 701, 702 set for the central coordinate 801a of the area 801 in the flow illustrated in <figref idref="f0005">FIG. 6</figref>. offset_a01 is a correction amount that contains information of the offset amounts 701, 702 set for the central coordinate 802a of the area 802 in the flow illustrated in <figref idref="f0005">FIG. 6</figref>. offset_al0 is a correction amount that contains information of the offset amounts 701, 702 set for the central coordinate 803a of the area 803 in the flow illustrated in <figref idref="f0005">FIG. 6</figref>. offset_a11 is a correction amount that contains information of the offset amounts 701, 702 set for the central coordinate 804a of the area 804 in the flow illustrated in <figref idref="f0005">FIG. 6</figref>.

At this time, an offset of an arbitrary coordinate (i,j) is found from the following expressions: When the offset amount is not a positive number, the CPU 30 of this embodiment converts the offset amount into a positive value by rounding. Next, the CPU 30 sets the offset amount obtained for each coordinate, to the level corrector 40: <maths id="math0001" num="expression 1"><math display="block"><mi>offset_h</mi><mo>⁢</mo><mn mathvariant="normal">0</mn><mo mathvariant="normal">=</mo><mi>offset_a</mi><mo>⁢</mo><mn mathvariant="normal">00</mn><mo mathvariant="normal">+</mo><mfrac><mi mathvariant="normal">i</mi><mi>Di</mi></mfrac><mo>⁢</mo><mfenced separators=""><mi>offset_a</mi><mo>⁢</mo><mn mathvariant="normal">01</mn><mo mathvariant="normal">-</mo><mi>offset_a</mi><mo>⁢</mo><mn mathvariant="normal">00</mn></mfenced></math><img file="EP2503539A2_D0001.tif" /></maths><maths id="math0002" num="expression 2"><math display="block"><mi>offset_h</mi><mo>⁢</mo><mn mathvariant="normal">1</mn><mo mathvariant="normal">=</mo><mi>offset_a</mi><mo>⁢</mo><mn mathvariant="normal">10</mn><mo mathvariant="normal">+</mo><mfrac><mi mathvariant="normal">i</mi><mi>Di</mi></mfrac><mo>⁢</mo><mfenced separators=""><mi>offset_a</mi><mo>⁢</mo><mn mathvariant="normal">11</mn><mo mathvariant="normal">-</mo><mi>offset_a</mi><mo>⁢</mo><mn mathvariant="normal">10</mn></mfenced></math><img file="EP2503539A2_D0002.tif" /></maths><maths id="math0003" num="expression 3"><math display="block"><mi>offset_ij</mi><mo mathvariant="normal">=</mo><mi>offset_h</mi><mo>⁢</mo><mn mathvariant="normal">0</mn><mo mathvariant="normal">+</mo><mfrac><mi mathvariant="normal">j</mi><mi>Dj</mi></mfrac><mo>⁢</mo><mfenced separators=""><mi>offset_ah</mi><mo>⁢</mo><mn mathvariant="normal">1</mn><mo mathvariant="normal">-</mo><mi>offset_h</mi><mo>⁢</mo><mn mathvariant="normal">1</mn></mfenced></math><img file="EP2503539A2_D0003.tif" /></maths>

Herein, "i" denotes a distance in the horizontal direction and "j" denotes a distance in the vertical direction from a central coordinate of a certain area to a coordinate at an arbitrary position. Dx denotes a distance in the horizontal direction and Dy denotes a distance in the vertical direction between adjacent areas. offset_a** denotes a correction value of a central coordinate of a certain area. of fset_h* denotes a value found through the interpolation calculation in the horizontal direction. offset_ij is a correction amount at an arbitrary coordinate determined by the interpolation calculation.

This embodiment also performs processing that sets a correction value for the entire image, and can display an image in which the disclination is reduced and the sharpness is maintained to some extent, instead of processing only for the edge of the image. In addition, this embodiment can obtain a natural image in which the level correction amount is smoothly connected through interpolations between the adjacent areas.

While this embodiment utilizes an interpolation operating means, another means may be used as long as an image generating means that does not cause the brightness discontinuity between areas. As a result of an investigation of the visual confirmation, the effect of this embodiment can be expected in the corrected image when the discontinuous brightness change generated associated with the image correction falls within 5% or 2% or 1% of the displayed maximum brightness.

FOURTH EMBODIMENT

The fourth embodiment is similar to the second and third embodiments in that the image is divided into a plurality of rectangular areas, each of which has one hundred pixels or more in one side. Even the image processing of the third embodiment may cause nonuniform brightness at the boundary between the area in which the disclination is corrected and the area in which the disclination is not corrected. Accordingly, the fourth embodiment performs image processing that corrects an area that does not require a correction of the disclination, so as to reduce the correctional difference from the area in which the disclination is corrected and to make the correctional difference unrecognized.

The apparatus structure applied to the fourth embodiment is similar to that illustrated in <figref idref="f0001 f0002">FIGs. 1 to 3</figref> of the first embodiment. In addition, in the fourth embodiment, the feature amount illustrated in <figref idref="f0003">FIGs. 4B and 4C</figref> are generated for each area. The flow performed by CPU 30 is similar to that illustrated in <figref idref="f0005">FIG. 6</figref>. Nevertheless, the offset amounts 701, 702 set in S1109 and S1118 are the offset amounts set to the central coordinate of each area similar to the third embodiment.

In the fourth embodiment, similar to the third embodiment, the display image is divided into a plurality of areas, but the CPU 30 does not commonly set the disclination correcting amount to each area to the level corrector 40.

<figref idref="f0008">FIG. 9</figref> is a flowchart for explaining an operation of the CPU 30 according to the fourth embodiment, and "S" stands for a step. The flowchart illustrated in <figref idref="f0008">FIG. 9</figref> is implemented as a computer executable program.

Initially, similar to the third embodiment, the CPU 30 obtains an offset amount for the central coordinate of each area as described in the third embodiment using the flow illustrated in <figref idref="f0005">FIG. 6</figref> (S1201). This embodiment is different from the third embodiment in that an obtained offset is a provisional offset amount in the fourth embodiment. In addition, the CPU 30 does not perform S1119 illustrated in <figref idref="f0005">FIG. 6</figref>.

Next, the CPU 30 searches the white-side offset amount 702 of the central coordinate of the entire area in the image for the maximum value and the minimum value (S1202), and determines whether a difference between the brightness corresponding to the maximum value and the brightness corresponding to the minimum value is larger than a second threshold 0.1 (10%) (S1203).

The second threshold of S1203 is not limited, and can be arbitrarily set. When the brightness difference between areas falls within 10%, 7%, or 5%, the uneven brightness is unlikely to stand out and the threshold in S1203 may be set so that the brightness difference cannot exceed one of the above values.

When determining that a difference between the maximum value and minimum value is larger than 10%, the CPU 30 modifies at least one of the maximum value and the minimum value because the correction amount difference between the areas is excessively large and the uneven brightness may be caused in the corrected image (S1204).

In case of No of S1203 or after S1204, the CPU 30 sets the offset amount to the level corrector 40 (S1205). S1205 corresponds to S1119. Thereafter, the offset amount at the coordinate other than the central coordinate of each area is set using Expressions 1 to 3 and the offset amount modified in S1204.

This embodiment performs processing that sets the correction value for the entire image instead of performing processing only for the edge of the image, and can also display an image in which the disclination is reduced and the sharpness is maintained to some extent. In addition, this embodiment can obtain a natural image in which the level correction amount is smoothly connected through interpolations between the adjacent areas. Moreover, this embodiment can provide a high-quality image with little uneven brightness.

This embodiment corrects the white-side offset amount 702 in which the uneven correction can be relatively visually recognized, but the black-side offset amount 701 may be similarly corrected.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.