Stacked half-bridge package with a common conductive leadframe

BACKGROUND OF THE INVENTION

0001The present application claims the benefit of and priority to a pending provisional application titled "Stacked Packaging Architecture with Reduced Form Factor and Increased Current Density with Application to Power Transistor Packaging," Serial Number <patcit id="pcit0001" dnum="US61461110B"><text>61/461,110 filed on January 14, 2011</text></patcit>. The disclosure in that pending provisional application is hereby incorporated fully by reference into the present application.

0002Moreover, application Serial No. <patcit id="pcit0002" dnum="US11986848B"><text>11/986,848, filed on November 27, 2007</text></patcit>, titled "DC/DC Converter Including a Depletion Mode Power Switch," now <patcit id="pcit0003" dnum="US7902809B"><text>U.S. Patent No. 7,902,809</text></patcit>; and pending applications Serial No. <patcit id="pcit0004" dnum="US12928102B"><text>12/928,102, filed on December 3, 2010</text></patcit>, titled "DC/DC Converter with Depletion-Mode III-Nitride Switches," and Serial No. <patcit id="pcit0005" dnum="US12927341B"><text>12/927,341, filed on November 12, 2010</text></patcit>, titled "Semiconductor Package with Metal Straps," are hereby incorporated fully by reference into the present application.

1.

FIELD OF THE INVENTION

0003The present invention relates generally to semiconductor devices. More particularly, the present invention relates to packaging of semiconductor devices.

2.

BACKGROUND ART

0004To allow for high efficiency power conversion, power converters, such as buck converters, commonly employ power switching circuits in which a high side power transistor and a low side power transistor are connected to form a half-bridge. One such power converter that is frequently employed is a synchronous buck converter, where the high side transistor is a control transistor and the low side transistor is a synchronous transistor. The control transistor and the synchronous transistor are typically formed on their respective separate dies, i.e. a control transistor die and a synchronous transistor die, that are connected in a package (i.e. co-packaged) to form the half-bridge.

0005One approach to connecting the control transistor and the synchronous transistor in a package would be to arrange the control transistor and the synchronous transistor side by side on a substrate, such as a printed circuit board (PCB). However, this arrangement would result in the package having a large footprint, as the package must be large enough to accommodate footprints of the control transistor and the synchronous transistor. Furthermore, conductive traces on the PCB could be used to connect the control transistor and the synchronous transistor so as to form the half-bridge package. However, the conductive traces would form long routing paths on the PCB, causing high parasitic inductance and resistance. Thus, this approach to packaging the control transistor and the synchronous transistor would result in a package having a large form factor where the package significantly degrades performance of the half-bridge.

0006What is needed is an approach to packaging control and synchronous transistors that is capable of achieving packages having a small form factor where the packages do not significantly degrade performance of the half-bridge.

SUMMARY OF THE INVENTION

0007A stacked half-bridge package with a common conductive leadframe, substantially as shown in and/or described in connection with at least one of the figures, and as set forth more completely in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

0008<ul id="ul0001" list-style="none" compact="compact"><li><figref idref="f0001">Figure 1</figref> shows an exemplary circuit schematic of a synchronous buck converter, according to one embodiment of the invention.</li><li><figref idref="f0002">Figure 2A</figref> illustrates a selective top view of a stacked half-bridge package, according to one embodiment of the invention.</li><li><figref idref="f0003">Figure 2B</figref> illustrates a selective top view of a stacked half-bridge package, according to one embodiment of the invention.</li><li><figref idref="f0004">Figure 2C</figref> illustrates a selective top view of a stacked half-bridge package, according to one embodiment of the invention.</li><li><figref idref="f0005">Figure 2D</figref> illustrates a cross sectional view of a portion of a stacked half-bridge package, according to one embodiment of the invention.</li></ul>

DETAILED DESCRIPTION OF THE INVENTION

0009The present application is directed to a stacked half-bridge package with a common conductive leadframe. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention. The specific details not described in the present application are within the knowledge of a person of ordinary skill in the art.

0010The drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments of the invention. To maintain brevity, other embodiments of the invention, which use the principles of the present invention, are not specifically described in the present application and are not specifically illustrated by the present drawings.

0011<figref idref="f0001">Figure 1</figref> shows an exemplary circuit schematic of synchronous buck converter 100 including half-bridge 102, which is formed in a stacked half-bridge package according to an embodiment of the invention, and is thus also referred to as "stacked half-bridge package" 102 or "half-bridge package" 102 in the present application. Synchronous buck converter 100 also includes, driver integrated circuit (IC) 104, output inductor 106, and output capacitor 108.

0012Half-bridge package 102 includes control transistor Q₁ and synchronous transistor Q₂ (also referred to as "sync transistor"), high voltage input terminal V_H, low voltage input terminal V_L, output terminal V_out, control gate terminal V_G1, and sync gate terminal V_G2.

0013In half-bridge package 102, high voltage input terminal V_H receives high voltage input V_HI, which can be, for example, a direct current (DC) voltage. Low voltage input terminal V_L receives low voltage input V_LI, which can be, for example, ground. Also in half-bridge package 102, control gate terminal V_G1 receives a control gate signal from driver IC 104 for driving control transistor Q₁. Similarly, sync gate terminal V_G2 receives a sync gate signal from driver IC 104 for driving sync transistor Q₂. Driver IC 104 may drive control transistor Q₁ and sync transistor Q₂ utilizing any suitable method. As a specific example, in one embodiment, driver IC 104 can vary a duty cycle of the sync and control gate signals responsive to a measurement of output voltage V_o of synchronous buck converter 100 to maintain a desired output voltage V_o, regardless of changes in high voltage input V_HI. It will be appreciated that in other embodiments, output voltage V_o is not measured in synchronous buck converter 100.

0014Control transistor Q₁ includes control source S₁, control drain D₁, and control gate G₁. Sync transistor Q₂ includes sync source S₂, sync drain D₂, and sync gate G₂. In various embodiments of the present invention, control transistor Q₁ and sync transistor Q₂ can be any combination of an enhancement more transistor and a depletion mode transistor. For example, in one embodiment, control transistor Q₁ and sync transistor Q₂ are both depletion mode transistors. Control transistor Q₁ and sync transistor Q₂ can be P-channel or N-channel transistors. Also, control transistor Q₁ and sync transistor Q₂ can be field-effect transistors (FETs). In one embodiment, at least one of control transistor Q₁ and sync transistor Q₂ is a silicon FET. However, at least one of control transistor Q₁ and sync transistor Q₂ may also comprise a non-silicon FET or any other FET in general. In one embodiment, at least one of control transistor Q₁ and sync transistor Q₂ is a metal-oxide-semiconductor field-effect transistor (MOSFET). At least one of control transistor Q₁ and sync transistor Q₂ can also be, as an example, a high electron mobility transistor (HEMT), such as a GaN HEMT.

0015Control transistor Q₁ has control drain D₁ for connection to high voltage input V_HI through high voltage input terminal V_H of half-bridge package 102. Control transistor Q₁ also has control source S₁ coupled to output terminal V_OUT of half-bridge package 102. Also, control transistor Q₁ has control gate G₁ coupled to control gate terminal V_G1 of half-bridge package 102 for being driven by driver IC 104.

0016Sync transistor Q₂ has sync drain D₂ for connection to output terminal V_OUT of half-bridge package 102. Sync transistor Q₂ also has sync source S₂ coupled to low voltage input V_LI through low voltage input terminal V_L of half-bridge package 102. Also, sync transistor Q₂ has sync gate G₂ coupled to sync gate terminal V_G2 of half-bridge package 102 for being driven by driver IC 104.

0017In some embodiments, at least one of control transistor Q₁ and sync transistor Q₂ can be connected to a diode. For example, <figref idref="f0001">Figure 1</figref> shows optional diodes 110 and 112. In the embodiment shown in <figref idref="f0001">Figure 1</figref>, diode 110 is coupled to control source S₁ and control drain D₁, such that diode 110 is in parallel with control transistor Q₁. Similarly, diode 112 is coupled to sync source S₂ and sync drain D₂, such that diode 112 is in parallel with control transistor Q₂. In some embodiments, at least one of diodes 110 and 112 can be connected with a reverse polarity to that shown in <figref idref="f0001">Figure 1</figref>. In various embodiments, diodes 110 and 112 can be internal to or external to control transistor Q₁ and sync transistor Q₂. As an example, in one embodiment, control transistor Q₁ and sync transistor Q₂ are MOSFETs and diodes 110 and 112 are respective body diodes of control transistor Q₁ and sync transistor Q₂.

0018Control transistor Q₁ and sync transistor Q₂ are commonly included on respective dies (i.e. a control transistor die and a synchronous transistor die). The respective dies may include other components, for example, diode 110 may be on the control transistor die and diode 112 may be on the synchronous transistor die. These other components may also be provided external to the respective dies and can be, for example, on a different die.

0019Synchronous buck converter 100 illustrates one power converter, which can benefit from including stacked half-bridge package 102, in accordance with embodiments of the present invention. However, half-bridge package 102 is not limited to being included in a synchronous buck converter and can be included in other types of power converters.

0020In accordance with embodiments of the present invention, control transistor Q₁ and sync transistor Q₂ can be connected in a stacked half-bridge package, which includes stacked half-bridge package 102, while achieving a small footprint with low parasitic inductance and resistance. Thus, the stacked half-bridge package can have a small form factor where the stacked half-bridge package does not significantly degrade performance of half-bridge 102.

0021<figref idref="f0002 f0003 f0004">Figures 2A-2C</figref> illustrate selective top views of stacked half-bridge package 202, corresponding to stacked half-bridge package 102 in <figref idref="f0001">Figure 1</figref>, in accordance with one embodiment of the present invention. Various features of stacked half-bridge package 202 are not shown in <figref idref="f0002 f0003 f0004">Figures 2A-2C</figref> for clarity of description. <figref idref="f0005">Figure 2D</figref> illustrates a cross sectional view of a portion of stacked half-bridge package 202, according to one embodiment of the invention. The cross sectional view shown in <figref idref="f0005">Figure 2D</figref> corresponds to a cross section along line 2D-2D in <figref idref="f0002 f0003 f0004">Figures 2A-2C</figref>.

0022<figref idref="f0002">Figure 2A</figref> shows control drain leadframe 220, control gate leadframe 222, common conductive leadframe 224, and sync transistor Q₂ of stacked half-bridge package 202. Sync transistor Q₂ in <figref idref="f0002 f0003 f0004 f0005">Figures 2A-2D</figref> corresponds to sync transistor Q₂ in <figref idref="f0001">Figure 1</figref>. Common conductive leadframe 224 is over sync transistor Q₂. In <figref idref="f0002">Figure 2A</figref>, dashed lines indicate portions of synch transistor Q₂ that would not otherwise be visible, as they are covered by common conductive leadframe 224. For example, an outline of synch transistor Q₂, which can be a semiconductor die, is depicted using a dashed line. Furthermore, sync transistor Q₂ includes sync source S₂ and sync gate G₂, which are depicted using dashed lines. Sync transistor Q₂ also includes sync drain D₂, a portion of which is shown in <figref idref="f0002">Figure 2A</figref>, as it is not fully covered by common conductive leadframe 224 in the present embodiment.

0023Sync source S₂ in stacked half-bridge package 202 corresponds to sync source S₂ in <figref idref="f0001">Figure 1</figref>, sync gate G₂ in stacked half-bridge package 202 corresponds to sync gate G₂ in <figref idref="f0001">Figure 1</figref>, and sync drain D₂ in stacked half-bridge package 202 corresponds to sync drain D₂ in <figref idref="f0001">Figure 1</figref>. In the present embodiment, sync transistor Q₂ has top and bottom surfaces, which are opposite one another. Sync drain D₂ is on the top surface and sync source S₂ and sync gate G₂ are on the bottom surface.

0024Also in the present embodiment, sync drain D₂ is provided with a sync drain pad that substantially covers an entirety of the top surface of sync transistor Q₂. Furthermore, sync source S₂ is provided with a plurality of sync source pads 228a, 228b, 228c, 228d, and 228e (also referred to collectively as "sync source pads 228"). Sync source S₂ is exposed for electrical connection on a bottom surface of sync transistor Q₂ via sync source pads 228 (See <figref idref="f0005">Figure 2D</figref>) and corresponds to low voltage input terminal V_L in <figref idref="f0001">Figure 1</figref>. Sync source pads 228 of sync source S₂ can include solderable front metal (SFM) that can be used for electrical connection to sync source S₂.

0025In the present embodiment, sync gate G₂ is also exposed for electrical connection on a bottom surface of sync transistor Q₂ via a gate pad (See <figref idref="f0005">Figure 2D</figref>) and corresponds to sync gate terminal V_G2 in <figref idref="f0001">Figure 1</figref>. Sync gate G₂ can also include SFM that can be used for electrical connection to sync source G₂.

0026It is noted that in some embodiments, sync drain D₂, sync source S₂, and sync gate G₂ are not provided as shown in stacked half-bridge package 202. For example, sync drain D₂, sync source S₂, and sync gate G₂ can be provided on different surfaces of sync transistor Q₂ and can be provided using one or more pads arranged in any suitable manner. As one example, in some embodiments, a single sync source pad can replace sync source pads 228. It is further noted that in some embodiments, sync source S₂ and sync gate G₂ are not exposed for electrical connection as described above, and other layers or features can be connected to sync source S₂ and sync gate G₂.

0027Control drain leadframe 220, control gate leadframe 222, and common conductive leadframe 224 are electrically conductive and can comprise, for example, an easily solderable metal such as aluminum, and other solderable materials such as a metal alloy or a tri-metal. Common conductive leadframe 224 is over sync transistor Q₂ and is electrically and mechanically connected to sync drain D₂.

0028<figref idref="f0003">Figure 2B</figref> is similar to <figref idref="f0002">Figure 2A</figref>, with an addition of showing control transistor Q₁ of stacked half-bridge package 202 over common conductive leadframe 224 and sync transistor Q₂. Control transistor Q₁ in stacked half-bridge package 202 corresponds to control transistor Q₁ in <figref idref="f0001">Figure 1</figref>. In <figref idref="f0003">Figure 2B</figref>, dashed lines indicate portions of control transistor Q₁ that would not otherwise be visible. More particularly, control transistor Q₁ includes control source S₁ and control gate G₁, which are depicted using dashed lines. Control transistor Q₁ also includes control drain D₁, which is visible in <figref idref="f0003">Figure 2B</figref>.

0029Control source S₁ in stacked half-bridge package 202 corresponds to control source S₁ in <figref idref="f0001">Figure 1</figref>, control gate G₁ in stacked half-bridge package 202 corresponds to control gate G₁ in <figref idref="f0001">Figure 1</figref>, and control drain D₁ in stacked half-bridge package 202 corresponds to control drain D₁ in <figref idref="f0001">Figure 1</figref>. In the present embodiment, control transistor Q₁ has top and bottom surfaces, which are opposite one another. Control drain D₁ is on the top surface and control source S₁ and control gate G₁ are on the bottom surface.

0030In the present embodiment, control drain D₁ is provided with a control drain pad that substantially covers an entirety of the top surface of control transistor Q₁. Also in the present embodiment, control source S₁ is provided with a plurality of control source pads 234a and 234b (also referred to as control source pads 234). It is noted that in some embodiments, control drain D₁, control source S₁, and control gate G₁ are not provided as shown in stacked half-bridge package 202. Rather, control drain D₁, control source S₁, and control gate G₁ can be provided on different surfaces of control transistor Q₁ and can be provided using one or more pads arranged in any suitable manner. For example, in some embodiments, a single control source pad can replace control source pads 234.

0031Control transistor Q₁ is over common conductive leadframe 224, which is electrically and mechanically connected to control source S₁. Thus, control and sync transistors Q₁ and Q₂ are stacked on opposite sides of common conductive leadframe 224, with common conductive leadframe 224 electrically and mechanically coupling control source S₁ with sync drain D₂. Common conductive leadframe 224 is thereby serving as output terminal V_OUT of stacked half-bridge package 202, corresponding to output terminal V_OUT in <figref idref="f0001">Figure 1</figref>. Advantageously, a short current path is formed between control source S₁ and sync drain D₂ that has low parasitic inductance and resistance (See <figref idref="f0005">Figure 2D</figref>). As such, stacked half-bridge package 202 does not significantly degrade performance of half-bridge 102 in <figref idref="f0001">Figure 1</figref>. Furthermore, stacked half-bridge package 202 has a small footprint that does not incorporate footprints of control transistor Q₁ and sync transistor Q₂ individually, thereby allowing for a small form factor.

0032Control transistor Q₁ is also over control gate leadframe 222, which is electrically and mechanically connected to control gate G₂. In the present embodiment, control gate leadframe 222 corresponds to control gate terminal V_G1 in <figref idref="f0001">Figure 1</figref>. Control gate leadframe 222 provides electrical and mechanical connection for control gate G₁. <figref idref="f0003">Figure 2B</figref> shows a majority of control transistor Q₁ being over common conductive leadframe 224, with a portion of control transistor Q₁ overhanging common conductive leadframe 224 so as to accommodate connection between control gate G₁ and control gate leadframe 222.

0033<figref idref="f0004">Figure 2C</figref> is similar to <figref idref="f0003">Figure 2B</figref>, with an addition of showing conductive clip 230 of stacked half-bridge package 202 over control transistor Q₁, common conductive leadframe 224 and sync transistor Q₂. Conductive clip 230 comprises conductive material, such as a metal or metal alloy. In one embodiment conductive clip 230 is a copper clip. Conductive clip 230 includes web portion 230a and leg portion 230b and provides connection between control drain D₁ and control drain leadframe 220. In <figref idref="f0004">Figure 2C</figref>, a dashed line indicates a boundary of web portion 230a and leg portion 230b. In the present embodiment, control drain leadframe 220 corresponds to high voltage input terminal V_H in <figref idref="f0001">Figure 1</figref> with leg portion 230b being over and electrically and mechanically connected to control drain leadframe 220 and web portion 230a being over and electrically and mechanically connected to control drain D₁ of control transistor Q₁.

0034As noted above, <figref idref="f0005">Figure 2D</figref> illustrates a cross sectional view of a portion of stacked half-bridge package 202 corresponding to a cross section along line 2D-2D in <figref idref="f0002 f0003 f0004">Figures 2A-2C</figref>. <figref idref="f0005">Figure 2D</figref> shows hermetic sealant 236, which is optional as indicated by dashed lines. In one embodiment, hermetic sealant 236 is a molding compound, which encapsulates stacked half-bridge package 202. <figref idref="f0005">Figure 2D</figref> shows hermetic sealant 236 leaves common conductive leadframe 224, sync gate G₂, sync source S₂, control gate leadframe 222, and control drain leadframe 220 exposed on bottomside 240b of stacked half-bridge package 202 and thus, available for electrical connection.

0035<figref idref="f0005">Figure 2D</figref> shows that in the present embodiment, common conductive leadframe 224 has web portion 224a and leg portion 224b. Leg portion 224b is of thickness 242, which is greater than that of sync transistor Q₂ and web portion 224a. Furthermore, control gate leadframe 222 is of thickness 242, which is greater than that of web portion 224a of common conductive leadframe 224 and is greater than that of sync transistor Q₁. Similarly, control drain leadframe 220 is of thickness 244, which is greater than that of web portion 224a of common conductive leadframe 224 and is greater than that of sync transistor Q₁. In the present embodiment, respective bottom surfaces of sync transistor Q₁, leg portion 224a of common conductive leadframe 224, conductive gate leadframe 222 and conductive drain leadframe 220 can thereby be substantially flush with one another, as shown in <figref idref="f0005">Figure 2D</figref>. As such, stacked half-bridge package 202 can easily be mounted on and electrically connected to a substrate (not shown in <figref idref="f0002 f0003 f0004 f0005">Figures 2A-2D</figref>).

0036<figref idref="f0005">Figure 2D</figref> also shows that conductive clip 230 is connected to control drain D₂ at topside 240a of stacked half-bridge package 202. Leg portion 230b of conductive clip 230 is of thickness 244 that is greater than that of control transistor Q₁ and web portion 230a. In the present embodiment, respective top surfaces of control gate leadframe 222, control drain leadframe 220, and common conductive leadframe 224 can thereby be substantially flush with one another, as shown in <figref idref="f0005">Figure 2D</figref>. Thus, in some embodiments, control gate leadframe 222, control drain leadframe 220, and common conductive leadframe 224 can be formed from a shared leadframe. In one embodiment, common conductive leadframe 224 is an etched or half-etched leadframe that can be formed from the shared leadframe. Etching or half-etching common conductive leadframe 224 can be used to form leg portion 224b of common conductive leadframe 224. <figref idref="f0005">Figure 2D</figref> also illustrates that common conductive leadframe 224 electrically and mechanically couples the control source (source of control transistor Q1) with the sync drain (drain of sync transistor Q2) to form the output terminal of stacked half-bridge package 202.

0037Thus, as described above with respect to <figref idref="f0001">Figures 1</figref> and <figref idref="f0002 f0003 f0004 f0005">2A-2D</figref>, embodiments of the present invention can provide for a stacked half-bridge package including a control transistor and a sync transistor. The control transistor and the sync transistor can advantageously be connected in a half-bridge package with low parasitic inductance and resistance. Furthermore, the control transistor and the sync transistor can be connected with the stacked half-bridge package having a small footprint. As such, among other advantages not specifically described herein, the stacked half-bridge package can have a small form factor, where the stacked half-bridge package does not significantly degrade performance of the half-bridge.

0038From the above description of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skills in the art would recognize that changes can be made in form and detail without departing from the spirit and the scope of the invention. As such, the described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein, but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.