Method and device for active load modulation by inductive coupling

p0001The present invention relates to a method for transmitting data by inductive coupling, comprising the steps of receiving an antenna signal by means of an inductive antenna circuit in the presence of an alternating external magnetic field, extracting signal antenna a first periodic signal, producing a second periodic signal using a synchronous oscillator having a synchronization input receiving the first periodic signal, place the oscillator in a mode of free oscillation and to apply bursts of antenna circuit second periodic signal to generate a magnetic field modulation active load.

p0002The present invention also relates to a device for transmitting and receiving data adapted to implement this method.

p0003The present invention relates generally to inductive coupling communication techniques also called "near field communications" or "NFC" (Near Field Communications). A communication by inductive coupling typically involves a device said passive and said active device. The two devices are equipped with an antenna coil. The active device emits an oscillating magnetic field, for example at 13.56 MHz, and sends data to the passive device by modulating the magnetic field. This magnetic field is designated in the following "external magnetic field". The passive device sends data to the active device by load modulation.

p0004The load modulation can be passive or active. The passive load modulation is to change the impedance of the antenna coil of the passive device to the rhythm of a data carrier load modulation signal. This impedance modulation affects the impedance of the antenna coil of the active device by inductive coupling. The active device can therefore extract its antenna signal the load modulation signal used by the passive device, and deduce the data that the passive device sends.

p0005The active load modulation of emitting, in the rhythm of data carrier modulation signal, bursts of alternating magnetic field. The magnetic field bursts are perceived by the active device as a passive load modulation. This technique has been proposed by the Applicant in patent<patcit id="pcit0001" dnum="EP1327222A"><text>EP 1327222</text></patcit> (<patcit id="pcit0002" dnum="US7098770B2"><text>US 7098 770B2</text></patcit>), See Figures 4A-4E, page 8 Table 4, paragraph 074.

p0006The active load modulation offers, compared to the passive load modulation, a distance of greater communication and / or improved data transmission in harsh environments, such an environment disrupted by generating metal frames of eddy currents. The active load modulation required in consideration of the excitation means of the antenna coil and thus a power source, but consumes much less power than a permanent magnetic field emission.

p0007An active load modulation device can not be purely passive in terms of power (a passive device is electrically powered by the magnetic field emitted by the active device) but is nevertheless considered "passive" in that it does not emit the external magnetic field required for communication.

p0008For obtaining a maximum communication distance, the active load modulation also requires that the load modulation magnetic field is in phase with the external magnetic field emitted by the active device. phase rotation between the magnetic field of active load modulation and the external magnetic field may cause undesirable fluctuations in the communication distance.

p0009The patent <patcit id="pcit0003" dnum="US5453748A"><text>US 5453748</text></patcit> discloses a transponder comprising a local oscillator that generates a local signal, and a synchronous oscillator. A comparator compares this signal with a received reference signal, and provides a comparison signal to the synchronous oscillator which synchronizes with the comparison signal and provides a latched signal. A combiner receives the local signal and the latched signal and provides a transponder response signal.

p0010The patent <patcit id="pcit0004" dnum="EP1801741A"><text>EP 1801741</text></patcit> discloses a NFC device active load modulation using a phase locked loop to control the phase of the magnetic field load modulation (see Fig. 19 of this document). The phase locked loop comprises a VCO (voltage controlled oscillator), a phase comparator and a low pass filter supplying a control voltage to the VCO. The phase comparator receives, as reference frequency, a first periodic signal which is extracted from the antenna signal induced by the external magnetic field. The phase locked loop provides a second periodic signal whose phase is locked to that of the first periodic signal. In the data transmission mode, the bursts of the second periodic signal applied to the antenna circuit for generating magnetic field bursts.

p0011When the device switches to the data transmission mode, the first periodic signal is no longer applied to the phase comparator and a sampling circuit HLD ( "Sample Hold") maintains the control voltage applied to the VCO. The flip-flop phase locked loop and of a mode of operation to a synchronous mode free oscillation and remains in this mode until the end of data transmission.

p0012If it is desired that the magnetic field bursts is in phase with the external magnetic field, the phase lock loop must have a very low phase shift for the duration of the mode data transmission, which is at least equal to the duration of transmission of a data frame. In practice, the maximum phase shift tolerated over this period is generally about 1/4 of the period of the oscillating magnetic field at 13.56 MHz.

p0013For example, a 14443-A ISO frame has a duration of about 25.6 ms. The frequency of the periodic signal is 13.56 MHz, the phase shift of the phase locked loop in free oscillation mode should preferably not be greater than 18 ns, that is 1/4 of the period of the oscillating magnetic field at 13.56 MHz.

p0014Or, get more stability to 18 ns over a period of 25.6 ms means that the phase locked loop has to offer extreme precision of the order of 0.7 ppm ((18x10^-9/25.6x10^-3) * 10⁶). Such precision circuitry requires very high quality and expensive to achieve.

p0015It may therefore be desirable to provide a means for providing magnetic field bursts with a low phase shift relative to the external magnetic field, without using an extremely precise circuitry and costly to achieve.

p0016To this end, the present invention proposes to use a synchronous oscillator and to resynchronize the oscillator on the external magnetic field before each application to the antenna circuit of a burst of a periodic signal supplied by the oscillator.

p0017More particularly, embodiments of the invention relate to a method for transmitting data by inductive coupling, comprising the steps of receiving an antenna signal by means of an inductive antenna circuit in the presence of a field AC external magnetic, extract the antenna signal a first periodic signal, producing a second periodic signal using a synchronous oscillator having a synchronization input receiving the first periodic signal, the oscillator having a synchronous oscillation mode stalled in phase on the first periodic signal and a mode of free oscillation, and applied to bursts of antenna circuit of the second periodic signal to generate a magnetic field modulation active load. The method also includes the steps of placing the oscillator in the synchronous oscillation mode before each application of a burst of the second periodic signal to the antenna circuit, and put the oscillator in a free oscillation mode during the applying a burst of the second periodic signal to the antenna circuit.

p0018In one embodiment, the method comprises the step of, after application of a burst of the second periodic signal to the antenna circuit, maintaining the oscillator in the method of free oscillation signal during a settling time antenna before replacing the oscillator in the synchronous oscillation mode.

p0019In one embodiment, the method comprises the steps of providing a data carrier modulation signal, apply the second periodic signal to the antenna circuit when the modulation signal has a first logic value, generating a masking signal having a masking value at least when the modulation signal has the first logic value, and blocking the application of the first periodic signal to the oscillator clock input when the masking signal has the masking value.

p0020In one embodiment, the method comprises the step of imparting to the mask value of the mask signal longer than that of the first logic value of the modulation signal to maintain the oscillator in the free mode oscillation during the stabilization time of the antenna signal.

p0021In one embodiment, the method comprises a step of phase shifting the second periodic signal relative to the antenna signal.

p0022Embodiments of the invention also relate to a transmitting device and inductive coupling by receiving data comprising an inductive antenna circuit in which appears an antenna signal in the presence of an alternating external magnetic field, means for extracting from the antenna signal a first periodic signal, a synchronous oscillator having a synchronization input receiving the first periodic signal, providing a second periodic signal, the oscillator having a synchronous oscillation mode stalled timed on the first periodic signal and a mode of free oscillation, and a modulation circuit active load, configured to apply the bursts of antenna circuit of the second periodic signal and generate a magnetic field modulation active load. The device is configured to place the oscillator in the synchronous oscillation mode before each application of a burst of the second periodic signal to the antenna circuit, and put the oscillator in the method of free oscillation during application of a burst of the second periodic signal to the antenna circuit.

p0023In one embodiment, the device is configured to, after the application of a burst of the second periodic signal to the antenna circuit, maintaining the oscillator in the method of free oscillation during a stabilization time of the antenna signal before replacing the oscillator in the synchronous oscillation mode.

p0024In one embodiment, the device is configured to generate or receive a data carrier load modulation signal, apply the second periodic signal to the antenna circuit when the modulation signal) has a first logic value, generating a signal masking with a masking value at least when the modulation signal has the first logic value, and blocking the application of the first periodic signal to the oscillator clock input when the masking signal has the masking value.

p0025In one embodiment, the device is configured to provide the mask value of the mask signal longer than that of the first logic value of the modulation signal to maintain the oscillator in the method of free oscillation during the stabilization time of the antenna signal.

p0026In one embodiment, the synchronous oscillator is of the type astable oscillator having a natural frequency of self-oscillation determined by the components of the oscillator.

p0027In one embodiment, the synchronous oscillator is of the digital type and is configured to, in the synchronous oscillation mode, copy the output period of the periodic signal applied to the clock input, and in the free mode oscillation output reconstruct the frequency received on the synchronization input during the synchronous oscillation mode.

p0028In one embodiment, the synchronous oscillator comprises a phase locked loop comprising a phase comparator providing a phase signal, an active low-pass filter receiving the phase signal and providing a control voltage, a controlled oscillator tension receiving the control voltage and supplying the second periodic signal, and means for, when passing in the mode of free oscillation, the phase comparator block and keep the input of the voltage controlled oscillator the value of the control voltage.

p0029In one embodiment, the device comprises means for shifting the phase of the second periodic signal relative to the antenna signal.

p0030Embodiments of the invention also relate to a device comprising a device for transmitting and receiving data according to the invention and at least one host processor providing the device with data to transmit.

p0031In one embodiment, the device is mounted in or on a portable media.

p0032Embodiments of the invention also relate to a smart card, comprising at least one processor and a device for transmitting and receiving data according to the invention.

p0033Embodiments of a method and a device according to the invention will be described in the following non-limiting in relation to the accompanying figures, in which:<ul><li>the <figref idrefs="f0001">figure 1</figref> represents an NFC device transmitting / receiving data according to the invention comprising a synchronous oscillator,</li><li>the <figref idrefs="f0001">2A to 2D</figref> show signals occurring in operation of the device of the <figref idrefs="f0001">figure 1</figref> when transmitting data by modulating active load,</li><li>the <figref idrefs="f0002">3A to 3D</figref> show other signals involved in the operation of the device of <figref idrefs="f0001">figure 1</figref> when transmitting data by modulating active load,</li><li>the <figref idrefs="f0002">4</figref> shows a phase error between a first periodic signal and second periodic signal used by the device of the <figref idrefs="f0001">figure 1</figref>, </li><li>the <figref idrefs="f0002">5</figref> shows a first embodiment of a synchronous oscillator,</li><li>the <figref idrefs="f0003">6</figref> shows a second embodiment of a synchronous oscillator,</li><li>the <figref idrefs="f0003">7A</figref> shows the shape of an antenna signal of the device of <figref idrefs="f0001">figure 1</figref> when receiving and transmitting data, and <figref idrefs="f0003">Figures 7B to 7E</figref> show signals associated with the antenna signal,</li><li>the <figref idrefs="f0003">8</figref> represents an alternative embodiment of a portion of the device of <figref idrefs="f0001">figure 1</figref>,</li><li>the <figref idrefs="f0004">9</figref> shows another variant embodiment of the device of <figref idrefs="f0001">figure 1</figref>,</li><li>the <figref idrefs="f0004">Figure 10</figref> shows an example of portable device comprising a transmission / reception data device according to the invention, and</li><li>the <figref idrefs="f0004">11A, 11B</figref> are views from above and from below of another example of portable device comprising a transmission / reception data device according to the invention.</li></ul>

p0034The <figref idrefs="f0001">figure 1</figref> ND1 represents a device for transmitting / receiving data according to the invention, operating by inductive coupling. ND1 device comprises:<ul><li>a communication interface circuit contact ICT,</li><li>an ACT antenna circuit tuned to a carrier frequency, comprising an antenna coil AC1 and may include various other components such as capacitors and / or self-inductances,</li><li>a demodulation circuit coupled to a DCCT DMCT decoding circuit for receiving data DTr via the antenna circuit,</li><li>a CTC encoding circuit coupled to a modulation circuit MCT, DTx for transmitting data via the antenna circuit,</li><li>CKCT a clock circuit, and </li><li>SO synchronous oscillator.</li></ul>

p0035The contact ICT communication interface circuit connects the device ND1 to at least one host processor HP1. The host processor HP1 DTx provides data and receives data DTr. Data DTx / DTr are generally application data of a NFC application (transaction, payment, information exchange, etc.). Alternatively, the device can be autonomous ND1 and include an internal processor configured to manage contactless applications. The internal processor then generates himself DTx data and processes the data DTr.

p0036CKCT the clock circuit and the demodulator circuit DMCT receive an antenna signal AS present in the antenna circuit ACT. The AS antenna signal is for example extracted from the antenna circuit through an amplifier A1 whose gain is controlled by an AGC automatic gain control circuit. The antenna signal AS appears in the presence of an alternating external magnetic field FLD1 emitted by an NFC reader type EDV external device equipped with an antenna coil and AC2 operating in the active mode (continuous transmission of the magnetic field) . FLD1 the field oscillates, for example a 13.56 MHz carrier frequency (ISO 14443, ISO 13693, Sony FeliCa).

p0037CKCT the clock circuit supplies an external clock signal CKe, or "first periodic signal", whose frequency is usually identical to the carrier frequency is 13.56 MHz in the framework of the above standards. In one embodiment, the CKCT circuit also provides a signal DET having a determined value, for example 1, when the field is detected FLD2. The signal DET as a carrier detection signal which may be useful in some embodiments of the device ND1.

p0038The SO synchronous oscillator receives the external clock signal CKe and provides an internal clock signal CKs, or "second periodic signal". The SO oscillator has a synchronous oscillation mode where the phase of the signal CKs is based on that of CKe signal, and a mode of free oscillation CKs where the signal is no longer stalled timed on the CKe signal.

p0039For sending the data DTr ND1 device, the external device EDV applies to FLD1 magnetic field modulation, for example amplitude modulation, by means of a data-carrying modulation signal MS (DTr). The MS signal (DTr) affects the antenna signal AS and is extracted from it by the demodulation circuit DMCT after removal of the carrier. DMCT circuit supplies the modulation signal MS (DTr) the DCCT circuit which decodes and provides the data DTr the ICT communication interface circuit or the internal processor of the ND1 device if it is equipped with such a processor.

p0040DTx the data to send to external device EDV are provided to TCC encoding circuit. This then provides the modulation circuit MCT a data carrying modulation signal MS (DTx). This modulation signal MS (DTX) can be modulated with a subcarrier derived from the carrier frequency, eg 848 kHz subcarrier (ISO 14443) or 424 kHz (ISO 15693) or be encoded only in band basis without subcarrier (Sony FeliCa). To generate the subcarrier, MCT circuit receives the internal clock signal CKs provided by the synchronous oscillator.

p0041The modulation circuit MCT is here an active load modulation circuit implementing the method described by the Applicant in the patent <patcit id="pcit0005" dnum="EP1327222A"><text>EP 1327222</text></patcit> (<patcit id="pcit0006" dnum="US7098770B2"><text>US 7098 770B2</text></patcit>). MCT circuit provides the antenna circuit ACT an SLM active load modulation signal comprises bursts (wave trains) of the internal clock signal CKs, interspersed with periods of non-modulation signal where the SLM has a value by default, for example 0. the MCT modulator circuit here includes a type G2 logic aND gate receiving the signals CKs and MS (DTX) and providing the signal Sml, and an amplifier A2 connecting the output of gate G2 and the point application of Sml signal to the antenna circuit ACT.

p0042The SLM signal is here equal to 0 when the MS signal (DTx) is equal to 0, and copies the signal CKs when the MS signal (DTx) is 1. Thus, when the MS signal (DTx) is equal to 1 the ACT antenna circuit receives a burst of signal CKs and the AC1 antenna coil emits a corresponding burst of a magnetic field FLD2. The burst FLD2 magnetic field are detected by the external device EDV as a passive load modulation. The latter can thus extract its own antenna signal the MS signal (DTx) to deduce the DTx data sent by the device ND1.

p0043The SO synchronous oscillator OSC1 oscillator comprises a circuit comprising a synchronization input connected to the output of a G1 masking circuit, here an AND gate. Gate G1 receives on its inputs the external clock signal CKe and a masking signal MSK. The MSK signal is provided by a mask generator MG from the modulation signal MS (DTx). The MSK signal has a masking value, here 0, and a transparent value here 1. The OSC1 oscillator circuit is synchronized to the external clock signal CKe when it is not masked (MSK = 1) on its synchronization input and is operating in free oscillation when CKe signal is masked (MSK = 0).

p0044In one embodiment, the masking signal has the masking value (MSK = 0) only when the modulation signal MS (DTX) has a value corresponding to the emission of a magnetic field burst FLD2, here 1, and has the transparent value (MSK = 1) in the opposite case. In this case, the OSC1 oscillator circuit operates in mode free oscillation only during the emission of a magnetic field burst.

p0045In one embodiment, the masking signal has the masking value for the emission of a magnetic field burst FLD2, and is maintained at this value for an additional period of time following the issuance of the burst to leave time the antenna signal AS to stabilize. The<figref idrefs="f0001">2A to 2D</figref> illustrate this embodiment. The<figref idrefs="f0001">2A</figref> represents the signal CKs, the <figref idrefs="f0001">2B</figref> MS signal (DTx), the <figref idrefs="f0001">2C</figref> MSK signal and <figref idrefs="f0001">2D</figref> Slm the signal consisting of bursts of signal CKs. In order to simplify the drawing, the frequency of the signal CKs is not drawn to scale and the MS signal (DTx) is shown comprised of logical value 1 slots of constant duration Tp, separated by an interval of Tp time constant. In practice, the MS signal (DTx) may have any other shape depending on the data to be transmitted DTx, coding is applied to DTx data, and how it is generated (eg with or without sub-carrier).

p0046The <figref idrefs="f0001">2D</figref> shows that bursts of signal CKs, a Tp duration, are applied to the antenna circuit when the modulation signal MS (DTx) is 1 (reverse convention could be provided). The<figref idrefs="f0001">2C</figref> shows that the MSK signal is set to 0 when the MS signal (DTx) is equal to 1, and is kept at 0 during a time Tm greater than Tp but lower than Tp + Tp '. The duration of the period of resynchronization, during which the oscillator circuit is in the synchronous mode of oscillation (referred Tsyn on the<figref idrefs="f0001">2C</figref>) Is equal to Tp-Tm + Tp'.

p0047The <figref idrefs="f0002">3A to 3D</figref> show more exactly the resynchronization mechanism CKs relatively CKe the signal, between the transmission of two bursts of magnetic field FLD2. The<figref idrefs="f0002">3A</figref> represents the MSK signal and is identical to the <figref idrefs="f0001">2C</figref>. The<figref idrefs="f0002">3B</figref> represents the signal CKe and <figref idrefs="f0002">Figure 3D</figref> represents the signal CKs. The<figref idrefs="f0002">3C</figref> represents an internal oscillation signal CK of oscillator circuit OSC1. The CK and signals CKs are identical in frequency and differ only in their amplitude, that of the signal CKs is reduced here to logic level 1 or 0.

p0048The <figref idrefs="f0002">3B</figref> shows that the external clock signal CKe has a phase which can fluctuate during periods of free oscillation. In fact, during these periods, the internal clock signal CKs is injected into the antenna circuit and is superimposed to the signal induced by the external magnetic field FLD1. Although the signal CKs is synchronized with a fairly good precision to the external clock signal CKe, the phase shift between the induced signal and the injected signal may be sufficient to produce a phase fluctuation making it unfit antenna signal to provide a signal CKe reliable external clock. The<figref idrefs="f0002">3C and 3D</figref> show by against the phase of the internal clock signal CKs remains substantially stable during periods of free oscillation (identified by reference P2) through frequent periods of resynchronization (identified by the reference P1) Tsyn term.

p0049The <figref idrefs="f0002">4</figref> represents the maximum phase shift Dtmax (expressed in time difference) between the signal CKs and the signal CKe, when the signal CKs is going to be resynchronized to the signal CKe, or when the MSK signal will become equal to 1. The value depends Dtmax the accuracy of the oscillator circuit OSC1 is selected according to the intended application. A maximum phase shift of 1/4 of the period CKe signal can for example be mentioned.

p0050With resynchronizations occurring before each emission of a magnetic field burst FLD2, it is not necessary that the OSC1 oscillator circuit has extreme precision to ensure a maximum phase shift of one quarter period over the entire duration of a frame DTx data. The precision required is reduced to the level of a data bit DTx and specifically throughout the duration of a magnetic field burst, which may be only a fraction bit DTx as the encoding used ( a binary data may optionally be encoded by several bursts of magnetic field).

p0051Various types of oscillator circuits can be provided to achieve synchronous oscillator OS. For example, the<figref idrefs="f0002">5</figref> OSC11 shows an oscillator circuit comprising a core of stable multivibrator type oscillator (also called astable oscillator). This oscillator core comprises two self-inductances L1, L2, a capacitor C1, two transistors T1, T2 MOS type and a current source CG1. The inductor L1 is connected between a power supply node receiving a voltage Vcc and a node N1. The inductance L2 is connected between the voltage supply node Vcc and a node N2. Capacitor C1 is connected between the nodes N1, N2. The transistor T1 has its source S connected to the node N1, its drain D connected to ground via the current source CG1, and its gate G connected to the node N2. The transistor T2 has its source S connected to node N2, its drain D connected to ground via the current source CG1 and its gate G connected to the node N1.

p0052Furthermore, the synchronization input of the oscillator OSC11 circuit is formed by the base B of bipolar transistor T3 whose emitter E is connected to ground and whose collector C is connected to the node N1. The output of the oscillator circuit is formed by an inverter gate I1 supplying the signal CKs, the input and connected to the node N1, to which the internal oscillation signal CK is present.

p0053CKe when the signal is applied to the base B of transistor T3 (MSK = 1), the phase of signal CK on the node N1 is set by the signal CKe. The core of the oscillator circuit then operates not as an astable oscillator but as a monostable oscillator.

p0054When the MSK signal is 0, the transistor T3 is no longer conductive and the heart of the oscillator circuit operates in the astable mode and oscillator oscillates freely in a self-oscillation frequency. This frequency is set as close as possible to the frequency of the signal CKe (13.56 MHz under the above standards) by appropriate selection of the inductors L1, L2 and capacitor C1.

p0055In an alternative embodiment, the OSC1 oscillator circuit can be of the digital type and configured to, in the synchronous oscillation mode, analyze and store the frequency of the signal received on the CKe synchronization input, and copy the signal on its CKe exit. When rocking in the free oscillation mode, the oscillator circuit reconstructs the signal CKs from the stored value.

p0056As another exemplary embodiment, the <figref idrefs="f0003">6</figref> OSC12 shows an oscillator circuit comprising a phase locked loop ( "Phase Locked Loop"). The OSC12 circuit includes a gate G10 type XOR, an active low-pass filter FT1, a VCO (voltage controlled oscillator), a follower circuit SCT and a type of gate G11. The VCO provides the internal oscillation signal CK. It is applied to TBS circuit whose output provides the internal clock signal CKs. The internal oscillation signal CK is also returned to an input of the gate G10 through G11 of the door, which receives on another input the signal MSK. Another input of the gate G10 forms the input of the synchronization circuit and OSC12 connected to the output of the gate G1, which provides the external clock signal CKe when the MSK signal is equal to 1. The gate G10 forms a phase comparator and its output is sent to a VCO control input via the low-pass filter FT1 active.

p0057When the MSK signal is 1, the gate G11 is conducting, the gate G10 receives both the signal CK and the signal CKe and provides a phase difference signal. This differential signal form after low-pass filtering, a reference voltage of the VCO. The CK signal is thus phase-locked to the signal CKe. When the MSK signal goes to 0, the outputs of gates G1 and G11 change to 0. The output of the gate G10 is forced to 0. means hold at the entrance of the VCO voltage setpoint he received prior the passage to 0 of the MSK signal. These means include, for example a voltage source arranged in the low-pass filter FT1 asset, such as a charge pump. Thus, the VCO continues to provide the CK signal and maintains the phase of the signal CK close to that of the signal CKe.

p0058The <figref idrefs="f0003">7A to 7E</figref> schematically illustrate a data DTr receiving sequence (left side figures) and a data DTx transmit sequence (right side figures).

p0059The <figref idrefs="f0003">7A</figref> shows the shape of the antenna signal AS. The<figref idrefs="f0003">7B</figref> represents the modulation signal MS (DTr) extracted from the antenna signal AS by DMCT circuit. The<figref idrefs="f0003">7C</figref> represents Sml active load modulation signal comprising bursts of the signal CKs. The<figref idrefs="f0003">7D</figref> represents the modulation signal MS (DTx) and <figref idrefs="f0003">7E</figref> represents the signal CKs. The AS signal is here a double alternating signal alternating who is the image of the magnetic field FLD1 receive mode. Embodiments of the antenna circuit ACT, however, may include a rectifier diode of the antenna signal. In this case, it is a semi-wave signal.

p0060While receiving DTr data, the external device EDV (Cf. <figref idrefs="f0001">Fig. 1</figref>) Modulates the amplitude of the magnetic field FLD 1 with a depth of modulation which depends on the selected communication protocol and the antenna signal AS has a similar amplitude modulation. We distinguish periods of non NM modulation where the amplitude of the antenna signal is maximum and AM modulation periods where the amplitude of the antenna signal is minimal. Maxima and voltage minima of the signal AS depend in practice on the distance between the external device and EDV ND1 device.

p0061DTx during the data transmission, the antenna signal AS also has periods of non NM modulation where its amplitude is identical to that observed during periods of non-modulation during reception of data. The amplitude of the antenna signal depends only FLD1 the magnetic field emitted by the external device EDV and the distance between the two devices. The AS signal also has periods of boost ALM when sending bursts FLD2 magnetic field. Indeed, the signal CKs is then injected into the antenna circuit and is superimposed to the signal induced by the external magnetic field FLD1. The antenna signal then comprises an induced component and an injected component.

p0062It will be apparent to those skilled in the art that the transmitting / receiving data ND1 according to the invention is capable of various embodiments. Including the modulation circuit MCT may include, in addition to the active load modulation means described above modulation means of conventional passive load such as a load modulation switch connected to the antenna circuit ACT.

p0063In a variant embodiment, the MSK signal is applied to the AGC gain control circuit and the latter is configured to force to 0 the output of the amplifier A2. In this case, it may not be necessary to prevent the application of the signal CKe on the circuit synchronizing input oscillator OSC1, it automatically switching the mode in free oscillation when the signal goes to 0 CKe.

p0064The ND1 device may also include means for extracting a supply voltage Vcc from the antenna signal, such as a rectifier circuit followed by a smoothing capacitor to allow the device to operate ND1 mode purely passive in the absence of a local power source.

p0065In an embodiment shown in <figref idrefs="f0003">8</figref>, ND1 device also includes an oscillator OSC2 that is not synchronized to the external clock signal CKe, for example a quartz oscillator. The OSC2 provides a clock signal CK2 DV1 allowing the device to operate in NFC reader mode and chat with an integrated circuit passive contactless or a similar device configured in passive mode. In this case, the synchronous oscillator circuit OSC1 may continue to be used to provide the internal clock signal CKs. The selection of CKe or CK2 clock signal applied to the circuit OSC1 synchronization input can be made using the DET signal described above, giving priority to the passive mode.

p0066Still referring to <figref idrefs="f0003">8</figref>Two gates G3 and G4 are added and the gate G1 is changed to submit three entries. Gate G3 is an AND gate having three inputs, including an inverting input. Gate G4 is an OR gate with two inputs. Gate G3 receives at its two non-inverting inputs the signal CK2 and the MSK signal and receives the signal DET at its inverting input. The gate G1 receives on its inputs the signals CK2, DET and CKe. The outputs of the gates G1 and G3 are applied to the gate G4 the output of which is connected to the circuit of the synchronization input oscillator OSC1. When the signal DET is equal to 1 (presence of an external magnetic field FLD 1), the output of the gate G3 is set to 0 and the device operates in a passive mode as described above. When the DET signal is equal to 0, the output of gate G1 is forced to 0 and the MSK signal is forced to 1 by the MG circuit. The clock signal CK2 is fed to the input of the oscillator circuit OSC1 for the continuous transmission of the magnetic field FLD1. The structure of the gate G2 receiving the CKs and MS signals (DTx) and providing the Sml signal, can be modified so that it provides a modulation of CKs signal with an adjustable depth of modulation less than 100%, particularly if the must conform to ISO 14443A and 1443B.

p0067In the embodiment shown in the<figref idrefs="f0004">9</figref>The ND1 device includes a phase shifter DPH. This phase shifter is arranged for example at the output of amplifier A1. The phase shifter DPH applies to antenna signal AS a Dp phase and provides CKCT clock circuit and demodulator circuit DMCT a phase-shifted antenna signal AS '. Dp phase shift can be fixed and determined during the design phase shifter DPH. Alternatively, the phase shift Dp can be dynamically determined by a PHC command applied to the phase shifter, which sets the value of Dp phase, for example between 0 and 360 °.

p0068The phase shifter allows the DPH ND1 device for transmitting bursts of magnetic field FLD2 Dp which have the phase shift relatively to the external magnetic field FLD1. This allows for example, in some applications where the communication distance does not exceed a certain threshold (eg for security reasons), reduce the communication distance below this threshold.

p0069This embodiment shows that controlling the phase of the signal CKs using the synchronous oscillator SO not only can target a zero phase shift between the magnetic field and the magnetic field FLD2 FLD1. Controlling the phase of the signal CKs by means of the synchronous oscillator SO may also allow control of voluntary desynchronization of the magnetic field FLD 2 relatively to the magnetic field FLD1, while maintaining as constant as possible the phase difference Dp between the two magnetic fields.

p0070The transmitting / receiving data ND1 according to the invention is also susceptible of various applications. In an application example shown in<figref idrefs="f0004">Figure 10</figref>, ND1 device is integrated in a portable device HD1 and is connected to one or more host processors, here two host processors HP1, HP2 using ND1 device as a communication contactless interface (NFC interface). The portable device HD1 is for example a mobile phone, a digital audio player, a personal digital assistant (PDA). The HP1 processor is the main processor of the device or a secure processor such a SIM card processor. HP2 processor may for example be the baseband processor of a mobile phone, also provides communication via GSM channel.

p0071In another application example shown in <figref idrefs="f0004">11A, 11B</figref>, ND1 device is connected to a host processor HP1 and the assembly is integrated in a plastic CD holder for forming a HD2 smart card. AC1 antenna coil is for example a co-planar coil having one or more turns. The rear panel (<figref idrefs="f0004">Fig. 11B</figref>), The HD2 is equipped with a contact CP group. The HD2 can for example form an NFC SIM card. The contact group may include in this case C1 to C8 contacts in accordance with ISO standard 7816. The HD2 can also form an SD card type to be inserted into any device (mobile phone, PC, ...) as interface NFC communication.