Calibration of lamps using power line communication for sending calibration data

Description of equivalent WO 2010126765 A2

CALIBRATION OF LAMPS

0002William A. Draper

0003Robert T. Grisamore

0004John L. Melanson

BACKGROUND OF THE INVENTION

0006Field of the Invention

0007(1) The present invention relates in general to the field of signal processing, and more specifically to a system and method of calibrating lamps.

DESCRIPTION OF THE RELATED ART

0009(2) Light emitting diodes (LEDs) are becoming particularly attractive as main stream light sources in part because of energy savings through high efficiency light output and environmental incentives such as the reduction of mercury. LEDs are semiconductor devices and are driven by direct current. The brightness (i.e. luminous intensity) of the LED approximately varies in direct proportion to the current flowing through the LED. Thus, increasing current supplied to an LED increases the intensity of the LED and decreasing current supplied to the LED dims the LED. Current can be modified by either directly reducing the direct current level to the white LEDs or by reducing the average current through duty cycle modulation.

0010(3) LEDs have component-to-component variation. For example, for a particular current, the brightness of one LED compared to another LED can vary by an amount that is noticeable by a human. Additionally, when one or more LEDs are assembled into a lamp and multiple lamps are arranged in proximity to each other, the variation between LEDs in different lamps can be sufficient to allow a human to notice a difference in the brightness of one lamp to another.

0011(4) Figure IA depicts a lamp calibration system 100. In general, lamp calibration system 100 allows the brightness of lamp 102 to be tested and, if desired, adjusted within a tolerance level. The tolerance level can be a specific value or a range of values. The lamp calibration system 100 includes a lamp 102 situated in proximity to a light meter 104. The lamp 102 connects via exemplary power terminals 106 and 108 to voltage source 110 that supplies an alternating current (AC) supply voltage V_{AC SUPPLY} to lamp 102. Each lamp 102 is calibrated so that the brightness of lamp 102 is within a predetermined brightness tolerance. The voltage source 110 is, for example, a public utility, and the AC supply voltage V_AC SU_PPLY is, for example, a 60 Hz/110 V line voltage in the United States of America or a 50 Hz/220 V line voltage in Europe. Lamp 102 includes a power control circuit 112 that converts the supply voltage V_AC SU_PPLY into a regulated link voltage V_LIN_K and an output current i_Ouτ- The link voltage is, for example, an approximately constant voltage having a regulated value between 200V and 400V. The power control circuit 112 includes a lamp driver 114. The lamp driver 114 is a switching power converter, such as a buck converter, boost converter, or a buck-boost converter. Lamp driver 114 includes a switch (not shown), and a duty cycle of the switch is controlled by a switch control signal CSo generated by controller 116. An exemplary power control circuit is described with reference to Figures 1 and 2 of U.S. Patent Application No. 11/967,269, entitled Power Control System Using A Nonlinear Delta-Sigma Modulator With Nonlinear Power Conversion Process Modeling, filed on December 31, 2007, inventor John L. Melanson, and assignee Cirrus Logic, Inc. U.S. Patent Application No. 11/967,269 is referred to herein as "Melanson I" and is hereby incorporated herein in its entirety.

0012(5) Figure IB depicts lamp calibration system 150, which represents a physical embodiment of lamp calibration system 100. Lamp 124 represents an exemplary physical embodiment of lamp 102. To calibrate lamp 124, lamp 124 is physically placed in a test apparatus 126 and connected to voltage source 110. Power control circuit supplies the output current i_Ouτ to light source 118 to cause each of one or more LEDs in light source 118 to illuminate. Light meter 104 detects the light 119 generated by light source 118 and displays an indication of the brightness of light source 118 on display 120. Power control circuit 112 includes a trim module 122 that can be adjusted to vary the brightness of lamp 124 so that the brightness of lamp 102 as indicated by light meter 104 is within the predetermined brightness tolerance. (6) Power control circuit 112 is connected to housing 128 via power wires 132 of lamp 124. To expose the trim module 122, lamp 124 is partially disassembled by disconnecting housing 128 from lamp cover 130. Exposing the trim module 122 allows access to the trim module 122 and allows adjustment of the trim module 122 to adjust the brightness of lamp 124. After adjustment, lamp 124 is reassembled.

0013(7) Partially disassembling lamp 124, adjusting the trim module 122, and reassembling lamp 124 results in a time consuming calibration process that is generally not conducive to manufacturing lamps in commercial volumes at competitive prices. Additionally, some conventional lamps 102 have inaccessible power control circuits and, thus, are not calibrated. Thus, it is desirable to have a different manner of calibrating a lamp.

SUMMARY OF THE INVENTION

0015(8) In one embodiment of the present invention, an apparatus includes a controller configured to generate one or more power control signals for a lamp, wherein the controller is further configured to receive lamp calibration data received via one or more power terminals of the lamp and to process the calibration data to calibrate the lamp.

0016(9) In another embodiment of the present invention, a method includes receiving lamp calibration data via one or more power terminals of a lamp and processing the lamp calibration data to calibrate the lamp. The method further includes generating one or more power control signals for the lamp using the calibration data.

0017(10) In a further embodiment of the present invention, an apparatus includes calibration unit configured to send calibration data for calibrating a lamp to one or more power terminals of a lamp.

BRIEF DESCRIPTION OF THE DRAWINGS

0019(11) The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the several figures designates a like or similar element.

0020(12) Figure IA (labeled prior art) depicts a lamp calibration system. (13) Figure IB (labeled prior art) depicts an embodiment of the lamp calibration system of Figure IA.

0021(14) Figure 2 depicts a lamp calibration system.

0022(15) Figure 3 depicts a lamp calibration system that receives supply voltage/calibration data via power terminals of a lamp.

0023(16) Figure 4 depicts a calibration unit embodiment for the lamp calibration system of Figure 2.

0024(17) Figure 5 depicts a switch of the calibration unit of Figure 4.

0025(18) Figure 6 depicts exemplary phase modulated waveforms of a supply voltage/calibration data of the calibration unit of Figure 4.

0026(19) Figure 7 depicts a high speed calibration unit embodiment for the lamp calibration system of Figure 2.

0027(20) Figure 8 depicts a high speed switch for the high speed calibration unit of Figure 7.

0028(21) Figure 9 depicts a respective high speed switch system for the high speed calibration unit of Figure 7.

0029(22) Figure 10 depicts exemplary high speed encoding of supply voltage/calibration data by a calibration modulation signal of the high speed calibration unit of Figure 7.

0030(23) Figure 11 depicts an embodiment of a controller of the lamp calibration system of Figure 2.

0031(24) Figure 12 depicts a decoder of the controller of Figure 11.

0032(25) Figure 13 depicts a lamp driver controller of the controller of Figure 11.

0033(26) Figure 14 depicts a state diagram for a processor of the controller of Figure 11.

0034(27) Figure 15 depicts an embodiment of a lamp. DETAILED DESCRIPTION

0035(28) In at least one embodiment, a lamp includes a controller configured to generate power control signals for a lamp is also configured to receive lamp calibration data received via one or more power terminals of the lamp. The controller is configured to process the calibration data to calibrate the lamp. A calibration system energizes the lamp to allow a light meter to measure the light emitted from the lamp under normal operating conditions. In at least one embodiment, the lamp includes one or more light emitting diodes (LEDs) that emit the light. The light meter provides light data to the calibration unit. The light data measures one or more properties of the light such as brightness and dominant optical wavelength. The calibration unit determines whether the light data indicates that the lamp is within tolerances.

0036(29) The lamp receives power from a voltage source via power terminals. The calibration unit generates calibration data for the controller and modulates the voltage supplied to the lamp to send the calibration data to the controller. Thus, in at least one embodiment, the lamp receives the calibration data via the power terminals. The controller includes a decoder that decodes the calibration data. In at least one embodiment, the controller includes a processor to process the calibration data to calibrate the lamp.

0037(30) In at least one embodiment, the voltage supplied to the lamp during calibration is an AC supply voltage. The calibration unit modulates the AC supply voltage to encode the calibration data in the supply voltage so that the supply voltage is converted into a supply voltage and data signal. In at least one embodiment, the calibration unit modulates the supply voltage by using phase modulation and encodes the calibration data in the resulting phase angles. In at least one embodiment, the controller already includes a timer to detect phase angles associated with dimming of the lamp during normal use. The output of the timer can be used to decode the calibration data.

0038(31) In at least one embodiment, the voltage to the lamp during calibration is a high speed, pulse width modulated (PWM) supply voltage signal. The duty cycle of the PWM signal is modified to encode the calibration data. The peak voltage of the PWM signal is adjusted in accordance with the pulse width modulation so that an average peak value of the supply voltage signal provides the voltage level used to turn the lamp "ON". (32) Figure 2 depicts a lamp calibration system 200 that includes a controller 202 configured to generate power control signals CSi and CS₂ for lamp 204 and to receive lamp supply voltage/calibration data V_SUPPLY/DATA- In general, lamp calibration system 200 allows one or more properties of lamp 102 to be tested and, if desired, adjusted to a tolerance level. The tolerance level can be a specific value or a range of values. In at least one embodiment, controller 202 is an integrated circuit fabricated on a semiconductor wafer. In other embodiments, controller 202 is fabricated using discrete components or a combination of integrated and discrete components. Controller 202 can be analog, digital, or mixed analog and digital. Although two control signals CSi and CS₂ are depicted, controller 202 can be configured to generate any number of control signals to control the link voltage V_LINK and the current or currents in light source 216. In at least one embodiment, multiple currents flow in light source 216 to respectively illuminate separate sets of light emitting sources, such as LEDs.

0039(33) During calibration of lamp 204, the power terminals 206 and 208 of lamp 204 are respectively connected to calibration unit 210 and voltage source 212. Voltage source 212 provides a supply voltage VSU_PPLY. The supply voltage VSU_PPLY can be an alternating current (AC) or a direct current (DC) voltage. During calibration of lamp 204, power control circuit 214 generates a link voltage V_LINK and supplies power to light source 216. In at least one embodiment, control signal CSi controls the link voltage V_LINK- Power control unit 214 also supplies an output current Ϊ_LS to light source 216 to cause light source 216 to emit light 218. In at least one embodiment, control signal CS₂ controls an average value of the output current i_LS. In at least one embodiment, power control unit 214 controls a switch (such as switch 1522 in Figure 15) in light source 216 that directly controls the output current i_Ls in light source 216. Light source 216 can be any type of light source. In at least one embodiment, light source 216 includes one or more sets of one or more LEDs.

0040(34) Light meter 220 detects the light emitted from light source 216 and generates a lighting data signal LDATA. The lighting data signal LDATA contains data representing the property(ies) of the light 218 as determined by light meter 220. In at least one embodiment, the lighting data signal LDATA contains data representing the brightness of light source 216. The light meter 220 provides the lighting data signal LDATA to calibration unit 210. The calibration unit 210 processes the lighting data signal LDATA and determines whether each property of the light 218, as reported by the lighting data signal LDATA, is within a predetermined tolerance. If the lamp 204 emits light 218 within tolerance, calibration unit 210 provides an indication that lamp 204 is ready for use. The "ready for use" indication can be a visual cue or an electronic signal provided to an automated test apparatus (Figure 3), which then removes the lamp 204 and replaces lamp 204 with another lamp for calibration. If the light 218 is not within tolerance, calibration unit 210 determines calibration data to be sent to lamp 204. The calibration data notifies controller 202 of changes to be made by lamp 204 that will bring lamp 204 into within a tolerance level or at least closer to a tolerance level.

0041(35) Calibration unit 210 sends the calibration data to controller 202 by modulating the supply voltage VSU_PPLY to generate supply voltage/calibration data VSU_PPLY/_DATA. Data signal V_{SUPPLY D} represents the data encoded in supply voltage/calibration data VSUPPLY/DATA. In at least one embodiment, data signal VSUPPLY D is a direct one-to-one observation of supply voltage/calibration data V_SUPPLY/DATA. In another embodiment, data signal V_{SUPPLY D} is observed across a sampling resistor (not shown) to generate a scaled version of supply voltage/calibration data V_SUPPLY/DATA. In at least one embodiment, calibration unit 210 also sends header data to the controller 202 to cause controller 202 to enter a calibration mode. In at least one embodiment, the header data is a sequence of bits that alerts the controller 202 that supply voltage/calibration data VSU_PPLY/_DATA includes calibration data to be decoded. The supply voltage/calibration data V_SUPPLY/DATA is received by the lamp 204 via power terminals 206 and 208. Calibration unit 210 can utilize any modulation technique, such as phase angle modulation and pulse width modulation, to encode the supply voltage/calibration data V_SUPPLY/DATA with the calibration data. In at least one embodiment, during normal use, e.g. not during calibration mode, controller 202 is configured to cause lamp driver 222 to dim light source 216 by detecting phase angles of a phase modulated supply voltage. Thus, in at least one embodiment, calibration unit 210 can encode the calibration data in the supply voltage/calibration data VSU_PPLY/_DATA by phase modulating the supply voltage VSU_PPLY during the calibration mode, and controller 202 can utilize the same components used to detect the phase angles for dimming to decode the calibration data from the phase modulated supply voltage/calibration data V_SUPPLY/DATA during a normal mode of use.

0042(36) However, in at least one embodiment, phase modulating the supply voltage VSU_PPLY to encode the calibration data in supply voltage/calibration data VSU_PPLY/_DATA limits the data transfer rate to lamp 204 to a multiple between 1 and 4 of the frequency /VSU_PPLY of the supply voltage VSU_PPLY. For example, identically phase modulating each half cycle of the supply voltage V_SUPPLY results in a data transfer rate of/vsuppLY. Independently phase modulating the leading edge or trailing edge of each half cycle of the supply voltage VSU_PPLY results in a data transfer rate of 2/VSU_PPLY- Independently phase modulating the leading and trailing edges of each half cycle of the supply voltage VSU_PPLY results in a data transfer rate of 4/VSU_PPLY- In the U.S., the value of frequency /VSU_PPLY is 60Hz, and in Europe the value of frequency /VSU_PPLY is 50 Hz. Thus, in at least one embodiment, the maximum transfer rate is 240 Hz in the U.S. and 200 Hz in Europe.

0043(37) In another embodiment, calibration unit 210 increases the data transfer rate of the calibration data by modulating a DC supply voltage V_SUPPLY supplied by voltage source 212. In at least one embodiment, calibration unit 210 utilizes pulse width modulation to vary the duty cycle of supply voltage VSU_PPLY. The value of the duty cycle encodes the calibration data. To decode the calibration data, in at least one embodiment, controller 202 includes a decoder, such as decoder 1200 (Figure 12), to detect each duty cycle of supply voltage/calibration data V_SUPPLY/DATA and to recover the calibration data from the supply voltage/calibration data V_SUPPLY/DATA. Since the supply voltage/calibration data V_SUPPLY/DATA also supplies operating voltage to lamp 204, calibration unit 210 adjusts the peak voltage of the pulse width modulated supply voltage/calibration data VSU_PPLY/_DATA SO that an average peak voltage of supply voltage/calibration data V_SUPPLY/DATA provides sufficient operating voltage to lamp 204. The data transfer rate of calibration data can be set at any value supported by calibration unit 210 and controller 202. For example, the data transfer rate can be set within a range of IkHz to 10kHz.

0044(38) In at least one embodiment, controller 202 stores the calibration data or data derived from the calibration data in memory 224. Memory 224 can be separate from controller 202 as depicted in Figure 2 or incorporated into controller 202. In at least one embodiment, memory 224 includes both volatile and nonvolatile storage devices.

0045(39) During the normal mode of use and in calibration mode, the controller 202 retrieves the stored calibration data from memory 224 and uses the calibration data to adjust the light 218 to within a tolerance level. The particular tolerance level is, for example, dependent upon the particular light source 216 and manufacturer specifications for the light source 216. For example, for a multiple LED light 218, an example tolerance level is 600 lumens +/- 10%, i.e. between 540 to 660 lumens. The manner in which controller 202 utilizes the calibration data to adjust the light 218 to within a tolerance level is a matter of design choice. For example, in at least one embodiment, the controller 202 receives a light source current feedback signal i_{LS FB} representing the current in light source 216. In at least one embodiment, controller 202 utilizes the calibration data as a target value to compare against the light source current feedback signal i_Ls _FB- The controller 202 then adjusts the control signal CSi so that lamp driver 222 drives the light source current feedback signal iLs _FB towards the target value indicated by the calibration data. In another embodiment, controller 202 utilizes the calibration data to modify the light source current feedback signal i_Ls _FB prior to comparison to a target value and then adjusts the control signal CSi so that lamp driver 222 drives the light source current feedback signal towards the target value. Because calibration of the lamp 204 does not require physical access to the power control circuit 214, lamp 204 can be calibrated while fully assembled.

0046(40) In at least one embodiment, the lamp 204 is configured to send information to another device, such as calibration unit 210 or any other device that can receive and decode data. In at least one embodiment, the information is related to lamp 204, such as an internal temperature of lamp 204, the value of calibration data stored in memory 204 (such as calibration data CAL D ATA in Figure 13), the serial number of lamp 204, hours of use, and/or date of manufacture.. In at least one embodiment, lamp 204 sends data by pulsing light source 216. The pulses of light 218 represent information. In at least one embodiment, lamp 204 responds to a request by calibration unit 210 to send specific information. For example, in one embodiment, calibration unit 210 is configured to request information from lamp 204, such as the internal temperature of lamp 204, the value of calibration data stored in memory 204 (such as calibration data CAL D ATA in Figure 13), or any other data that is, for example, determined by lamp 204 or stored in memory 224. In at least one embodiment, controller 202 is configured to encode the data as pulses of light 218. Light meter 220 detects the pulses of light 218 and sends lighting data signal LDATA. The value of lighting data signal LDATA represents the pulses of light 218. Calibration unit 210 decodes the lighting data signal LDATA to obtain the requested information.

0047(41) In at least one embodiment, lamp 204 pulses light 218 without receiving a request, such as in response to internal programming of controller 202. Light 218 can be pulsed by, for example, turning the light source 216 "on" and "off or by varying the intensity of light 218. In at least one embodiment, when pulsing light 218 without receiving a request, the pulses of light 218 represents a packet of data that informs the data recipient, such as calibration unit 210, of, for example, that data is being sent, the type of data, and the value of the information of interest represented by the data.

0048(42) For example, calibration unit 210 encodes supply voltage/calibration data V_SUPPLY/DATA with a request that lamp 204 provide the calibration data CAL_DATA stored in memory 224. Controller 202 decodes the request, retrieves the value of the calibration data CAL_DATA from memory 224, commands lamp driver 222 to cause light source 216 to pulse light 218 in accordance with a response packet of data. The response packet includes the data responsive to the request of calibration unit 210 and can include other data to allow calibration 210 to identify and verify the response. For example, in one embodiment, the response packet contains three blocks of data respectively consisting of a key sequence to identify the response, the responsive data, and verification data. Thus, in one embodiment, if the calibration unit 210 requests the value of calibration data CAL_DATA stored in memory 224, the key sequence is

0049110110111, the calibration data CAL D ATA has a binary value of "10011", and a summation of the key sequence and the calibration data CAL D ATA (referred to as a "checksum") has a binary value of 111001010. Lamp 204 responds to the request by pulsing light 218 with a sequence 11011011110011111001010. In at least one embodiment, each pulse has a predetermined duration known to both the controller 202 and calibration unit 210, and pulses representing a binary "0" have a different brightness than pulses representing a binary "1". The length of data in the response packet, the configuration of the packet, the coding of data in the packet, and any other parameter related to the packet are matters of design choice.

0050(43) Figure 3 depicts lamp calibration system 300, which represents one embodiment of lamp calibration system 200. Referring to Figures 2 and 3, the particular, physical configuration of lamp 204 is a matter of design choice. In lamp calibration system 300, lamp 302 represents one embodiment of lamp 204. Lamp 302 includes power terminals 304 and 306 to receive supply voltage/calibration data VSU_PPLY/_DATA during calibration. The power control circuit 214 is located in housing 308, and light source 216 is located in translucent cover 310. The lamp 302 is either manually or automatically positioned in test apparatus 312 for calibration. In at least one embodiment, light meter 220 is mounted within test apparatus 312.

0051(44) Figure 4 depicts calibration unit 400, which represents one embodiment of calibration unit 210. Calibration unit 400 includes a calibration controller 402 that receives lighting data signal LDATA and target light value TLV. In at least one embodiment, the target light value TLV is stored in a memory (not shown). The value of target light value TLV represents the target value of lighting data signal LDATA. Calibration unit 400 compares the target light value TLV with the lighting data signal LDATA and generates calibration modulation signal CAL MS. Switch 404 is connected between voltage source 406 and power terminal 206. The calibration modulation signal CAL_MS operates switch 404 to phase modulate the AC voltage supply VSU_PPLY to generate supply voltage/calibration data VSU_PPLY/_DATA. As subsequently described in more detail, in at least one embodiment, the particular phase angle of each half cycle of supply voltage/calibration data V_SUPPLY/DATA represents either a logical "1" or a logical "0". Thus, the calibration modulation signal CAL_MS encodes data, including calibration data, as a binary bit stream in the supply voltage/calibration data V_SUPPLY/DATA by controlling the phase angles in the phase modulated supply voltage/calibration data V_SUPPLY/DATA. The calibration controller 402 samples the voltage supply V_SUPPLY and phase locks to the voltage V_SUPPLY to allow calibration modulation signal CAL_MS to accurately generate the phase angles in supply voltage/calibration data VSU_PPLY/_DATA.

0052(45) The particular type of phase modulation by calibration controller 402 is a matter of design choice. Calibration controller 402 can be configured to identically phase modulate each half cycle of supply voltage V_SUPPLY or independently modulate leading, trailing, or both leading and trailing edges of each half cycle of voltage supply VSUPPLY.

0053(46) Other types of phase modulation encoding schemes can be used to encode supply voltage/calibration data V_SUPPLY/DATA with calibration data. For example, calibration controller 402 can be configured to phase modulate leading edges of each half cycle of a cycle of supply voltage V_SUPPLY to encode a logical "1" and phase modulate trailing edges of each half cycle of supply voltage VSU_PPLY to encode a logical "0". The particular type of phase modulation encoding scheme is a matter of design choice.

0054(47) Referring to Figures 4 and 5, the particular type of switch 404 is a matter of design choice. Figure 5 depicts switch 500 to phase modulate supply voltage V_SUPPLY. Switch 500 represents one embodiment of switch 404. Two insulated gate bipolar junction transistors (IGBTs) 502 and 504 with connected emitters form switch 500 to allow calibration controller 402 to phase modulate each half cycle of supply voltage V_SUPPLY- Calibration controller 402 provides calibration modulation signal CAL_MS to the gates of IGBTs 502 and 504 to control conductivity of IGBTs 502 and 504. Controlling the conductivity of IGBTs 502 and 504 controls the phase angles of supply voltage V_SUPPLY- In another embodiment, switch 404 is a triac device.

0055(48) Figure 6 depicts exemplary phase modulated waveforms of supply voltage/calibration data V_SUPPLY/DATA- In at least one embodiment, to help ensure accurate decoding by controller 202 (Figure 2), phase angles indicating logical "0" and logical "1" are sufficiently separated to avoid overlap and, thus, ambiguity as to the encoded data. For example, for each cycle of supply voltage/calibration data VSU_PPLY/_DATA 602, phase angles from 0° to 45° in the first half cycle and phase angles from 180° and 225° of supply voltage/calibration data V_SUPPLY/DATA indicate a logical "0". For each cycle of supply voltage/calibration data V_SUPPLY/DATA 602, Phase angles from 135° to 180° in the first half cycle and phase angles from 315° and 360° of supply voltage/calibration data V_SUPPLY/DATA indicate a logical "1". Exemplary supply voltage/calibration data VSU_PPLY/_DATA 604 encodes "0110". Exemplary supply voltage/calibration data V_SUPPLY/DATA 606 encodes "10" by phase modulating trailing edges of each half cycle of a cycle supply voltage/calibration data V_SUPPLY/DATA followed by phase modulating leading edges of each half cycle.

0056(49) Figure 7 depicts calibration unit 700, which represents one embodiment of calibration unit 210. Calibration unit 700 includes calibration controller 702. Calibration controller 702 compares the lighting data signal LDATA with the target light value TLV as previously described to determine the calibration data to provide to controller 202 (Figure 2) so as to bring lamp 204 within a tolerance level. Calibration controller 702 generates a pulse width modulated calibration modulation signal CAL_CS to control the duty cycle of high speed switch system 704. Voltage source 706 supplies a DC supply voltage V_DD to high speed switch system 704. Voltage source 706 represents one embodiment of voltage source 212 (Figure 2). High speed switch(es) 704 modulate the supply voltage V_DD to generate a pulse width modulated supply voltage/calibration data V_SUPPLY/DATA. Variations in the duty cycle of calibration modulation signal CAL CS represent encoded binary data in supply voltage/calibration data VSU_PPLY/_DATA. The frequency of calibration modulation signal CAL_CS determines the data transfer rate of supply voltage/calibration data V_SUPPLY/DATA- The data transfer rate using calibration controller 702 can be much larger than the data transfer rate achievable with calibration unit 400 because the data transfer rate of calibration controller 702 is dependent on the frequency of calibration modulation signal CAL_CS and responsiveness of high speed switch system 704 rather than on the frequency of the supply voltage VSU_PPLY-

0057(50) Figure 8 depicts high speed switch system 800, which represents one embodiment of high speed switch system 704. The calibration modulation signal CAL_CS is applied directly to the gate of n-channel field effect transistor (FET) 802 and indirectly to the gate of n-channel FET 804 through inverter 806. Resistor 808 limits the current supplied by voltage source 706 (Figure 7). Referring to Figures 2 and 9, the value of resistor 808 is selected so that an adequate amount of current i_Ls is supplied to light source 216 to generate a desired brightness of light 218. Referring to Figure 8, the duty cycle of each pulse of supply voltage/calibration data V_SUPPLY/DATA tracks the duty cycle of each pulse of calibration modulation signal calibration modulation signal CAL_CS. Thus, the data indicated by the duty cycle of each pulse of calibration modulation signal CAL_CS is encoded in supply voltage/calibration data VSUPPLY/DATA-

0058(51) Figure 9 depicts high speed switch system 900, which also represents one embodiment of high speed switch system 704. The calibration modulation signal CAL CS is applied directly to the gate of n-channel FET 902. Resistor 904 limits the current supplied by voltage source 706 (Figure 7). Referring to Figures 2 and 9, the value of resistor 808 is selected so that an adequate amount of current Ϊ_LS is supplied to light source 216 to generate a desired brightness of light 218. Referring to Figure

00599, the duty cycle of each pulse of supply voltage/calibration data V_SUPPLY/DATA tracks the duty cycle of each pulse of calibration modulation signal calibration modulation signal CAL_CS. Thus, the data indicated by the duty cycle of each pulse of calibration modulation signal CAL_CS is encoded in supply voltage/calibration data VSU_PPLY/_DATA. Referring to Figures 8 and 9, high speed switch system 900 contains fewer components than high speed switch system 800. However, unlike high speed switch system 800, current flows in high speed switch system 900 regardless of the logical value of calibration modulation signal CALIBRATION MODULATION SIGNAL CAL_CS, which is generally less efficient.

0060(52) Figure 10 depicts exemplary encoding of supply voltage/calibration data V_SUPPLY/DATA by calibration modulation signal CAL_CS. Referring to Figures 7 and

006110, calibration controller 702 duty cycle modulates calibration modulation signal CAL_CS to encode calibration data in supply voltage/calibration data V_SUPPLY/DATA based on the comparison between the lighting data LDATA and the target light value TLV. In at least one embodiment, a duty cycle of calibration modulation signal CAL_CS greater than or equal to 75% represents a logical "1", and a duty cycle less than or equal to 25% represents a logical "0". The exemplary calibration modulation signal CAL CS 1002 represents binary data "10100". Calibration unit 700 modulates the supply voltage V_DD to encode supply voltage/calibration data VSU_PPLY/_DATA 1004 with the same binary data as calibration modulation signal CAL CS 1002. The peak voltage V_PEAK of supply voltage/calibration data VSU_PPLY/_DATA is maintained so that the average voltage of supply voltage/calibration data VSU_PPLY/_DATA provides sufficient operating voltage to lamp 204. (53) Figure 11 depicts controller 1100, which represents one embodiment of controller 202. Controller 1100 includes two controllers, lamp calibration controller 1101 and lamp driver controller 1110. Lamp calibration controller 1101 is active during calibration mode to allow controller 1100 to calibrate lamp 204. In at least one embodiment, lamp calibration controller 1101 is inactive after completion of calibration. In at least one embodiment, lamp calibration controller 1101 is used to decode and process dimming levels indicated by phase angles in V_{SUPPLY D} during normal use. Lamp driver controller 1110 generates control signal CSi to control lamp driver 222 and generates control signal CS₂ to directly control current in light source 216. Lamp calibration controller 1101 receives data signal V_{SUPPLY D}, which contains the data encoded in supply voltage/calibration data V_SUPPLY/DATA. In at least one embodiment, the supply voltage/calibration data VSU_PPLY/_DATA received by lamp driver controller 1110 is a sampled version of supply voltage/calibration data V_SUPPLY/DATA. In one embodiment, data signal V_{SUPPLY D} is supply voltage/calibration data VSU_PPLY/_DATA. In another embodiment, data signal VSU_{PPLY D} is a sampled value of supply voltage/calibration data V_SUPPLY/DATA. In at least one embodiment, data signal VSU_PPLY D is a sampled value of supply voltage/calibration data VSU_PPLY/_DATA sampled prior to any electromagnetic interference filtering. Decoder 1102 decodes the data encoded in data signal V_{SUPPLY D} and generates data signal D_v. Processor 1104 processes data signal Dy to determine the calibration data CAL D ATA provided by calibration unit 210. As subsequently described in more detail, controller 1100 utilizes the calibration data CAL D ATA to calibrate lamp 204. Processor 1104 writes the calibration data CAL D ATA to nonvolatile memory 1106 and writes calibration data CAL D ATA to random access memory (RAM) 1108 during calibration and during normal use of lamp 204. As subsequently described, in at least one embodiment, processor 1104 is a state machine.

0062(54) Lamp driver controller 1110 receives light source current feedback signal Ϊ_{LS FB} representing the current in light source 216. In at least one embodiment, lamp driver controller 1110 utilizes the calibration data CAL D ATA as a target value to compare against the light source current feedback signal Ϊ_LS _FB. The lamp driver controller 1110 then adjusts the control signal CS₂ to drive the light source current feedback signal i_{LS FB} towards the target value indicated by calibration data CAL D ATA. Thus, for example, if the calibration data CAL D ATA indicates that light source 216 is not bright enough, lamp driver controller 1110 generates control signal CSi to cause lamp driver 216 to increase the current in light source 216. If the calibration data CAL D ATA indicates that light source 216 is too bright, lamp driver controller 1110 generates control signal CSi to cause lamp driver 216 to decrease the current in light source 216. Thus, in at least one embodiment the calibration data CAL_DATA represents a predefined target value plus or minus an offset value. In at least one embodiment, supply voltage/calibration data V_SUPPLY/DATA supplies the offset value.

0063(55) Referring to Figures 2 and 11, calibration unit 210 encodes supply voltage/calibration data V_SUPPLY/DATA in data packet 1112. The particular data format of data packet 112 is a matter of design choice. In at least one embodiment, data packet 1112 has a predetermined format of four data blocks. Data packet 1112 includes a key block 1114. Key block 1114 contains a binary sequence that alerts lamp calibration controller 1101 to enter calibration mode. Data packet 1112 also includes a command block 1116. The data in command block 1116 represents specific commands to be executed by processor 1104. The CAL D ATA block 1118 contains the calibration data. The checksum block 1120 contains a checksum to allow processor 1104 to determine whether the data in supply voltage/calibration data VSUPPLY/DATA and data signal V SUPPLY _D are accurate or corrupted.

0064(56) Figure 12 depicts decoder 1200, which represents one embodiment of decoder 1102. Comparator 1202 compares data signal V_{SUPPLY D} against a known reference 1203. To detect phase angles of a phase modulated data signal V_{SUPPLY D}, the reference 1203 is generally the cycle cross-over point voltage of data signal V_{SUPPLY D}, such as a neutral potential of voltage source 212. To detect duty cycles of a pulse width modulated data signal V_{SUPPLY D}, the reference 1203 is a potential representing a logical zero. The timer 1204 counts the number of cycles of clock signal f_ci_k that occur until the comparator 1202 indicates an edge of data signal V_{SUPPLY D}- Digital data Dy represents the count. Since the frequency of data signal VSU_PPLY D and the frequency of clock signal f_cik is known, the phase angle can be determined from the count of cycles of clock signal f_ci_k that occur until the comparator 1202 indicates that an edge of data signal V_{SUPPLY D} is present, e.g. upon transition of a logical state of an output of comparator 1202 from one logical state to another. Likewise, the duty cycle can be determined from the count of cycle of clock signal f_clk that occur between edges of data signal VSU_PPLY __D-

0065(57) Figure 13 depicts lamp driver controller 1300, which represents one embodiment of lamp driver controller 1110. Lamp driver controller 1300 receives calibration data CAL D ATA from RAM 1108. Comparator 1304 compares the light source current feedback signal Ϊ_{LS FB} with calibration data CAL_DATA. Referring to Figures 2 and 13, in at least one embodiment, the calibration data CAL D ATA is set so that when the light source current feedback signal i_{LS FB} matches the calibration data CALIBRATION DATA CAL D ATA, the brightness of light source 216 is within a tolerance level. Error signal i_{LS E} represents the difference between light source current feedback signal i_Ls _FB and calibration data CAL_DATA. In at least one embodiment, if the error signal i_{LS E} indicates that light source current feedback signal i_{LS FB} is greater than calibration data CALIBRATION DATA CAL D ATA, the switch state controller 1302 is configured to generate control signal CSi to cause the current in light source 216 to decrease. Likewise, if the error signal i_{LS E} indicates that light source current feedback signal i_Ls _FB is less than calibration data CALIBRATION DATA CAL D ATA, the switch state controller 1302 is configured to generate control signal CSi to cause the current in light source 216 to increase. U.S. Patent Application No. 12/047,249, entitled "Ballast for Light Emitting Diode Light Sources", inventor John L. Melanson, assignee Cirrus Logic, Inc., and filed on March 12, 2008 (referred to herein as "Melanson II") and U.S. Patent Application No. 11/864,366, entitled "Time-Based Control of a System having Integration Response," inventor John L. Melanson, assignee Cirrus Logic, Inc., and filed on September 28, 2007 (referred to herein as "Melanson III") describe exemplary methods and systems including an exemplary switch state controller 1302. Melanson II and Melanson III are hereby incorporated by reference in their entireties.

0066(58) Figure 14 represents state machine diagram 1400, which represents one embodiment of a state machine for processor 1104. Referring to Figures 11 and 14, if the root mean square (RMS) value of supply voltage/calibration data VSU_PPLY/_DATA RMS is less than a predetermined minimum supply voltage/calibration data VSU_PPLY/_DATA RMS MiN, then processor 1104 enters a startup state 1402. If the link voltage V_LIN_K is greater than a minimum link voltage V_LIN_{K MI}N, the processor 1104 enters a normal use state 1404. In at least one embodiment, the predetermined minimum supply voltage/calibration data VSU_PPLY/_{DATA RM}S _MIN is 90V RMS, and the minimum link voltage V_{LINK MIN} is 380 VDC. After start up and before the processor 1104 enters the normal use state 1404, a NORMAL bit is set to 0, and processor 1104 resets in the reset state 1406 and continues in the reset state 1406 if bit CAL_DISABLE = 1 until V_LIN_K is greater than the minimum link voltage V_LIN_{K MI}N- In at least one embodiment, the CAL DISABLE bit = 1 prevents the processor 1104 from reentering calibration mode regardless of the data encoded in V _SUPPLY __D- Once processor 1104 enters the normal use state 1404, the NORMAL bit is set to 1. If the CAL DISABLE bit = 0, the processor 1104 enters a calibration program seek state 1408. In the calibration program seek state 1408, processor 1104 analyzes the data in data signal V_{SUPPLY D} from calibration unit 210 to determine if the key block 1114 of data signal V_{SUPPLY D} contains a predetermined calibration start sequence of bits instructing processor 1104 to enter calibration mode. In at least one embodiment, the calibration start sequence is 0110110110. If the key block 1114 contains the calibration start sequence and processor 1104 determines that the sum of the bits in data packet 1112 match the checksum in checksum block 1120, processor 1104 sets a SEQUENCE MATCH bit to 1. Otherwise, the SEQUENCE MATCH bit is set to 0.

0067(59) If the SEQUENCE_MATCH bit is set to 1, processor 1104 executes the command indicated by the bit(s) in command block 1116 send from calibration unit 210. In at least one embodiment, calibration unit 210 commands lamp calibration controller 1101 to temporarily write calibration data CAL D ATA to memory (such as memory 1106) until lamp 204 is within a tolerance level. In at least one embodiment, calibration unit 210 commands lamp calibration controller 1101 to permanently write calibration data CAL D ATA to memory (such as memory 1106) when lamp 204 is within a tolerance level. If the command is a "write" command, from the write CAL D ATA state 1412 processor 1104 writes the calibration data CAL D ATA to memory 1106 and then returns to the calibration program seek state 1408. If the command is a "burn" command, from the burn CAL D ATA state 1414 processor 1104 burns the calibration data calibration data CAL D ATA to memory 1106 so that calibration data CAL D ATA is permanently stored in memory 1106 and then returns to the calibration program seek state 1408. In at least one embodiment, the "write" command allows the lamp 204 to undergo multiple calibration cycles and, thus, iterate the calibration data CAL D ATA until the lighting data signal LDATA indicates that lamp 204 is within a tolerance level. In at least one embodiment, the number of calibration cycles is limited, and, upon reaching the limit, the lamp calibration system 200 indicates that the lamp 204 failed to operate with an acceptable tolerance level. In at least one embodiment, calibration unit 210 sends the "burn" command if the lighting data signal LDATA indicates that lamp 204 is within an acceptable tolerance level. Thus, after burning the calibration data CAL D ATA in state 1414, processor 1104 enters the calibration program seek state 1408, sets the CAL DISABLE bit = 1, and returns to the reset state 1406 until the lamp 204 enters the startup state 1402 or normal state 1404.

0068(60) Figure 15 depicts lamp 1500, which represents one embodiment of lamp 204. Full-bridge diode rectifier 1502 rectifies supply voltage/calibration data VSU_PPLY/_DATA into rectified supply voltage/calibration data VS_DR. In at least one embodiment, data signal V _SUPPLY __D is taken before electromagnetic interference ("EMI") filter 1504 to avoid attenuation of data signal V_{SUPPLY D} by EMI filter 1504. Switching power converter 1506 represents one embodiment of lamp driver 222. Switching power converter 1506 is configured as a boost converter such that the inductor current Ϊ_L in inductor 1508 ramps up when switch 1510 conducts, thus increasing the voltage across inductor 1508. When switch 1510 stops conducting, diode 1512 conducts, and inductor current Ϊ_L charges capacitor 1514 to link voltage V_LIN_K. When switch 1510 conducts, diode 1512 prevents capacitor 1514 from discharging through switch 1510.

0069(61) Controller 1516 represents one embodiment of controller 202 and lamp driver controller 1300. Controller 1516 generates control signal CSo to provide power factor correction and regulate the link voltage V_LINK- Exemplary power factor correction and regulation of the link voltage V_LINK are described in U.S. Patent Application No.

007011/967,269, entitled "Power Control System Using a Nonlinear Delta-Sigma Modulator with Nonlinear Power Conversion Process Modeling," inventor John L. Melanson, Attorney Docket No. 1745-CA, and filed on December 31, 2007 (referred to herein as "Melanson IV") and U.S. Patent Application No. 11/967,275, entitled "Programmable Power Control System," inventor John L. Melanson, Attorney Docket No. 1759-CA, and filed on December 31, 2007 (referred to herein as "Melanson V"). Melanson IV and Melanson V are hereby incorporated by reference in their entireties.

0071(62) Controller 1516 also generates control signals CS₂ to control the current in LED string 1518 of light source 1520. LED string 1518 includes one or more LEDs. The voltage across resistor 1530 is fed back as feedback signal Ϊ_LS _FB to controller 1516. The feedback signal 1_LS__FB represents the current in LED string 1518. Controller 1516 generates CS₂ by comparing the feedback signal Ϊ_{LS FB} calibration data CALIBRATION DATA CAL D ATA as described with reference to lamp driver controller 1300 (Figure 13). Control signal CS₂ controls the duty cycle of switch 1522 to control the average lamp current i_LS and, thus, control the brightness of LED string 1518. Diode 1524 permits current flow in only one direction. Inductors 1526 and capacitor 1528 regulate the voltage across the LED string 1518 and provide filtering.

0072(63) Thus, a lamp includes a controller configured to generate power control signals for a lamp is also configured to receive lamp calibration data received via one or more power terminals of the lamp. The controller is configured to process the calibration data to calibrate the lamp.

0073(64) Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.