Amplifying circuit, AC signal amplifying circuit and input bias adjusting method

FIELD

0001The embodiments discussed herein are related to an amplifying circuit for amplifying an input signal.

BACKGROUND

0002<figref idref="f0001">Figure 1</figref> is an explanatory diagram illustrating a configuration example of an amplifying circuit. The amplifying circuit includes an n-channel field-effect transistor (FET) 101 for amplifying an input signal supplied from a signal source 100. The input signal from the signal source 100 is first passed through a resistor R10 and then fed into a capacitor C10 where the DC component of the input signal is removed. The input signal whose DC component is thus removed, and then summed with a gate bias voltage, and the resulting signal is applied to the gate terminal of the FET 101. The gate bias voltage is supplied from a power supply line that supplies predetermined voltage v_g via a resistor R11, which is grounded via a capacitor C11.

0003The drain terminal of the FET 101 is coupled via an inductor L10 to a power supply line that supplies voltage V_d. This power supply line is grounded via a capacitor C12. The amplified signal obtained by amplifying the input signal by the FET 101 is output from its drain terminal and applied via a DC component removing capacitor C13 to a load 102.

0004The gate voltage biasing method of the FET 101 include a class of operation intended for power conservation, which is described as class B operation, class C operation, etc., according to the magnitude of the voltage applied to the gate. The biasing method further includes a class of operation described as class AB operation in which bias current flows even during a period when there is no input signal in order to avoid signal waveform distortion that occurs near the pinch-of voltage, though this operation increases power consumption compared with the above two classes.

0005There is proposed a class AF3 operating transistor power amplifying circuit for amplifying an amplitude-modulated wave, which includes a detector for detecting a portion of an input signal, an impedance conversion circuit for performing impedance conversion on the output of the detector, a time constant circuit for integrating the output of the impedance conversion circuit, and an amplifying circuit for amplifying the output of the time constant circuit. The base bias of this transistor power amplifying circuit is controlled by the output of the amplifying circuit.

0006There is also proposed a power amplifier wherein when amplifying an input power signal by a class B or class AB amplifier, the gate voltage can be set to the operating point of FET without an operator having to make an adjustment for setting the gate voltage to the operating point. This power amplifier includes a first field-effect transistor which amplifies the input power signal applied to its gate terminal and outputs the amplified signal at its drain terminal, a bias setting circuit which applies a predetermined voltage to the gate-terminal while maintaining a first drain current applied to the drain terminal at a predetermined value, a detector circuit which produces a voltage signal proportional to the magnitude of the input power signal and sends it out from an output terminal, and a current supply circuit which supplies the drain terminal with a second drain current corresponding to the voltage signal received from the detector circuit.

0007Related art is disclosed in Japanese Laid-open Patent Publication No. <patcit id="pcit0001" dnum="JPH03249810B"><text>H03-249810</text></patcit> and Japanese Laid-open Patent Publication No. <patcit id="pcit0002" dnum="JP2004274316A"><text>2004-274316</text></patcit>.

SUMMARY

0008An object of the device and method discussed herein is to improve the reproducibility of the waveform of an amplified signal when amplifying an input signal by an amplifying circuit.

0009Another object of the device and method discussed herein is to improve power utilization efficiency when amplifying an input signal by an amplifying circuit.

0010According to one embodiment, there is provided an amplifying circuit for amplifying a signal having a waveform that alternates repeatedly between a first section where a signal value varies within a variation range limited by at least one of upper and lower limit values and a second section that is a section other than the first section, including: an amplifying unit which amplifies the input signal and applies the amplified signal to a designated load; a current detection unit which detects a load current that flows into the designated load upon application of the amplified signal; an estimating unit which calculates, based on the voltage level of the input signal, an estimated value of the load current to be supplied to the load; and an adjusting unit which adjusts an input bias, to be applied to the amplifying unit, in such a manner so as to reduce a difference value representing a difference between the estimated value and the load current detected by the current detection unit.

BRIEF DESCRIPTION OF DRAWING(S)

0011<ul id="ul0001" list-style="none" compact="compact"><li><figref idref="f0001">Figure 1</figref> is an explanatory diagram illustrating a configuration example of an amplifying circuit;</li><li><figref idref="f0002">Figure 2</figref> is an explanatory diagram illustrating the waveform of is first example of an input signal;</li><li><figref idref="f0003">Figure 3</figref> is an explanatory diagram illustrating the shape of an output waveform produced by the amplifying circuit depicted in <figref idref="f0001">Figure 1</figref>;</li><li><figref idref="f0004">Figure 4</figref> is an explanatory diagram illustrating a configuration example of an amplifying circuit according to the present disclosure;</li><li><figref idref="f0005">Figure 5</figref> is an explanatory diagram illustrating 13. first configuration example of an amplifying unit;</li><li><figref idref="f0005">Figure 6</figref> is an explanatory diagram illustrating a configuration example of a bias determining unit;</li><li><figref idref="f0006">Figure 7</figref> is an explanatory diagram illustrating how an average input voltage is calculated;</li><li><figref idref="f0007">Figures 8A and 8B</figref> are explanatory diagrams illustrating first and second configuration examples, respectively, of a bias adjusting unit;</li><li><figref idref="f0008">Figures 9A and. 9B</figref> are explanatory diagrams each illustrating a function f(ΔI) that is used to determine a bias correction amount ΔV_g;</li><li><figref idref="f0009">Figure 10</figref> is an explanatory diagram illustrating a bias adjusting method according to the present disclosure;</li><li><figref idref="f0009">Figure 11</figref> is an explanatory diagram illustrating a second configuration example of the amplifying unit;</li><li><figref idref="f0010">Figure 12</figref> is an explanatory diagram illustrating the waveform of a second example of the input signal;</li><li><figref idref="f0011">Figure 13</figref> is an explanatory diagram illustrating a third configuration example of the amplifying unit; and</li><li><figref idref="f0011">Figure 14</figref> is an explanatory diagram illustrating a configuration example of an AC signal amplifying circuit according to the present disclosure.</li></ul>

DESCRIPTION OF EMBODIMENT(S)

0012As described previously, class B operation is intended for power conservation, which is the example of signal waveform that can be inputted to a class B amplifier.

0013<figref idref="f0002">Figure 2</figref> is an explanatory diagram illustrating the waveform of a first example of the input signal. The input signal waveform alternates repeatedly between a first section T1 where there is a waveform to be amplified and a second section T2 where there is not. In the first section T1, the signal value varies within a range limited by a lower limit value V_L. For example, in the input signal example illustrated in <figref idref="f0002">Figure 2</figref>, the waveform has a shape similar to that of a half-wave and, during the second section T2, the signal remains unchanged with its signal value maintained substantially at the lower limit value V_L. When amplifying the waveform having the above-described characteristic, since there is no signal waveform to be amplified in the second section T2, there is no need to amplify the portions of the waveform that lie in regions below the lower limit value. Therefore, amplifier power consumption can be reduced by using a class B amplifier.

0014Next, referring to <figref idref="f0003">Figure 3</figref>, a description will be given of the shape of the output waveform produced when the waveform having the characteristic described above with reference to <figref idref="f0002">Figure 2</figref> is amplified by the amplifying circuit of <figref idref="f0001">Figure 1</figref> which is operated in class B. The semi-dashed line indicates the input signal waveform having the above-described characteristic. The dashed line indicates the DC level of the input signal. The solid line indicates the waveform of the signal output from the drain terminal of the FET 101, the waveform here being inverted for ease of comparison.

0015When the gate bias voltage is added to the input signal passed through the DC component removing capacitor C10, the DAC level of the input signal indicated by the dashed line becomes equal to the gate bias voltage. When the amplifying circuit is used as a class B amplifying circuit, since the gate bias voltage is set at or near the pinch-off voltage, the portions of the waveform that lie in regions where the voltage level is lower than the gate bias voltage are not amplified.

0016When the signal having the characteristic described above with reference to <figref idref="f0002">Figure 2</figref> is input to the class B amplifying circuit, the DAC level the input signal becomes larger than the lower limit value V_L. For example, in the case of the waveform illustrated in <figref idref="f0002">Figure 2</figref>, the signal value in the second section T2 is approximately equal to the lower limit value V_L, but the DC level of the input signal is larger than the lower limit value V_L. As a result, if the input signal is supplied to the class B amplifier after removing the DC component of the signal, the output waveform will have a shape such that the input waveform is sliced at the DC level. If a bipolar transistor is used instead of the FET 101, the output waveform will also have a shape such that the input waveform is sliced at the cutoff voltage.

0017Further, in the case of a class B amplifying circuit using an FET, for example, the bias voltage is set at or near the pinch-off voltage, and in the case of a class B amplifying circuit using a bipolar transistor, for example, the bias voltage is set at or near the cutoff voltage. If these bias voltages are not set appropriately, either the reproducibility of the amplified waveform worsens or power consumption increases.

0018Therefore, in a class B amplifier, if the DC component of the input signal is removed, the output waveform may have a shape such that the input waveform is sliced at the DC level, and this can impair the reproducibility of the waveform. To address this, a method was considered that superimposes the bias voltage directly on the input signal, rather than removing the DC component at the input. For example, in the case of an amplifying circuit that uses an FET as an amplifying device as illustrated in <figref idref="f0001">Figure 1</figref>, the gate bias voltage is superimposed directly on the input signal, after which the input signal is applied to the gate of the FET without passing it through the DC component removing capacitor C10.

0019In this case also, if the gate bias voltage is too low, the output waveform will have a shape such that the input waveform is sliced. Conversely, if the gate bias voltage is too high, the drain current will flow excessively, increasing the power consumption. In view of this, the class B amplifying circuit according to the embodiment described herein is provided with a bias determining unit that determines the input bias.

0020The embodiment will be described below with reference to the accompanying drawings. <figref idref="f0004">Figure 4</figref> is an explanatory diagram illustrating a configuration example of the amplifying circuit according to the present disclosure. Reference numeral 1 represents the amplifying circuit, and reference numeral 2 indicates a load; further, reference numeral 11 indicates an adder, and 12 indicates a digital-analog converter (DAC). Reference numeral 13 indicates an amplifying unit, 14 indicates a current detection unit, and 15 indicates an analog-digital converter (ADC); the bias determining unit is indicated at 16. Reference numeral 17 indicates an input line via which the input signal is applied to the amplifying circuit 1, and 18 indicates an output line via which an amplified signal produced by amplifying the input signal is output from the amplifying circuit 1 to the load 2.

0021In the amplifying circuit 1, the input signal supplied in digital form is first converted into an analog signal which is then amplified by a predetermined voltage gain A, and the amplified signal produced by thus amplifying the input signal is applied to the load 2. The signal having the characteristic earlier described with reference to <figref idref="f0002">Figure 2</figref> is input to the amplifying circuit 1, and the amplifying circuit 1 is used to amplify such an input signal.

0022The adder 11, the DAC 12, the amplifying unit 13, the current detection unit 14, the ADC 15, and the bias determining unit 16 together constitute the amplifying circuit 1. The adder 11 adds a bias voltage V_q(t) to the input signal and supplies the resulting signal to the DAC 12. The bias voltage V_g(t) is determined by the bias determining unit 16 at every predetermined interval of time. Time t indicates the determination timing at which the bias voltage V_g(t) is determined.

0023V_g(t) represents the input bias voltage of the amplifying unit 13 that is determined at a given determination timing t. As will be described later, when the amplifying unit 13 uses an FET as the amplifying device, V_g(t) may be the gate bias voltage of the FET.

0024The DAC 12 converts the sum of the input signal and the bias voltage V_g(t) into an analog signal which is then supplied to the amplifying unit 13. The amplifying unit 13 amplifies the input signal by the predetermined voltage gain A and applies the resulting amplified, signal to the load 2.

0025The current detection unit 14 detects a load current I_det that flows from a power supply line into the load 2 under the control of the amplifying unit 13. When the amplifying unit 13 uses an FET as the amplifying device, as described below, the current I_det may be the drain current of the FET. Further, rather than an instantaneous value of the load current I_det, the current detection unit 14 may output its average value as the detection result. The ADC 15 converts the load current I_det into a digital signal.

0026The bias determining unit 16 determines the bias voltage V_g(t) based on the input signal and the load current I_det.

0027<figref idref="f0005">Figure 5</figref> is an explanatory diagram illustrating a first configuration example of the amplifying unit 13. Reference numeral 20 indicates an n-channel FET, R1 indicates a resistor, C1, C2, and C3 indicate capacitors, and L1 indicates an inductor. The amplifying unit 13 includes a source grounding circuit for the FET 20 which is used as the amplifying device. The output signal from the DAC 12 its applied to the gate terminal of the FET 20, and the drain terminal of the FET 20 is coupled via the inductor Il and the current detection unit 14 to the power supply line that supplies voltage. This power supply line is grounded via the capacitor C2.

0028The drain and gate terminals of the FET 20 is connected together by a feedback line having a series connection of the resistor R1 and the capacitor C1. The voltage gain of the FET 20 is controlled to the predetermined value A through this feedback line. The FET 20 amplifies the output signal of the DAC 12 by the predetermined voltage gain A, and supplies the resulting amplified signal to the load 20 via the DC component removing capacitor C3.

0029<figref idref="f0005">Figure 6</figref> is an explanatory diagram illustrating a configuration example of the bias determining unit 16. Reference numeral 30 indicates a load current estimating unit, 31 indicates a difference calculation unit, and 32 indicates a bias adjusting unit. The load current estimating unit 30, the difference calculation unit 31, and the bias adjusting unit 32 together constitute the bias determining unit 16.

0030All or some of the constituent elements 30 to 32 of the bias determining unit 16 may be implemented on a dedicated hardware circuit. The bias determining unit 16 may include a processor and a storage device for storing an operating program for the processor. All or some of the functions of the constituent elements 30 to 32 may be implemented by the processor executing the operating program. The bias determining unit 16 may include a programmable LSI such as an FPGA. The FPGA may be configured to implement all or some of the functions of the constituent elements 30 to 32.

0031The load current estimating unit 30 calculates an estimated value I_cal of the load current based on the voltage level of the input signal. The load current estimating unit 30 calculates the estimated value I_cal, for example, by the following method.

0032First, the load current estimating unit 30 calculates an average input voltage which represents the average difference between the input signal and the lower limit value V_L of the signal in the first section T1. <figref idref="f0006">Figure 7</figref> is an explanatory diagram illustrating how the load current estimating unit 30 calculates the average input voltage S_p. The load current estimating unit 30 divides the measurement time of the input signal voltage on the basis of a predetermined integration period T_s. The load current estimating unit 30 calculates the average input voltage S_p in accordance with the following equation (1); i.e., an integrated value calculated by integrating over each integration period the difference (V_in - V_L) between the input voltage V_in and the lower limit value V_L of the signal in the first section T1 of <figref idref="f0002">Figure 2</figref> is divided by the integration period T_s. <maths id="math0001" num="(1)"><math display="block"><msub><mi mathvariant="normal">S</mi><mi mathvariant="normal">P</mi></msub><mo mathvariant="normal">=</mo><mfrac><mstyle displaystyle="true"><mstyle displaystyle="false"><mstyle displaystyle="true"><munder><mo mathvariant="normal">∑</mo><msub><mi mathvariant="normal">T</mi><mi mathvariant="normal">S</mi></msub></munder></mstyle><mfenced open="{" close="}"><mfenced><msub><mi mathvariant="normal">V</mi><mi>in</mi></msub><mo mathvariant="normal">-</mo><msub><mi mathvariant="normal">V</mi><mi mathvariant="normal">L</mi></msub></mfenced><mo mathvariant="normal">×</mo><mi mathvariant="normal">ΔT</mi></mfenced></mstyle></mstyle><msub><mi mathvariant="normal">T</mi><mi mathvariant="normal">S</mi></msub></mfrac></math><img file="EP2244378A2_D0001.tif" /></maths>

0033In equation (1), ΔT denotes the sampling period of the input signal. Next, the load current estimating unit 30 calculates the estimated value I_cal in accordance with the following equation (2). <maths id="math0002" num="(2)"><math display="block"><msub><mi mathvariant="normal">I</mi><mi>cal</mi></msub><mo mathvariant="normal">=</mo><mfenced><msub><mi mathvariant="normal">S</mi><mi mathvariant="normal">p</mi></msub><mo mathvariant="normal">×</mo><mi mathvariant="normal">A</mi></mfenced><mo mathvariant="normal">/</mo><mi>ZL</mi></math><img file="EP2244378A2_D0002.tif" /></maths>

0034In equation (2), constant A is the voltage gain of the amplifying unit 13, and constant ZL is the resistance of the load 2.

0035Reference is made to <figref idref="f0005">Figure 6</figref>. The difference calculation unit 31 calculates a difference ΔI in accordance with the following equation (3) by subtracting the load current I_det detected by the current detection unit 14 from the estimated value I_cal calculated by the load current estimating unit 30. <maths id="math0003" num="(3)"><math display="block"><mi mathvariant="normal">ΔI</mi><mo mathvariant="normal">=</mo><msub><mi mathvariant="normal">I</mi><mi>cal</mi></msub><mo mathvariant="normal">-</mo><msub><mi mathvariant="normal">I</mi><mi>det</mi></msub></math><img file="EP2244378A2_D0003.tif" /></maths>

0036Alternatively, the difference calculation unit 31 may calculate the difference ΔI in accordance with the following equation (4) by adding a predetermined adjusting constant to the value obtained by subtracting the load current I_det from the estimated value I_cal. <maths id="math0004" num="(4)"><math display="block"><mi mathvariant="normal">ΔI</mi><mo mathvariant="normal">=</mo><msub><mi mathvariant="normal">I</mi><mi>cal</mi></msub><mo mathvariant="normal">-</mo><msub><mi mathvariant="normal">I</mi><mi>det</mi></msub><mo mathvariant="normal">+</mo><mi mathvariant="normal">B</mi></math><img file="EP2244378A2_D0004.tif" /></maths>

0037The bias adjusting unit 32 adjusts the bias voltage V_g(t) (i.e., the gate bias voltage of the FET 20) in such a manner as to reduce the difference ΔI. <figref idref="f0007">Figure 8A</figref> is an explanatory diagram illustrating a first configuration example of the bias adjusting unit 32. Reference numeral 33 indicates a correction amount calculation unit, and 34 indicates an adder. The correction amount calculation unit 33 and the adder 34 together constitute the bias adjusting unit 32.

0038Based on the difference ΔI, the correction amount calculation unit 33 calculates a bias correction amount ΔV_g, i.e., the amount by which to correct the bias voltage V_g(t). The adder 34 corrects the bias voltage V_g(t) by adding the bias correction amount ΔV_g to the bias voltage V_g(t-1) determined at the immediately preceding determination timing (t-1).

0039<figref idref="f0008">Figures 9A and 9B</figref> are explanatory diagrams each illustrating a function f(ΔI) that is used to determine the bias correction amount ΔV_g. The correction amount calculation unit 33 calculates the bias correction amount ΔV_g by using the function f(ΔI) whose independent variable is the difference ΔI, as given by the following equation (5). <maths id="math0005" num="(5)"><math display="block"><msub><mi mathvariant="normal">ΔV</mi><mi mathvariant="normal">g</mi></msub><mo mathvariant="normal">=</mo><mi mathvariant="normal">f</mi><mfenced><mi mathvariant="normal">ΔI</mi></mfenced></math><img file="EP2244378A2_D0005.tif" /></maths>

0040The function f(ΔI) is a monotonically increasing function having a function value "0" for a given difference ΔI0. When the difference ΔI is relatively large, i.e., when the actual detected value I_det (i.e., the load current) is smaller than the value I_cal estimated from the input signal, the sign of ΔV_g is positive. As a result, the bias voltage V_g(t) is increased, thus increasing the load current. Since the actual detected value Idol thus increases, the difference between the estimated value and the actual detected value I_det reduces.

0041Conversely, when the difference ΔI is relatively small, i.e., when the actual detected value I_det is larger than the value I_cal estimated from the input signal (the load current is excessive), the sign of ΔV_g is negative. As a result, the bias voltage V_g(t) is reduced, thus reducing the load current. Since the actual detected value I_det thus reduces, the difference between the estimated value I_cal and the actually detected value I_det reduces.

0042The function f(ΔI) may be a function whose slope changes as its value departs from the given difference ΔI0, as depicted in <figref idref="f0008">Figure 9A</figref>. For example, the function f(ΔI) may be a function whose slope increases as its value departs from the given difference ΔI0. Alternatively, the function f(ΔI) may be a function whose value is proportional to ΔI, as depicted in <figref idref="f0008">Figure 9B</figref>.

0043<figref idref="f0007">Figure 8B</figref> is an explanatory diagram illustrating a second configuration example of the bias adjusting unit 32. Reference numeral 35 indicates a smoothing unit.

0044The correction amount calculation unit 33, the adder 34, and the smoothing unit 35 together constitute the bias adjusting unit 32.

0045The smoothing unit 35 smoothes the variation of the difference ΔI. The smoothing unit 35 outputs difference ΔI_f by smoothing the variation of the difference ΔI. The smoothing unit 35 may be configured to smooth the variation of the difference ΔI by calculating the moving average value of the difference ΔI and taking it as the difference AI_f. For example, the smoothing unit 35 may be implemented as an accumulator that stores the difference ΔI calculated in each of the past (n+1) integration periods as ΔI(i) (i is an integer between 0 and n) and that calculates the smoothed difference ΔI_f in accordance with the following equation (6). <maths id="math0006" num="(6)"><math display="block"><msub><mi mathvariant="normal">ΔI</mi><mi mathvariant="normal">f</mi></msub><mo mathvariant="normal">=</mo><mfrac><mrow><mstyle displaystyle="true"><munderover><mo mathvariant="normal">∑</mo><mrow><mi mathvariant="normal">i</mi><mo mathvariant="normal">=</mo><mn mathvariant="normal">0</mn></mrow><mi mathvariant="normal">n</mi></munderover><mi mathvariant="normal">ΔI</mi></mstyle><mfenced><mi mathvariant="normal">i</mi></mfenced></mrow><mi mathvariant="normal">n</mi></mfrac></math><img file="EP2244378A2_D0006.tif" /></maths>

0046The correction amount calculation unit 33 calculates the bias correction amount ΔV_g based on the smoothed difference ΔI_f in much the same way that it calculates the bias correction amount ΔV_g based on the difference ΔI in the configuration of <figref idref="f0007">Figure 8A</figref>. The adder 34 corrects the bias voltage V_g(t) by adding the bias correction amount ΔV_g to the bias voltage V_g(t-1) determined at the immediately preceding determination timing (t-1).

0047According to the configuration example of <figref idref="f0007">Figure 8B</figref>, the speed with which the bias voltage V_g(t) responds to the change of the difference ΔI can be adjusted by adjusting the degree of the smoothing to be applied by the smoothing unit 35. For example, when calculating the bias correction amount ΔV_g based on the moving average value of the difference ΔI as in the above equation (6), the time constant with which the bias voltage V_g(t) responds to the change of the difference ΔI can be adjusted by adjusting the integration period Ts and the averaging interval n.

0048<figref idref="f0009">Figure 10</figref> is an explanatory diagram illustrating a bias adjusting method according to the present disclosure. In an alternative embodiment, the following operations AA to AE may be implemented as steps. In operation AA, the current detection unit 14 detects the load current I_det that flows from the power supply line into the load 2 under the control of the amplifying unit 13. Rather than an instantaneous value of the load current I_det, the current detection unit 14 may output its average value as the detection result.

0049In operation AB, the load current estimating unit 30 calculates the estimated value I_cal of the load current I_det based on the voltage level of the input signal.

0050In operation AC, the difference calculation unit 31 calculates the difference ΔI by subtracting the detected current I_det from the estimated value I_cal in accordance with the earlier given equation (3) or (4).

0051In operation AD, the correction amount calculation unit 33 calculates the bias correction amount ΔV_g based on the difference ΔI in accordance with the earlier given equation (5). Alternatively, the correction amount calculation unit 33 may calculate the bias correction amount ΔV_g based on the smoothed difference ΔIf output from the smoothing unit 35.

0052In operation AE, the adder 34 corrects the bias voltage V_g(t) by adding the bias correction amount ΔV_g to the bias voltage V_g(t-1) determined at the immediately preceding determination timing (t-1).

0053The bias voltage V_g(t) is then fed to the adder 11 where it is superimposed as the gate bias voltage of the FET 20 onto the input signal.. The input signal with the bias voltage V_g(t) superimposed thereon is input directly to the amplifying unit 13 without passing through the DC component removing capacitor; in this way, the bias voltage V_g(t) is adjusted so that the actual load current value I_det becomes equal to the load current estimated value I_cal calculated from the input signal waveform.

0054In this condition, it can be considered that the actual measured value I_det is identical to the load current estimated value I_cal predicted based on the input signal waveform. That is, in this condition, it is considered that the input signal waveform in the first section T1 is correctly reproduced in the output signal waveform, and that no excessive current is flowing. Accordingly, by adjusting the bias in accordance with the above method, the amplifying unit 13 is biased with the correct bias voltage V_g(t).

0055In the above configuration example, the amplifying unit 13 includes a source grounding circuit for the FET 20 which is used as the amplifying device. Alternatively, the amplifying unit 13 may include a drain grounding circuit for the FET 20. <figref idref="f0009">Figure 11</figref> is an explanatory diagram illustrating a second configuration example of the amplifying unit 13. Reference numeral 20 indicates an n-channel FET, C2 and C3 indicate capacitors, and L2 indicates an inductor.

0056The output signal from the DAC 12 is applied to the gate terminal of the FET 20, and the source terminal of the FET 20 is coupled via the current detection unit 14 to a power supply line that supplies voltage V_d. This power supply line is grounded via the capacitor C2. The drain terminal of the FET 20 is grounded via the inductor L2, and the output signal from the drain terminal is supplied to the load 2 via the DC component removing capacitor C3.

0057The above description has been given by taking as an example the amplifying circuit that uses an FET as the amplifying device. It will, however, be appreciated that the device and method disclosed herein can be applied extensively to any class B amplifying circuit.

0058Therefore, the scope of the device and method disclosed herein is not limited to amplifying circuits that use FETs. The scope of the device and method disclosed herein includes any class B amplifying circuit whose bias is adjusted in accordance with the above configuration and method. For example, a bipolar transistor may be used as the amplifying device.

0059According to the present embodiment, since the bias voltage is correctly adjusted, the reproducibility of the waveform produced by amplifying the input signal having the characteristic previously described with reference to <figref idref="f0002">Figure 2</figref> improves. Furthermore, according to the present embodiment, since the bias voltage is correctly adjusted so that no excessive drain current flows, the power utilization efficiency of the amplifying circuit improves.

0060In the present embodiment, the bias determining unit 16 determines the bias voltage V_g(t) in a manner relatively unaffected by the kind, magnitude, and shape of the input waveform. That is, since the estimated value I_cal and the measured value I_det both change simultaneously and in a similar manner with the input signal, the bias voltage V_g(t) calculated based on their difference (estimated value I_cal - measured value I_det) is relatively unaffected by the behavior of the input waveform.

0061Accordingly, the method of the embodiment can be used regardless of the shape of the input signal waveform such as the density of the input signal waveform (the change with time of the duty ratio which is the ratio between the first section T1 and the second section T2). Further, the method of the embodiment can be used regardless of the shape of the input signal waveform such as the presence or absence of a flat portion where the input signal value is maintained at its lower limit value V_L. Furthermore, since there is no need for the bias determining unit 16 to respond so as to follow the change of the input signal waveform, the bias determining unit 16 can be implemented without using a high-speed circuit.

0062As described above, the bias voltage V_g(t) is relatively unaffected by the behavior of the input waveform. However, in such cases as when the density of the input signal waveform changes, that is, when the duty ratio, i.e., the ratio between the first section T1 and the second section T2, changes with time, the load current changes between a period where the duty ratio is large and a period where the duty ratio is small. As a result, the difference ΔI can change between a large-outy-ratio period and a small-duty-ratio period. The difference ΔI can also change due to such factors as changes in temperature. By providing the smoothing unit 35, the speed with which the bias voltage V_g(t) responds to the change of the difference ΔI can be adjusted, thus reducing the perturbations of the bias voltage V_g(t) caused by the change with time of the duty ratio. For example, by adjusting the integration period Ts and the averaging interval n, as earlier described, the time constant with which the bias voltage V_g(t) responds to the change of the difference ΔI can be adjusted.

0063<figref idref="f0010">Figure 12</figref> is an explanatory diagram illustrating the waveform of a second example of the input signal. The input signal waveform alternates repeatedly between a first section T1 where there is a waveform to be amplified and a second section T2 where there is not. In the first section T1, the signal value varies within a range limited by an upper limit value V_U. In the input signal example illustrated here, the waveform has a shape similar to that of a half-wave and, during the second section T2, the signal remains unchanged with its signal value maintained substantially at the upper limit value V_U.

0064The amplifying circuit 1 depicted in <figref idref="f0004">Figure 4</figref> may be used to amplify the input signal illustrated in <figref idref="f0010">Figure 12</figref>. In this case, the load current estimating unit 30 calculates the average input voltage S_p by dividing an integrated value, calculated by integrating over each integration period T_s the difference (V_in - V_U) between the input voltage V_in and the upper limit value V_U, by the integration period T_s.

0065To amplify the waveform in the first section T1 illustrated in <figref idref="f0010">Figure 12</figref>, the amplifying unit 13 is configured as illustrated in <figref idref="f0011">Figure 13</figref>. Reference numeral 21 indicates a p-channel FET, R1 indicates a resistor, C1, C2, and C3 indicate capacitors, and L1 indicates an inductor. The amplifying unit 13 includes a source grounding circuit for the FET 21 which is used as the amplifying device. The output signal from the DAC 12 is applied to the gate terminal of the FET 21, and the drain terminal of the FET 21 is coupled via the inductor L1 and the current detection unit 14 to a power supply line that supplies a voltage of negative polarity. This power supply line is grounded via the capacitor C2.

0066The drain and gate terminals of the FET 21 is connected together by a feedback line having a series connection of the resistor R1 and the capacitor C1. The voltage gain of the FET 21 is controlled to the predetermined value A through this feedback line. The FET 21 amplifies the output signal of the DAC 12 by the predetermined voltage gain A, and supplies the resulting amplified signal to the load 20 via the DC component removing capacitor C3.

0067<figref idref="f0011">Figure 14</figref> is an explanatory diagram illustrating a configuration example of an AC signal amplifying circuit 100 according to the present disclosure. The AC signal amplifying circuit 100 is a circuit for amplifying an AC input signal which is an AC signal in the microwave region. Reference numeral 1 indicates the amplifying circuit described with reference to <figref idref="f0004">Figure 4</figref>, 40 indicates a high-power amplifier (HPA), 41 indicates an envelope signal generating unit, 42 indicates a waveform inverting unit, and L3 indicates an inductor. When the amplifying unit 13 in the amplifying circuit 1 is constructed as illustrated in <figref idref="f0009">Figure 11</figref>, the waveform inverting unit 42 need not be provided.

0068The amplifying circuit 1, the HPA 40, the envelope signal generating unit 41, the waveform inverting unit 42, and the inductor L3 together constitute the AC signal amplifying circuit 100. The HPA 40 is an amplifying device for amplifying the AC input signal in the microwave region. The envelope signal generating unit 41 generates an envelope signal that has an envelope waveform corresponding to the AC input signal supplied to the HPA 40. The envelope signal generating unit 41 supplies the generated envelope signal to the amplifying circuit 1 described with reference to <figref idref="f0004">Figure 4</figref>. The envelope signal is, for example, a signal in the VHF band.

0069The amplifying circuit 1 amplifies the envelope signal and supplies the amplified signal to the waveform inverting unit 42. The waveform inverting unit 42 outputs a relatively small signal for a relatively large input and a relatively large signal for a relatively small input, thus generating an inverted signal by inverting the waveform of the amplified envelope signal with respect to the magnitude of the signal intensity. The inverted signal output from the waveform inverting unit 42 is added to the supply voltage V_dd that is being supplied from the power supply line via the inductor L3. The supply voltage with the inverted signal added thereto is supplied as power to the HPA 40.

0070With the above configuration, the HPA 40 is supplied with a large supply voltage during a period when the amplitude of the envelope of the AC input signal is large and with a small supply voltage during a period when the amplitude of the envelope of the AC input signal is small; this serves to reduce the power consumption of the HPA 40.

0071All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiment(s) of the present invention have been described in detail, it should be understood that the various change, substitutions, and alterations can be made hereto without departing from the spirit and scope of the invention.