Pulse generator having an efficient fractional voltage converter and method of use

CROSS-REFERENCE TO RELATED APPLICATIONS

0001Priority is hereby claimed to United States provisional patent application serial number <patcit id="pcit0001" dnum="US60648556B"><text>60/648,556</text></patcit> entitled "Efficient Fractional Voltage Converter," filed January 31, 2005, the disclosure of which is hereby incorporated herein by reference. The present application is related to co-pending and commonly assigned United States patent applications serial number <patcit id="pcit0002" dnum="US11105191B"><text>11/105,191</text></patcit> entitled "Systems and Methods for Precharging Circuitry for Pulse Generation," filed April 12, 2005, <patcit id="pcit0003" dnum="US11122540B"><text>11/122,540</text></patcit> entitled "Multi-Programmable Trial Stimulator," filed May 5, 2005, and <patcit id="pcit0004" dnum="US11105332B"><text>11/105,332</text></patcit> entitled "Fractional Voltage Converter," filed April 12, 2005, the disclosures of which are hereby incorporated herein by reference.

TECHNICAL FIELD

0002This application relates generally to power supply circuitry and, more particularly, to an efficient voltage multiplier.

BACKGROUND

0003A variety of devices employ power supply circuitry in order to provide voltages and/or currents used in operating the device itself or used in the operation of the device. Such power supply circuitry is often utilized to alter power supplied from a power source, such as line power or a battery, to meet the demands or requirements of the device. For example, power supply circuitry may be utilized to step-up/step-down current, step-up/step-down voltage, provide a direct current (DC) output from an alternating current (AC) input, and/or provide an AC output from a DC input, Circuitry providing the foregoing may be relatively complex, perhaps including a number of active components, and often suffers from inefficiencies, e.g., an appreciable amount of the power supply energy is consumed in altering the power supplied from the power source. However, complex and inefficient power supply circuits are undesirable in a number of situations, such as in certain portable devices using a battery as a power supply.

0004An implantable neurostimulator, such as the GENBSIS™ Neurostimulation System available from Advanced Neuromodulation Systems, Plano Texas, is one example of a portable device which may implement power supply circuitry as described above in altering one or more aspects of a battery power supply output for use in operating the device or in the operation of the device. Because implanting and explanting such a neurostunulator causes appreciable trauma to the patient, it is typically desired that the neurostimulator power supply be small and relatively long lived and that the circuitry (including power supply circuitry) of the neurostimulator be small and reliable. Even where a rechargeable battery is used as a power supply, it is typically desired to provide operation of the neurostimulator in such a way as to result in a relatively long battery life between recharge cycles so as to minimize restrictions on the patient's mobility. Battery voltage associated with a battery such as may be implemented in a neurostimulator can be 2.5 volts, for example, or on the order of 4.2 volts, for lithium ion, but in any case is typically relatively low due to the size constraints of the device.

0005In providing neurostimulation, it may be desirable to provide up to 30 milliamp pulses, for example, to an area of the patient's anatomy, such as near the spinal cord. The patient equivalent resistance in the area of the delivery of the therapeutic current can often range from 200 ohms to 2 kilohms. Knowing the current and load, the voltage needed to effect the desired therapy can be calculated in the above example as being on the order of 15 volts to provide the desired current to the patient. However, as described above, the battery voltage may be much less than 15 volts.

0006Accordingly, the above mentioned neurostimulator may implement power supply circuitry which provides voltage up-conversion to facilitate delivery of therapy to the patient using the available power supply. There are many ways to implement voltage up-conversion. However, in a battery powered device, in particular, it is generally desirable to provide the voltage up-conversion in the most efficient way possible.

0007In the past a number of power supply circuit configurations have been implemented to provide voltage up-conversion. In particular, inductive voltage up-converters (voltage up-converters also being referred to herein as voltage multipliers) and capacitive voltage up-converters.

0008Inductive voltage up-converters or voltage multipliers require the use of a coil for voltage conversion, which in turn necessitates the use of alternating current. However, batteries such as those used in the above mentioned neurostimulators provide direct current. Accordingly, the use of an inductive voltage multiplier with a battery power supply generally involves the use of complicated and inefficient switching regulator circuitry to convert the direct current from the battery to alternating current for voltage up-conversion. Moreover, additional rectifier circuitry is typically implemented to convert the up-converted alternating current back to direct current. Electromagnetic noise is often introduced by inductor-based switching regulator circuitry, such as may interfere with data communications, thereby requiring additional shielding and/or circuitry to prevent such electronmagnetic noise from interfering with operation of the device. Accordingly, inductive voltage up-converters are generally undesirable for use in small battery powered devices, such as implantable neurostimulators.

0009Capacitive voltage up-convetters or voltage multipliers have generally been used to provide output voltages in integer multiples of the battery voltage (e.g., 2 times the battery voltage, 3 times the battery voltage, etcatera). However, such integer multiples of the battery voltage often are not the most efficient voltages. For example, assuming a battery voltage of 4 volts and that a desired current for therapeutic stimulation requires 9 volts, a typical prior art capacitive voltage multiplier must provide 12 volts for the needed 9 volt pulse because its design provides selection between 4 volts (1 times the 4 volt battery voltage), 8 volts (2 times the 4 volt battery voltage), 12 volts (3 times the 4 volt battery voltage), etcetera.

0010The power consumed from the battery is based on the multiplicative factor created from the battery. In the foregoing example, if 10 milliamps was delivered to the patient, 30 milliamps was pulled from the battery because of the 3 times multiplicative factor used in the voltage up-conversion. Accordingly, if the voltage provided by the power supply circuitry could be controlled to more closely match that needed for the desired level of stimulation, the multiplicative factor, and thus the power pulled from the battery, could be reduced.

0011Further compounding the inefficiencies associated with capacitive voltage multipliers of the prior art is their operation in creating and storing a voltage multiple. In operation, a capacitive voltage multiplier will create a particular multiply voltage and store that voltage on a storage capacitor for output by the power supply circuit. When it is desired to change the output voltage of the power supply circuit, the previously stored multiply voltage stored by the storage capacitor must be discharged in order to change the voltage to a new value. The discharge of the previously stored multiply voltage is a waste of energy which, if done often, can amount to an appreciable drain on the power supply. For example, where two sequential stimulation pulses of a neurostimulator require different voltages, prior art capacitive voltage multipliers would require discharging of capacitors charged for providing the first voltage for recharging of the capacitors for providing the second voltage, thereby wasting energy.

0012Accordingly, a need exists in the art for an efficient voltage multiplier, such as may be used in relatively small, battery powered devices.

SUMMARY

0013The present application is directed to systems and methods which provide voltage conversion in increments less than integer multiples (i.e., fractions) of a power supply (e.g., battery) voltage. Some representative embodiments provide a plurality of different power supply voltage multipliers, including fractional multipliers. Additionally or alternatively, some representative embodiments provide a plurality of different power supply voltage dividers, including fractional dividers.

0014A representative embodiment provides power supply voltage multipliers and/or dividers in a binary ladder distribution to provide a desired number of output voltage steps using a circuit design which may readily be implemented in an integrated circuit or integrated circuits. For example, a capacitive voltage multiplier provided according to a representative embodiment may comprise a voltage doubler generating twice the battery voltage, the battery itself generating the battery voltage, a voltage halfer generating half of the battery voltage, and a voltage quarterer generating a quarter of the battery voltage. Circuitry of the foregoing voltage multiplier preferably operates to combine the different voltages to provide a range of output voltages in one-quarter battery voltage (¼ V_B), or other power source voltage steps. By using these different sources in various combinations and/or by "stacking" these different sources in various ways, the voltage multiplier circuit may be used to provide desired voltages. For example, the output voltage of such a voltage multiplier may range from V_B to 3 ¾ V_B, in one-quarter battery voltage steps. Accordingly, representative embodiments may be controlled to provide an output voltage more near that desired than would otherwise be available using a conventional capacitive voltage conversion circuit configuration.

0015In order to minimize the number of components used in a voltage converter of a representative embodiment, a capacitive voltage converter circuit uses one or more storage capacitors in place of pump capacitors in a voltage generation cycle. In past capacitive voltage multiplier circuits, pump capacitors have been used to generate a voltage from the power supply and storage capacitors have been used in storing the generated voltage until output, and the use of these capacitors as pump or storage capacitors has been mutually exclusive. However, representative embodiments use some of the storage capacitors in place of pump capacitors in order to reduce the number of components used in providing a conversion circuit Moreover, representative embodiments utilize pump and storage capacitors which are not matched (e.g., not of the same capacitance) when generating voltages. According to a representative embodiment, storage capacitors ate relatively large whereas pump capacitors are relatively small, although a combination of storage and pump capacitors is used in generating a particular voltage multiple or fraction of a voltage.

0016Representative embodiments do not operate to generate an output voltage until the time that voltage that is needed. For example, by stacking the supply capacitors (e.g., pump capacitors and/or storage capacitors) to form the desired output voltage as that voltage is being requested, representative embodiments avoid a need to discharge a particular source capacitor in order to change the output voltage. Instead, representative embodiments operate to stack the supply capacitors as needed to provide a desired output voltage. Accordingly, there is no energy wasted in the formation of the desired voltage according to some embodiments.

0017As can be appreciated from the foregoing, some representative embodiments provide an efficient voltage multiplier, such as may be used in relatively small, battery powered devices.

0018In some embodiments, a pulse generator, for delivering electrical stimulation to a patient, comprises a battery operable to power the pulse generator; circuitry for generating and delivering electrical pulses to tissue of the patient according to a plurality of controllable output levels; and a voltage conversion module operable to convert from a voltage level from the battery to a variable converted voltage level for provision to the circuitry for generating and delivering, wherein the voltage conversion module comprises a plurality of capacitive voltage multipliers including at least one fractional capacitive voltage multiplier, and the voltage conversion module including a voltage combining element that combines the voltages output from the plurality of capacitive voltage multipliers to produce the converted voltage level.

0019In some embodiments, the voltage conversion module comprises a logic element for receiving multiple control bits, the control bits identifying a desired voltage level for the converted voltage level. In some embodiments, the voltage conversion module comprises switching circuitry that is operable to controllably arrange a plurality of capacitors into a stacked circuit configuration to achieve a desired fractional voltage level.

0020In some embodiments, the pulse generator further comprises control circuitry for causing delivery of multiple pulses to tissue of the patient in succession, the control circuitry (i) causing the converted voltage level to equal a first voltage level before causing the circuitry for delivering to deliver a first electrical pulse at a first amplitude; and shortly thereafter (ii) causing the converted voltage level to equal a second voltage level before causing the circuitry for delivering to deliver a second electrical pulse at a second amplitude, wherein at least one storage capacitor in the plurality of capacitive voltage multipliers is not discharged between the first and second electrical pulses.

0021In some embodiments, a method of operating a pulse generator for delivering electrical stimulation to a patient, comprises powering the pulse generator using a battery; generating electrical pulses according to a plurality of controllable output levels; delivering the generated electrical pulses to tissue of the patient; and converting from a voltage level from the battery to a variable converted voltage level for use by the generating, wherein the converting includes (i) multiplying the voltage level from the battery by multiple capacitive multipliers including at least one fractional capacitive multiplier and (ii) combining voltages output from the multiple capacitive multipliers to produce the converted voltage level.

0022In one embodiment, a system for provides selectable voltage level output. The system comprises: a capacitive voltage converter accepting an input voltage level and providing a plurality of output voltage levels selectable in fractional increments of said input voltage level.

0023In some embodiments, a method for providing selectable voltage level output, said method comprises providing a control signal for selecting a desired output voltage level from a plurality of output voltage levels available in fractional increments of an input voltage level; and switching, under control of said control signal, a plurality of capacitors in a stacked circuit configuration for outputting said desired output voltage level.

0024In some embodiments, a system comprises a medical device for providing stimulation therapy to a patient, said medical device having a capacitive voltage converter providing a plurality of output voltage levels selectable in fractional increments of an supply voltage level. In some embodiments, the medical device comprises a neurostimulator or a tissue stimulator.

0025In some embodiments, the fractional increments comprise ¼ increments of said input voltage level. In some embodiments, the capacitive voltage converter accepts input of a digital control signal for selection of a desired output voltage level of said plurality of output voltage levels. In some embodiments, the digital control signal comprises 4 bits operable to select said desired output voltage level from a range of said plurality of output voltage levels including ¼ times said input voltage level through 3 ¼ times said input voltage level. In some embodiments, the capacitive voltage converter comprises a plurality of capacitors, wherein at least one capacitor of said plurality of capacitors is used in a charge phase, a pump phase, and a source phase of said voltage converter.

0026In some embodiments, the capacitive voltage converter comprises switching circuitry disposed in at least one integrated circuit In some embodiments, the switching circuitry is operable to couple a plurality of capacitors in a stacked configuration for output of a desired output voltage level. In some embodiments, the switching circuitry comprises a plurality of controllable switches, wherein said plurality of controllable switches are partitioned in operation of said capacitive voltage converter to minimize a number of components of said capacitive voltage converter experiencing high voltage levels of said plurality of output voltage levels, In some embodiments, lower voltage ones of switches of said plurality of controllable switches are provided near a bottom of a stacked circuit configuration for outputting an output voltage level and higher voltage ones of said switches of said plurality of controllable switches are provided near a top of said stacked circuit configuration. In some embodiments, the plurality of controllable switches comprise a plurality of MOSFET switching devices of different sizes. In some embodiments, the switching circuitry comprises a MEMS device.

0027In some embodiments, the system comprises a high power digital to analog converter that provides voltage level output above said input voltage level. In some embodiments , the input voltage level is provided by a battery based power supply system. In some embodiments, a battery of said battery based power supply system is rechargeable.

0028In some embodiments, a capacitive voltage conversion system comprises output voltage level control circuitry; and a plurality of switchable capacitor circuits operating under control of said control circuitry to stack a plurality of capacitors to provide a desired output voltage level, said stack being controlled by said control circuitry to always dispose lower voltage components of said system more near a bottom of said stack than higher voltage components of said system.

0029The foregoing has outlined rather broadly the features and technical advantages of some embodiments in order that the detailed description that follows may be better understood. Additional features and advantages will be described hereinafter. It should be appreciated that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes. It should also be realized that such equivalent constructions do not depart from the appended claims. The novel features with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the appended claims.

BRIEF DESCRIPTION OF THE DRAWING

0030For a more complete understanding of the present application, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:

0031<figref idref="f0001">FIGURE 1</figref> shows a high level block diagram of a voltage multiplier configuration of a representative embodiment;

0032<figref idref="f0001">FIGURES 2A, 3A, and 4A</figref> show interconnection of pump and storage capacitors in a charge phase according to a representative embodiment;

0033<figref idref="f0001">FIGURES 2B, 3B, and 4B</figref> show interconnection of pump and storage capacitors in a pump phase according to a representative embodiment;

0034<figref idref="f0001">FIGURE 4C</figref> shows one possible configuration of capacitors coupled in series to a power supply voltage (V_B) to provide ¼ V_B; and

0035<figref idref="f0002">FIGURE 5</figref> shows detail with respect to the voltage multiplier circuitry of <figref idref="f0001">FIGURE 1</figref> according to a representative embodiment.

DETAILED DESCRIPTION

0036In order to aid the reader in understanding the concepts of some embodiments, a representative embodiment is described herein with reference to a neurostimulation system. Such a system generally has several design constraints associated therewith, such as limited battery power, small size, high reliability, and efficient operation, particularly relevant to advantages available from voltage converters implementing concepts. However, it should be appreciated that voltage converters provided according to some embodiments may be used in any number host systems or situations. Exemplary embodiments are described herein with reference to providing voltage multiplication. However, one of ordinary skill in the art will readily appreciate that concepts disclosed in relation to voltage multipliers are applicable to voltage dividers as well.

0037Directing attention to <figref idref="f0001">FIGURE 1</figref>, a high level block diagram of a voltage multiplier configuration of a representative embodiment is shown as voltage multiplier 100. Voltage multiplier 100 of the illustrated embodiment includes capacitive voltage multiplier (CVM) integrated circuit 110, pump capacitors CP1, CP2, and CP3, and storage capacitors CS1, CS2, and CS3. CVM 110 includes signal inputs V_REG, CLOCK, V_B, D0:3 and OE, and output V_TARG.

0038V_REG of the illustrated embodiment provides a regulated voltage input for use by circuits (e.g., digital control circuits) of CVM 110 in providing voltage multiplication. V_REG is typically at a logic level (e.g., 2.2 volts) which is lower than the power supply voltage (e.g., V_B). CLOCK is a system clock signal used for synchronizing operation of aspects of CVM 110 with operation of aspects of a host system, such as for digital communication, voltage output timing, etcetera. V_B provides a power supply voltage level input for use in voltage multiplication by CVM 110. For example, V_B may provide unregulated battery voltage input, such as 4.1 volts where a lithium-ion battery is used. D0:3 provides a digital input signal. In the illustrated embodiment, D0:3 provides a 4 bit digital signal which is used in selecting a desired output voltage level. OE provides an output enable signal to selectively enable the output voltage V_TARG. Accordingly, a signal provided at OE may comprise a binary logic level signal. V_TARG provides a target output voltage level as selected under control of D0:3 and as enabled under control of OE. Further detail with respect to the circuitry of CVM 110 according to one representative embodiment is provided below with reference to <figref idref="f0002">FIGURE 5</figref>.

0039Pump capacitors CP1, CP2, and CP3 of the illustrated embodiment are utilized in a voltage generation cycle. Because of the use of a partitioned circuit configuration of CVM 100 of a representative embodiment, as will be better understood from the discussion which follows, and the relatively low voltages experienced by capacitors CP1, CP2, and CP3, these pump capacitors may be relatively small, such as on the order of 0.5 µFarads. One or more of storage capacitors CS1, CS2, and CS3 may be stacked in providing a desired output voltage (V_TARG) such that a relatively high voltage is experienced thereby. Moreover, in order to sustain a relatively constant (i.e., flat) output voltage level during a voltage output cycle, storage capacitors CS 1, CS2, and CS3 may be larger than the pump capacitors, such as on the order of 100 µFarads. Accordingly, various capacitors utilized in generating a particular voltage multiple or voltage fraction need not be matched. For example, according to a representative embodiment where pump capacitors are used in combination with storage capacitors to generate a voltage multiple or voltage fraction, are not matched.

0040It should be appreciated that through controlled stacking of the various capacitors in providing a desired output voltage, the maximum voltage levels experienced by particular capacitors (and other components) may be minimized. Therefore, one or more of the capacitors or other circuitry may be sized differently with respect to one another according to some embodiments. Accordingly, various ones of the pump capacitors may be sized differently with respect to other pump capacitors and/or various ones of the storage capacitors may be sized differently with respect to other storage capacitors.

0041In operation according to a representative embodiment, CVM 110 provides selectable voltage output at V_TARG from 0 V_B through 3 ¾ V_B in ¼ V_B steps. For example, a logic low input at OE may be used to turn the voltage output at V_TARG off (0 V_B), such as during a voltage generation cycle. A logic high input at OE in combination with a particular bit combination logic input at D0:3 may be used to turn the voltage output at V_TARG on and select a particular voltage level from ¼ V_B through 3 ¾ V_B. Other fractional voltages may be provided through the use of combinations of capacitors different than those of the exemplary embodiment

0042Generation of voltages using a voltage conversion circuit may include a plurality of phases, wherein during one or more such phases an output of the voltage conversion circuit may be disabled. For example, a charge phase may be used to charge the pump capacitors with current from the power supply and a pump phase may be used to pump the current into storage capacitors (the combination of these phases being referred to as a generation phase). A source phase may be used to output a desired voltage using an appropriate configuration of pump capacitors and/or storage capacitors. <figref idref="f0001">FIGURES 2A-4B</figref> illustrate interconnection of pump and storage capacitors in a charge phase (<figref idref="f0001">FIGURES 2A, 3A, and 4A</figref>) and a pump phase (<figref idref="f0001">FIGURES 2B, 3B, and 4B</figref>) according to a representative embodiment.

0043<figref idref="f0001">FIGURES 2A and 2B</figref> illustrate a charge phase and pump phase, respectively, of a 2 V_B source according to a representative embodiment. In the charge phase of <figref idref="f0001">FIGURE 2A</figref>, capacitor CS2 is coupled between the power supply voltage (V_B) and ground in order to be charged to V_B. Thereafter, during the pump phase of <figref idref="f0001">FIGURE 2B</figref>, the lead of capacitor CS2 formerly coupled to ground is coupled to V_B to be pumped to twice the power supply voltage (2 V_B). This provides the 2 V_B source of a voltage binary ladder of a representative embodiment. It should be appreciated that the above described charge and pump phases utilize a same capacitor, here CS2, thereby avoiding the use of separate pump and storage capacitors in providing a 2 V_B source. Capacitor CS2 may be coupled to output V_TARG of CVM integrated circuit 110, perhaps in a "stack" including other capacitors, to provide a desired voltage level output during a source phase.

0044<figref idref="f0001">FIGURES 3A and 3B</figref> illustrate a charge phase and pump phase, respectively, of a ¼ V_B, source according to a representative embodiment. In the charge phase of <figref idref="f0001">FIGURE 3A</figref>, capacitors CP1 and CP2 are coupled in series between the power supply voltage (V_B) and ground in order to charge each capacitor to ½ V_B. In the illustration of <figref idref="f0001">FIGURE 3A</figref>, capacitor CS1 is not utilized in charging the capacitors CP1 and CP2 and, therefore, is illustrated as disconnected therefrom. During the pump phase of <figref idref="f0001">FIGURE 3B</figref>, the lead of capacitor CP1 formerly coupled to a lead of capacitor CP2 is coupled to ground and the capacitors are coupled in parallel with capacitor CS1 to pump capacitor CS1 to ½ the power supply voltage (½ V_B). Capacitor CS1 provides the ½ V_B source of a voltage binary ladder of a representative embodiment. Capacitor CS2 may be decoupled from capacitors CP1 and CP2 and coupled to output V_TARG of CVM integrated circuit 110, perhaps in a "stack" including other capacitors, to provide a desired voltage level output during a source phase.

0045<figref idref="f0001">FIGURES 4A and 4B</figref> illustrate a charge phase and pump phase, respectively, of a ¼ V_B source according to a representative embodiment. It should be appreciated that 4 capacitors coupled in series to the power supply voltage (V_B) may be utilized in providing % V_B, as shown in <figref idref="f0001">FIGURE 4C</figref>. However, it was realized in the development of some embodiments that a ½ V_B charge circuit (the lower half of the circuit shown in <figref idref="f0001">FIGURE 4C</figref>) is provided in the circuitry of <figref idref="f0001">FIGURES 3A and 3B</figref>. Moreover, experimentation has revealed that, when capacitor CS1 is coupled to the ½ V_B point in the charge circuit of <figref idref="f0001">FIGURE 3A</figref>, an equilibrium is reached, such that this capacitor may be relied upon to provide current in both the charge and pump phases. As such, in the charge phase of <figref idref="f0001">FIGURE 4A</figref>, capacitors CP3 and CS3 are coupled in series between ½ the power supply voltage (½ V_B), as provided by capacitor CS1, and ground in order to charge each capacitor to ¼ V_B. Thereafter, during the pump phase of <figref idref="f0001">FIGURE 4B</figref>, the lead of capacitor CP3 formerly coupled to a lead of capacitor CS3 is coupled to ground and the capacitors are coupled in parallel to pump capacitor CS3 to ¼ the power supply voltage (¼ V_B). This provides the ¼ V_B source of a voltage binary ladder of a representative embodiment. It should be appreciated that the above described charge and pump phases reduce the number of capacitors utilized in providing a ¼ V_B source, as compared to the circuit configuration of <figref idref="f0001">FIGURE 4C</figref>. Capacitor CS3 may be decoupled from capacitor CP3 and coupled to output V_TARG, of CVM integrated circuit 110, perhaps in a "stack"' including other capacitors, to provide a desired voltage level output during a source phase.

0046The forgoing charge and pump phases provide a ¼ V_B, a ½ V_B, and a 2 V_B source of a voltage binary ladder. The power supply voltage itself may be utilized in providing a V_B source. These 4 sources may be used in various combinations and/or stacked in various ways for a source phase to provide a desired output voltage (V_TARG) in the range from ¼ V_B to 3 ¾ V_B, in one-quarter V_B steps. Stacking of the sources to provide an output voltage may be provided upon demand, such that the output voltage is generated at the time that voltage is needed. Such an on-demand output voltage generation technique avoids the situation in which a previously charged storage capacitor must be discharged in order to accommodate a change in desired output voltage. On-demand output voltage generation techniques of some embodiments are particularly efficient in delivery of pulses of asymmetric shapes and/or having different amplitudes. For example, where CVM integrated circuit 110 is utilized for voltage output in a neurostimulation device implementing a multi-stimulation set program (e.g., interleaving various stimulation voltages or amplitudes in successive stimulation pulses), the on-demand output voltage generation technique of come embodiments will provide efficient operation (e.g., extending battery life). The above reference patent application entitled "Multi-Programmable Trial Stimulator" provides detail with respect to a neurostimulation device implementing a multiple stimulation set as may benefit from implementation of one of the representative embodiments.

0047Controllable switching circuitry is preferably utilized in coupling capacitors in the various circuit configurations of <figref idref="f0001">FIGURES 2A-4B</figref> as well as to select sources and provide stacking for output of a desired voltage level. Such switching circuitry preferably provides a "break-before-make" connection so as to avoid overlapping connection of components between various circuit configurations (e.g., between a charge phase circuit configuration and a pump phase circuit configuration). The foregoing switching circuitry may be comprised of solid state circuitry such as bipolar devices, metal-oxide-silicon field effect transistors (MOSFETs), micro electromechanical systems (MEMS) devices (e.g., thermally actuated MEMS, electrostatically actuated MEMS, electromagnetically actuated MEMS), etcetera.

0048Directing attention to <figref idref="f0002">FIGURE 5</figref>, detail with respect to controllable switching circuitry as may be provided in an integrated circuit of CVM 110 according to a representative embodiment is shown. It should be appreciated that the circuitry of <figref idref="f0002">FIGURE 5</figref> may be provided in one or more integrated circuits, according to some embodiments. In the embodiment of <figref idref="f0002">FIGURE 5</figref>, switches SCP1-SCP6 provide switching between charge and pump circuit configurations to provide connection of the capacitors as shown in <figref idref="f0001">FIGURES 2A-4B</figref>. Control of switches SCP1-SCP6 is provided such that the charge phase is of sufficient duration to charge the capacitors used as pump capacitors and the pump phase is of sufficient duration for the capacitors used as pump capacitors to pump the capacitors used as source capacitors. According to some embodiments, the charge and pump phases are completed within a voltage generation cycle of the voltage multiplier. Thereafter, a source cycle of the voltage multiplier is invoked to provide output of a desired voltage. The source cycle is preferably of sufficiently long duration to provide desired energy output (e.g., provide a neurostimulator stimulation pulse of a desired length) and of sufficiently short duration to avoid draining the source capacitors (e.g., resulting in an unacceptable voltage droop). The foregoing timing may be established using a system clock signal, such as that provided at the CLOCK input of CVM 110 shown in <figref idref="f0001">FIGURE 1</figref>.

0049In the representative embodiment illustrated in <figref idref="f0002">FIGURE 5</figref>, control signals are provided to voltage selection circuitry 510, such as may be provided at the D0:3 input of CVM 110, in order to select a desired output voltage (V_TARG). Specifically, voltage selection circuitry 510 includes switches SW1-SW4 which may be controlled to provide selection of V_TARG in a range from ¼ V_B to 3 ¼ V_B. Representative information of control of switches SW1-SW4 in providing selection of output voltage levels according to a representative embodiment is provided in the following table. <tables id="tabl0001" num="0001"><table frame="all"><tgroup cols="3"><colspec colnum="1" colname="col1" colwidth="32mm" /><colspec colnum="2" colname="col2" colwidth="36mm" /><colspec colnum="3" colname="col3" colwidth="29mm" /><thead><row><entry align="center" valign="top">Control Signal D0:3 (D, C, B, A)</entry><entry align="center" valign="top">Output Voltage V_TARG</entry><entry align="center" valign="top">Switch On</entry></row></thead><tbody><row><entry>0000</entry><entry>Off</entry><entry>None</entry></row><row><entry>0001</entry><entry>¼ V_B</entry><entry>4-A, 1-0</entry></row><row><entry>0010</entry><entry>½ V_B</entry><entry>4-B, 2-0</entry></row><row><entry>0011</entry><entry>¾ V_B</entry><entry>4-B, 1-0, 2-A</entry></row><row><entry>0100</entry><entry>V_B</entry><entry>4-C</entry></row><row><entry>0101</entry><entry>1 ¼ V_B</entry><entry>4-A, 1-C</entry></row><row><entry>0110</entry><entry>1 ½ V_B</entry><entry>4-B, 2-C</entry></row><row><entry>0111</entry><entry>1 ¾ V_B</entry><entry>4-B, 1-C, 2-A</entry></row><row><entry>1000</entry><entry>2 V_B</entry><entry>4-D</entry></row><row><entry>1001</entry><entry>2 ¼ V_B</entry><entry>4-D, 3-A</entry></row><row><entry>1010</entry><entry>2 ½ V_B</entry><entry>4-D, 3-B</entry></row><row><entry>1011</entry><entry>2 ¾ V_B</entry><entry>4-D, 2-A, 3-B</entry></row><row><entry>1100</entry><entry>3 V_B</entry><entry>4-D, 3-C</entry></row><row><entry>1101</entry><entry>3 ¼ V_B</entry><entry>4-D, 1-C, 3-A</entry></row><row><entry>1110</entry><entry>3 ½ V_B</entry><entry>4-D, 2-C, 3-B</entry></row><row><entry>1111</entry><entry>3 ¼ V_B</entry><entry>4-D, 1-C, 2-A, 3-B</entry></row></tbody></tgroup></table></tables>

0050It should be appreciated that the foregoing circuitry facilitates selection of output voltage levels with a resolution heretofore unavailable in a capacitive voltage multiplier design well suited for use in applications such as implantable neurostimulator devices. For example, in operation of the foregoing, the output voltage level may be chosen as 1 ¼ V_B, 1 ½ V_B, or 1 ¾ V_B, which ever more closely matches a desired output voltage level. Where the power supply comprises a lithium-ion battery providing 4.1 volts (V_B), approximately 1 volt increments are provided between each of the above selections. The difference in power consumption associated with a voltage multiplier able to more closely match the desired output voltage level can be quite significant For example, the power savings associated with selection of 1 ¼ V_B by operation of a voltage multiplier (where 1 ¼ V_B provides an output voltage level at least as high as that desired) over selection of 2 V_B of a typical prior art is on the order of 37 ½% power savings. Accordingly, a battery may last as much as 37 ½ % longer in an implantable neurostimulator implementing a voltage multiplier. Likewise, recharge cycle time associated with a rechargeable battery device may be increased as much as 37 ½ %, by implementing a voltage multiplier. Accordingly, if such a device required recharging every 18 hours using a typical voltage multiplier, the device might be operated with a recharge every 24 hours by using a voltage multiplier.

0051Moreover, circuit configurations used according to some embodiments provide efficiencies with respect to power consumed by the voltage multiplier circuitry itself. For example, circuitry used in providing various levels of voltage multiplication are partitioned in the representative embodiment illustrated in <figref idref="f0002">FIGURE 5</figref> so as to reduce the maximum voltage levels experienced by particular components. In particular, the partitioning of some embodiments provides stacking of components in providing a desired output voltage level such that the majority of devices (e.g., switches and capacitors) do not experience high voltages (e.g., 3 V_B), although these devices are used in generating the highest voltages available from the voltage multiplier. Accordingly, many of the devices used in a voltage multiplier may be designed to handle lower voltages, and thus perhaps be smaller, introduce less resistance, etcetera, whereas only a few of the devices may be designed to handle the maximum voltage levels provided by the voltage multiplier. Such a configuration may be particularly useful in an integrated circuit configuration, such as that of CVM 110 shown in <figref idref="f0001">FIGURE 1</figref>, wherein MOSFET switches may be implemented. For example, the smaller a MOSFET switching device may be made, the less capacitance associated therewith, and the less power consumption associated with its operation.

0052Providing the foregoing switches as MOSFET switches or other transmission gates, and making gates as low voltage as possible, as discussed above, allows lower voltage control signals to operate these switches. Accordingly, the digital control signals provided at input D0:3 of CVM 110 of <figref idref="f0001">FIGURE 1</figref> may be utilized to drive a number of these switches directly. Level shifters may be implemented to drive switches associated with the higher voltage partitions of the voltage multiplier circuit according to some embodiments. However, it should be appreciated that the above described technique of partitioning the circuitry of the voltage multiplier minimizes the number of level shifters used in providing the optimum level control signals to the switches.

0053The foregoing voltage multiplier configuration provides a representative embodiment providing relatively fine output voltage level increments with a relatively small number of components. In particular, the switching circuitry may readily be implemented in an integrated circuit with a small number of external components (e.g., a minimum number of external capacitors). Moreover, the illustrated embodiment has provided a balance between providing fine enough control of output voltage level selection to maximize power efficiency while minimizing the area and external components, and thus balances between the size and power consumption of the circuitry and the resulting power efficiency.

0054Although the representative embodiments above have been described with reference to providing output voltage level selection in ¼ power supply voltage increments, the concepts of some embodiments are scalable and may be used in providing voltage multipliers providing different increments (e.g., 1/16, 1/8, 1/5, 1/3, etcetera) of a power supply voltage. Moreover, although the discussion above has made reference to a power supply voltage, some embodiments may be utilized with respect to any voltage available as an input to the voltage conversion circuit, including regulated, filtered, and level shifted voltages from any of a number of sources. Likewise, embodiments are not limited in application to battery power supplies, and may be used with respect to any number of sources, including line sources.

0055Some embodiments of fractional voltage conversion circuits have been described herein with respect to providing desired power supply voltage level output. However, the present concepts of voltage multiplication are not limited to use with respect to providing a power supply. For example, embodiments may be utilized to provide a high power digital to analog converter that provides voltage level output above a power supply voltage level.

0056Although some embodiments and advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the appended claims. Moreover, the scope of the appended claims is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.