Frequency synthesiser

0001The invention relates to digital phase-locked loop circuits for use as frequency synthesisers in, for example, ultra low power (ULP) pulse-based radio transceivers.

0002Down-conversion RF receiver architectures require frequency synthesizers in order to translate a received RF signal to a much lower frequency where channel filtering can be performed with a low-Q filter. Frequency synthesizers are also used to up-convert baseband information to an RF frequency for wireless communications. Synthesizers in RF transceivers must be able to provide a clean (i.e. low noise) frequency signal with very high absolute accuracy over an expected range of process voltage and temperature (PVT) variations, and are usually the most power-hungry blocks in a transceiver.

0003In impulse radio (IR) based transceivers, particularly in the context of low data rate ultra low power (ULP) radios, transmitted signals consist of a sequence of short duration pulses with a high RF centre frequency and a fixed pulse repetition frequency (PRF). Data can be encoded by changing either the phase, the amplitude, the frequency or the position of pulses realizing respectively the well-known modulation schemes of PSK (phase shift keying), OOK (on-off keying), FSK (frequency shift keying) or PPM (pulse-position modulation) [5]. A reduction in the energy used in receiving and in transmitting modes is mainly obtained by duty-cycling the system, i.e. by putting the system into a 'sleep mode' for a significant fraction of the time in use.

0004The circuits in a typical receiver signal path, such as a low-noise amplifier (LNA), mixer and IF amplifier, can be duty-cycled according to the PRF of the signal. Moreover, the frequency used to down convert the RF signal can be generated in burst mode and in synchronization with the incoming pulse by means of a digital controlled oscillator (DCO) operating in an open loop mode and periodically calibrated. At the transmitter side, a calibrated pulse generator is typically used, which avoids the use of a power-hungry oscillator, to up-convert the baseband information. At the receiver side, in order to achieve ultra low power operation a duty-cycled down-conversion architecture is combined with a burst mode and a periodically calibrated free-running DCO.

0005By duty-cycling all the transceiver blocks at the pulse level, i.e. by shutting down the complete radio, including the frequency generating system, between transmitted or received pulses, a highly energy-efficient system can be realized.

0006High frequency synthesizers are often the most power hungry blocks in Wireless Sensor Networks (WSN) [3]. They need to be accurate, and considerable effort has been devoted to the realization of low-power PLLs with sufficient accuracy.

0007In references [3] and [4] below, a free-running digital controlled oscillator (DCO) is periodically calibrated. Although the inherently reduced complexity makes the above described architectures extremely energy efficient, the associated susceptibility to temperature and voltage variations between successive calibration steps makes the use of a free-running DCO (i.e. without closed-loop regulation of the centre frequency) impractical for most applications. In practice, temperature and voltage supply variations are not predictable and may cause a large drift in the generated frequency, which cannot be tolerated. Moreover, the accuracy in the generated frequency is limited to a few percent.

0008The traditional way of improving stability and accuracy of the generated RF frequency is to embed the DCO in a feedback loop, in the form of a phase-locked loop circuit (PLL). Known arrangements are disclosed in references [1] and [2] cited below. The output frequency is then a multiplied copy of the lower reference frequency, which is usually insensitive to PVT variations. Reference [2], for example, discloses a digital controlled oscillator designed to operate at frequencies orders of magnitude higher, around 2.4 GHz, than that supplied by a crystal oscillator reference frequency of around 10-40 MHz.

0009Conventional PLLs can achieve an accuracy of a few ppm (parts per million), but are usually designed to meet stringent phase noise and spectral purity requirements. These lead to high power consumption, which is not suitable for use in ULP applications such as for WSN nodes.

0010<figref idref="f0001">Figure 1</figref> illustrates a simplified block diagram of a modern phase domain all-digital phase locked loop circuit (ADPLL) 10, similar to that described in reference [1] below. The associated DCO and reference phase signals for the circuit 10 are shown in <figref idref="f0001">figure 2</figref>. The DCO phase signal P_DCO is determined by counting the number of rising clock transitions of the output frequency F_o. The reference phase P_REF[k] is obtained by accumulating the frequency command word (FCW) at every rising edge of the frequency reference clock (RefClock). The sampled DCO phase signal P_DCO[k] is subtracted from the reference phase P_REF[k] by a synchronous arithmetic phase detector 11. The digital phase error φ_e thereby obtained is conditioned by a digital loop filter 12, which provides the digital control word (DCW) for the DCO 13.

0011The DCO control word DCW changes the DCO frequency output F_o in a direction that tends to reduce the phase difference between the reference phase signal P_REF[k] and the DCO phase signal P_DCO[k].

0012As the RefClock is generally a constant frequency (since it is typically obtained from a stable crystal oscillator), the reference phase signal P_REF[k] is a linear time function and its slope, <i>FCW</i> · RefClock, corresponds to the desired frequency.

0013When the PLL is locked, the error in phase between P_REF[k] and P_DCO[k], and hence the error in frequency, is on average zero; the output frequency is a multiplied copy of the stable reference frequency. A disadvantage of this type of arrangement is the high power requirement for the DCO and the counter 14. Because these components are always active, this kind of frequency synthesizer would not generally be suitable for ULP applications, where the power consumption should be minimized.

0014In WSN nodes, which are characterized by low activity, PLLs can be duty-cycled to save power. This suggests that the PLL should be operated in a "burst mode", in which short bursts of generated signals are separated by long idle periods in which energy is saved. Although burst mode PLLs are less accurate than conventional PLLs, the achievable frequency accuracy can easily meet the requirements of WSN applications, as disclosed in reference [5]. Moreover, a PLL, because of its closed loop nature is less prone to frequency drift than a free running oscillator.

0015A problem, however, with burst-mode PLLs is that special architectures are required to ensure stability and fast start-up circuitry to avoid extra power consumption during the transitions between active and idle periods.

0016An object of the invention is to provide a frequency synthesizer for an ultra-low power RF transceiver that is able to operate in burst mode while also maintaining a low frequency error.

0017In accordance with the invention there is provided a low power frequency synthesiser circuit for a radio transceiver, the synthesiser circuit comprising: <ul id="ul0001" list-style="none" compact="compact"><li>a digital controlled oscillator configured to generate an output signal having a frequency controlled by an input digital control word;</li><li>a feedback loop connected between an output and an input of the digital controlled oscillator, the feedback loop configured to provide the digital control word to the input of the digital controlled oscillator from an error derived from an input frequency control word and the output signal; and</li><li>a duty cycle module connected to the digital controlled oscillator and the feedback loop, the duty cycle module configured to generate a plurality of control signals to periodically enable and disable the digital controlled oscillator for a set fraction of clock cycles of an input reference clock signal.</li></ul>

0018The invention aims to reduce the power consumption of a frequency synthesizer utilising a digital phase-locked loop by means of duty cycling the operation of the PLL, while maintaining a precise definition of the output frequency despite PVT variations.

0019The feedback loop is optionally configured to store a digital control word in response to one of the plurality of control signals and to use the stored digital control word in controlling the digital controlled oscillator when the digital controlled oscillator is subsequently enabled. An advantage of storing the digital control word between pulses is that the digital controlled oscillator is maintained in a calibrated state, reducing the need for adjustments when subsequently enabled, and thereby reducing the start-up period of the oscillator.

0020The duty cycle module optionally comprises, or is in the form of, a finite state machine (FSM) configured to generate the plurality of control signals driven by the reference clock signal. A finite state machine can be configured to generate a set sequence of timed signals for control of different parts of the oscillator and feedback loop, to ensure that these different parts are enabled and disabled with a timing that maintains operation of each part to a minimum time and thereby minimises power requirements.

0021The digital controlled oscillator optionally comprises a current-controlled ring oscillator and a digital to analog converter configured to receive the digital control word and to provide a current to the ring oscillator that determines the frequency of the output frequency signal. Ring oscillators are able to start up faster than LC oscillators, and are therefore preferred, due to the need for the oscillator to be started up sufficiently quickly for the output signal to be reasonably stable at the start of each pulse.

0022The ring oscillator will typically comprise a plurality of delay stages arranged in a closed loop, the output frequency of the oscillator being controllable by complementary input voltages applied to each of the delay stages.

0023The ring oscillator typically also comprises a pair of capacitors arranged to store the complementary input voltages when the digital controlled oscillator is disabled, which reduce the start-up period of the oscillator as the voltages applied during a previous pulse remain stored on the capacitors.

0024The digital to analog converter of the digital controlled oscillator preferably comprises an R/2R resistor network.

0025The duty cycle module is optionally configured to provide a control signal to enable the digital controlled oscillator in a preset phase using the stored digital control word one or more reference clock cycles prior to enabling the DCO.. During this preset phase, the complementary input voltages can be adjusted according to the frequency control word input prior to the signal being generated, thereby increasing the frequency accuracy of the output signal while keeping operation of the oscillator to a minimum to save power.

0026The duty cycle module may be configured to modulate the temporal position of successive pulses generated by the digital controlled oscillator according to an input data signal. Such a pulse position modulation (PPM) scheme can allow for a simple way of encoding data on to the output of the synthesiser, particularly in cases where a high bit rate is not required.

0027The feedback loop typically comprises a counter module and a phase difference module, the counter module being configured to count cycles of the output signal from the digital controlled oscillator while the digital controlled oscillator is enabled and to provide a output phase signal to the phase difference module, the phase difference module configured to receive the input frequency control word and the output phase signal and to provide an error signal output to determine the digital control word.

0028The duty cycle module may be configured to reset the counter when enabling the digital controlled oscillator with one of the plurality of control signals.

0029The feedback loop may comprise a first feedback loop configured to provide a first part of the digital control word for coarse control of the output frequency of the digital controlled oscillator and a second feedback loop configured to provide a second part of the digital control word for fine control of the output frequency of the digital controlled oscillator. The use of a second feedback loop for fine frequency control allows for fine tuning to align the last rising edge of the DCO output with the reference clock edge, reducing the total error and improving accuracy.

0030The first and second feedback loops optionally comprise an accumulator module configured to provide respective parts of the digital control word and to store the parts of the digital control word when the digital controlled oscillator is disabled. Each accumulator thereby maintains the calibration state of the oscillator between pulses, preventing the oscillator from drifting out of alignment with the set frequency.

0031The first feedback loop may be configured to control the number of cycles of the output frequency signal of the digital controlled oscillator between successive transitions of the reference clock signal, while the second feedback loop is configured to minimise a time difference between transitions of the output frequency signal of the digital controlled oscillator and corresponding transitions in the reference clock signal.

0032Each of the feedback loops may comprise an accumulator module configured to provide respective parts of the digital control word and to store the parts of the digital control word when the digital controlled oscillator is disabled.

0033The first feedback loop may be configured to alter a more significant respective part of the digital control word only when a number of cycles of the output frequency signal between successive reference clock signal transitions differs from the number of cycles indicated by the frequency control word by one or more cycle. This may be achieved by having a deadband in the transfer characteristic of a summing module in the first feedback loop, for example in the form of a horizontal deadband in the relationship between an output error signal of the summing module and a difference between the frequency control word and the number of cycles of the output frequency signal between successive transitions of the reference clock signal.

0034The second feedback loop, however, may be configured to alter a less significant respective part of the digital control word by one or more bits to minimise a time difference between transitions of the output frequency signal and corresponding transitions in the reference clock signal. This may be achieved by having a deadband in the transfer characteristic of a summing module of the second feedback loop, for example in the form of a vertical deadband in the relationship between an output error signal of the summing module and the difference between the frequency control word and the number of cycles of the output frequency signal between successive transitions of the reference clock signal.

0035The duty cycle module is preferably configured to provide one of the plurality of control signals to the digital controlled oscillator to cause the digital controlled oscillator to be enabled in a preset phase to receive the stored digital control word prior to enabling the digital controlled oscillator for generating the output signal. By presetting the oscillator for one reference clock cycle prior to providing the output signal, the oscillator is allowed to settle to a desired frequency, thereby improving the overall accuracy of the output.

0036The frequency synthesiser of the invention is preferably implemented as a module in an integrated circuit, for example forming part of an integrated circuit for a wireless sensor network.

0037Imposing a duty cycle on the frequency generating circuitry of the phase-locked loop allows the circuit to operate at significantly reduced power levels compared with existing digital phase-locked loop circuits. This enables a phase-locked loop circuit in accordance with the invention to operate in a burst mode, thereby realizing an ultra low power frequency synthesizer while providing sufficient frequency accuracy required by radio transceivers for wireless sensor network applications.

0038A particular advantage of a digital phase-locked loop circuit according to the invention is that of improved energy efficiency with a reduced sensitivity to process voltage and temperature (PVT) variations.

0039The invention allows for the generation of a train of pulses with a highly accurate centre frequency. This in turn allows the duty cycle module to modulate the train of pulses to directly encode information to be transmitted to the RF bandwidth.

0040The invention will now be described by way of example and with reference to the appended drawings, in which: <ul id="ul0002" list-style="none" compact="compact"><li><figref idref="f0001">figure 1</figref> is a schematic block diagram of a phase domain all-digital phase-locked loop circuit (ADPLL);</li><li><figref idref="f0001">figure 2</figref> illustrates DCO and reference phase signals for the PLL of <figref idref="f0001">figure 1</figref>;</li><li><figref idref="f0002">figure 3</figref> is a schematic block diagram of a duty-cycled ADPLL;</li><li><figref idref="f0002">figure 4</figref> illustrates synchronisation, DCO phase and reference phase signals for the duty-cycled ADPLL of <figref idref="f0002">figure 3</figref>;</li><li><figref idref="f0003">figures 5a, 5b and 5c</figref> illustrate a) the DCO control word, b) the instantaneous output frequency and c) the output voltage signal of an exemplary duty-cycled ADPLL system as a function of time;</li><li><figref idref="f0004">figure 6</figref> is a schematic block diagram of an alternative embodiment of a duty-cycled ADPLL;</li><li><figref idref="f0005">figure 7</figref> illustrates various waveforms used in the duty-cycled ADPLL of <figref idref="f0004">figure 6</figref>;</li><li><figref idref="f0005">figures 8a and 8b</figref> illustrate a) coarse acquisition and b) fine tuning of the duty-cycled ADPLL of <figref idref="f0004">figure 6</figref>;</li><li><figref idref="f0006">figures 9a and 9b</figref> illustrate transfer characteristics of the counter and subtractor blocks of the duty-cycled ADPLL of <figref idref="f0004">figure 6</figref> for a) course acquisition and b) fine tuning;</li><li><figref idref="f0006">figure 10</figref> is a schematic circuit diagram of a digital controlled oscillator for use with a duty-cycled ADPLL;</li><li><figref idref="f0007">figures 11a and 11b</figref> illustrate the measured output of an exemplary duty-cycled ADPLL, <figref idref="f0007">figure 11b</figref> showing a magnified view of the signal in <figref idref="f0007">figure 11a</figref>;</li><li><figref idref="f0007">figure 12</figref> illustrates a measurement of settling time for an exemplary duty-cycled ADPLL;</li><li><figref idref="f0008">figure 13</figref> illustrates a measured frequency deviation for an exemplary duty-cycled ADPLL as a function of time; and</li><li><figref idref="f0008">figure 14</figref> illustrates a measured instantaneous frequency of the output from a DCO during a single burst for an exemplary duty-cycled ADPLL as a function of time.</li></ul>

0041The aim of the invention is to generate a train of pulses with a fixed time width and with a centre frequency which is locked to the reference clock frequency (RefClock), typically being a multiple of the reference clock frequency. <figref idref="f0002">Figure 3</figref> depicts a schematic block diagram of an exemplary frequency synthesiser 30, comprising a phase domain all-digital frequency-locked loop (ADFLL) 31 and a finite state machine (FSM) 32 as a duty-cycling module. All the blocks in the ADFLL 31 are gated in order to reduce the power consumption between the generation of two successive IR pulses. With proper synchronization, stability of the feedback loop is maintained and the output frequency from the DCO 33 is locked to the stable reference frequency input RefClock with low power consumption.

0042In a general aspect, the frequency synthesiser circuit 30 comprises a feedback loop 31 having a counter module 35, 36 and a phase difference module 34, 37, the counter module 35, 36 being configured to count cycles of the output signal Fo from the digital controlled oscillator 33 while the digital controlled oscillator 33 is enabled and to provide a output phase signal P_DCO[k] to the phase difference module 34, 37, the phase difference module configured to receive the input frequency control word FCW and the output phase signal P_DCO[k] and to provide an error signal output φ_e to determine the digital control word DCW.

0043<figref idref="f0002">Figure 4</figref> shows the synchronization signals provided by the duty-cycling module 32 and the phase signals associated with operation of the synthesiser 30. The DCO 33 is enabled, or activated, for N clock cycles of the reference clock RefClock and is disabled, or switched off, during the remaining M-N clock cycles, where M is the ratio between the RefClock and the pulse repetition frequency PRF. The average power consumption then scales proportionally to the duty-cycle factor <maths id="math0001"><math display="inline"><mfrac><mi>N</mi><mi>M</mi></mfrac><mn>.</mn></math><img file="EP2237418A2_D0001.tif" /></maths>

0044The reference phase <i>P_REF</i>[<i>k</i>] is obtained by accumulating the frequency command word (FCW) at every rising edge of the RefClock signal 43 (<figref idref="f0002">figure 4</figref>). Since the accumulator 34 (<figref idref="f0002">figure 3</figref>) is gated by the synchronization signal DCO_ENABLE 44 from the duty cycle module 32, the reference phase <i>P_REF</i>[<i>k</i>] is in the form of a duty-cycled saw-tooth signal 41 (<figref idref="f0002">figure 4</figref>). The modulus of the accumulator 34 is chosen to be equal to N in order to fix the initial phase of each cycle of the saw-tooth signal 41 to zero. The DCO phase signal <i>P_DCO</i> 45 is determined by counting, by the counter 35, the number of rising clock transitions of the output frequency F_o. In order to align the initial DCO phase with the initial reference phase, the counter 35 is reset before activation of the DCO 33 by means of the COUNTER_RESST synchronization signal 46 from the duty cycle module 32. The sampled DCO phase <i>P_DCO</i>[<i>k</i>] 42 output by the sampler 36 is subtracted from the reference phase <i>P_REF</i>[<i>k</i>] 41 in a synchronous arithmetic phase detector 37. The digital phase error φ_e output from the phase detector 37 is conditioned by a digital loop filter 38, for example in the form of a FIR (finite impulse response) loop filter, the output of which provides the digital control word (DCW) for the DCO 33.

0045Since the Phase Detector 38 and the loop filter 38 are gated, the last sampled phase on each burst, together with the memory of the loop filter, is used to derive the initial control word for a subsequent burst. This information is stored while the system is turned off between bursts. Therefore, in a general aspect, the feedback loop of the ADFLL 31 is configured to store a digital control word in response to one of a plurality of control signals output from the duty cycle module 32 and to use the stored digital control word DCW in controlling the digital controlled oscillator 33 when the digital controlled oscillator 33 is subsequently enabled.

0046The DCO control word DCW changes the output frequency of the DCO 33 in a direction that tends to reduce the phase difference between the reference phase signal P_REF[k] 41 and the sampled DCO phase signal P_DCO[k] 42.

0047When the PLL 31 is locked, <i>P_REF</i>[<i>k</i>] = <i>P_DCO</i>[<i>k</i>] and the output from the DCO 31 consists of a train of pulses with a centre frequency that is a multiple of the RefClock reference frequency, which is usually insensitive to PVT variations.

0048In a preferred embodiment, all the blocks 33-38 are activated for only for a fraction of time, given by the ratio <maths id="math0002"><math display="inline"><mfrac><mi>N</mi><mi>M</mi></mfrac><mn>.</mn></math><img file="EP2237418A2_D0002.tif" /></maths>

0049<figref idref="f0003">Figures 5a, 5b and 5c</figref> illustrate simulation results for a particular embodiment, where the RefClock and FCW are set to 20MHz and 119, respectively. The duty cycle factor is chosen to be <maths id="math0003"><math display="inline"><mfrac><mi>N</mi><mi>M</mi></mfrac><mo>=</mo><mfrac><mn>1</mn><mn>10</mn></mfrac><mo>,</mo></math><img file="EP2237418A2_D0003.tif" /></maths> resulting in an order of magnitude power saving compared with a non-duty-cycled ADPLL. The DCO control word DCW 51 (<figref idref="f0003">figure 5a</figref>) changes over time to fix the centre frequency of the pulses to the desired frequency given by the frequency control word. The instantaneous output frequency (<figref idref="f0003">figure 5b</figref>) settles to the frequency given by <i>FCW</i> · RefClock (2.38 GHz in the example shown). The output of the duty-cycled frequency synthesizer 33 (<figref idref="f0002">figure 3</figref>), as shown in <figref idref="f0003">figure 5c</figref>, is in the form of a train of pulses with a PRF given by <maths id="math0004"><math display="inline"><mfrac><mi>RefClock</mi><mi mathvariant="normal">M</mi></mfrac><mo mathvariant="normal">=</mo><mn mathvariant="normal">2</mn><mspace width="1em" /><mi>MHz</mi></math><img file="EP2237418A2_D0004.tif" /></maths> MHz and a centre frequency equal to 2.38 GHz.

0050A frequency synthesiser according to the present invention can be used at the transmitter side as a pulse generator. By means of the duty-cycle module 32, it is possible to modulate, according to input data, the temporal position of each successive pulse, realizing pulse position modulation (PPM). The resulting signal will already be in the RF bandwidth and no additional power-hungry local frequency generators are required for up-conversion. In a general aspect therefore, the duty cycle module may be configured to modulate the temporal position of successive pulses generated by the digital controlled oscillator according to an input data signal

0051A simplified block diagram of an embodiment of a duty-cycled PLL (DCPLL) frequency synthesiser according to the invention is shown in <figref idref="f0004">figure 6</figref>. The main loop of the synthesiser 60 consists of a DCO 61, a counter 62, an accumulator (ACC1) 63a and one digital subtractor (S1) 64. A second fine tuning loop 65 comprising a second accumulator (ACC2) 63b may be employed to increase the accuracy of the output frequency signal from the DCO 61. Both loops are controlled in an efficient manner by a finite state machine (FSM) 66 connected to an input reference signal generator 67, the FSM 66 being configured to provide three control signal output lines: i) a preset/start/stop signal line connected to the DCO 61, ii) a count/reset signal line connected to the counter 62, and iii) a DCO update line connected to the accumulators 63a, 63b.

0052According to an exemplary embodiment, the DCO 61 illustrated in <figref idref="f0004">figure 6</figref> comprises a current-controlled ring oscillator and a 16-bit digital-to-analog converter (DAC), having 7 bits for coarse frequency acquisition and 9 bits for fine tuning.

0053The reference clock signal generator 67 generates a reference clock signal with a frequency REF of 20 MHz, which drives the FSM 66. The FSM 66 generates the various control signals from this, illustrated in the timing diagrams shown in <figref idref="f0005">figure 7</figref>. In this particular embodiment, the PLL is enabled for 1 out of every 10 cycles of the reference clock signal fref, i.e. N=1, M=10. The DCO 61 is periodically turned on and off by the DCO start/stop signal, while the two loops ensure that the output frequency of the DCO 61 is locked to the reference clock signal REF. After a sleep time of M-1=9 reference clock cycles, the DCO 61 is started up and allowed to run for N=1 reference clock cycle, i.e. for a period T = 50 ns. The resulting integer generated by the counter 62 is compared with the desired frequency control word (FCW) and the resulting error signal updates the DCW stored in the accumulator. Since the error is computed one reference clock cycle after the DCO is stopped, the counter 62 can be implemented as a simple asynchronous D-FF-based counter.

0054When locked, the number of DCO output rising edges between two reference edges is equal to the programmable FCW. With the <maths id="math0005"><math display="inline"><mi>DCO</mi><mo>⁢</mo><mfrac><mi>N</mi><mi>M</mi></mfrac><mo>=</mo><mfrac><mn>1</mn><mn>10</mn></mfrac></math><img file="EP2237418A2_D0005.tif" /></maths> duty-cycled, its output frequency Fo is given by: <maths id="math0006" num="(1)"><math display="block"><msub><mi mathvariant="normal">F</mi><mi mathvariant="normal">o</mi></msub><mo mathvariant="normal">=</mo><mi>FCW</mi><mo mathvariant="normal">⋅</mo><mi>REF</mi></math><img file="EP2237418A2_D0006.tif" /></maths>

0055Conceptually a single loop should be sufficient. However, as shown in <figref idref="f0005">figure 8a</figref>, the DCO rising edge 81 at reference clock pulse FCW+1 might be delayed by Δt_coarse with respect to the reference rising edge 82. This would result in a worst-case frequency error equal to REF. Significantly better performance can be achieved if, in conjunction with the main loop used for handling coarse frequency acquisition, an additional loop 65 (<figref idref="f0004">figure 6</figref>) is employed for fine frequency tuning. A small increase Δf_fine in the DCO output frequency signal advances the last DCO edge by a time .interval Δt_fine (<figref idref="f0005">figure 8b</figref>), which is given by: <maths id="math0007" num="(2)"><math display="block"><mi mathvariant="normal">Δ</mi><mo>⁢</mo><msub><mi>t</mi><mi mathvariant="italic">fine</mi></msub><mo>≃</mo><mfrac><mrow><mi mathvariant="normal">Δ</mi><mo>⁢</mo><msub><mi>f</mi><mi mathvariant="italic">fine</mi></msub></mrow><mi mathvariant="italic">REF</mi></mfrac><mo>⁢</mo><msub><mi>T</mi><mi mathvariant="italic">DCO</mi></msub></math><img file="EP2237418A2_D0007.tif" /></maths> where T_DCO is a DCO period. Before each burst generation, the fine tuning loop 65 increases the DCW by a least significant bit (LSB), thereby increasing the DCO frequency by a small step Δf_fine until the DCO edge at pulse (FCW + 1) only just leads the reference clock edge 82. At this point, the fine tuning loop increases or decreases the DCW by 1 LSB depending on whether the (FCW + 1)_th DCO edge 81 leads or lags the reference clock edge 82. Burst by burst, the frequency then varies by ±Δf_fine and so the last DCO edge oscillates around the reference clock edge. While the main loop controls the number of rising edges occurring between two successive reference clock edges, the fine tuning loop 65 decreases the delay between the last DCO rising edge and the reference clock edge. The total error is reduced and the accuracy is improved, as shown in <figref idref="f0005">figure 8b</figref>.

0056In a general aspect therefore, the feedback loop of the synthesiser 60 comprises a first feedback loop configured to provide a first part of the digital control word for coarse control of the output frequency of the digital controlled oscillator 61 and a second feedback loop 65 configured to provide a second part of the digital control word for fine control of the output frequency of the digital controlled oscillator 61.

0057The quantization error in the frequency generated by the above dual loop configuration is proportional to Δf_fine. This error can be minimized by increasing the DCO resolution. However, in a low power implementation, the accuracy is limited by the DCO's phase noise and, hence, by the total power available. In preferred implementations, Δf_fine is chosen to be low enough to make the quantization noise negligible with respect to the phase noise.

0058Since the PLL operates in burst mode, the fine tuning operation does not require a power hungry "bang-bang" phase detector, but only requires simple logic circuits. <figref idref="f0006">Figures 9a and 9b</figref> illustrate the combined transfer characteristic of the counter and subtractor for the coarse acquisition loop (<figref idref="f0006">figure 9a</figref>) and the fine tuning loop (<figref idref="f0006">figure 9b</figref>). In the transfer characteristic of the coarse acquisition loop, a horizontal deadband 91 is introduced to produce a null error signal when the integer number of DCO edges falling into one clock cycle is equal to the programmed FCW. In order to realize the bang-bang operation of the fine tuning loop, as described above, a vertical dead-band 92 is implemented in its transfer characteristic.

0059In a general aspect therefore, the first feedback loop is configured to control the number of cycles of the output frequency signal of the digital controlled oscillator between successive transitions of the reference clock signal and the second feedback loop 65 is configured to minimise a time difference between transitions of the output frequency signal of the digital controlled oscillator and corresponding transitions in the reference clock signal. The first feedback loop is preferably configured to alter a more significant respective part of the digital control word only when a number of cycles of the output frequency signal between successive reference clock signal transitions differs from the number of cycles indicated by the frequency control word by one or more cycle. The second feedback loop is preferably configured to alter a less significant respective part of the digital control word by one or more bits to minimise a time difference between transitions of the output frequency signal and corresponding transitions in the reference clock signal.

0060The fine tuning dynamics may also be adjusted based on whether the system is in the acquisition or in the steady-state tracking mode. In doing so, both a faster PLL settling time and an accurate frequency output can be achieved. By means of the bandwidth control block 68 (<figref idref="f0004">figure 6</figref>), the gain in the fine loop 65 can be modified to achieve an adaptive bandwidth.

0061The exemplary DCPLL described herein can work only with a fast start-up DCO whose output frequency can settle within a single period of the reference clock, in the present case within 50 ns. Ring oscillators start up faster than LC oscillators, which require approximately Q periods, where Q is the quality factor of the LC tank, to reach steady-state, as for example disclosed in reference [6]. Additionally, if phase noise is not the main requirement, ring oscillators require less power than LC oscillators, as for example disclosed in reference [4]. Finally, since the DCO 61 will be turned off for a significant fraction of time, its static power consumption in idle mode should be very low. These considerations motivate the use of a ring oscillator, as for example shown in <figref idref="f0006">figure 10</figref>. The ring oscillator 100 consists of four delay stages 100a-d in a closed loop, driven by a current IDAC defined by the output of an R/2R ladder current DAC. Each delay stage 100a-d uses a pseudo-differential architecture. The frequency is controlled by the complementary voltages V_p and V_n at the gates of PMOS transistors M₁, M₂, M₃, M₄ and NMOS transistors M₅, M₆, M₇, M₈, the values of V_p and V_n being stored on two large gate capacitors C_p and C_n.

0062The delay stages and input current from the digital to analog converter are switchable under control of one or more control signals from the duty cycle module 66 (<figref idref="f0004">figure 6</figref>). During the idle state, switches s₁ and s₂ are connected to V_dd and Ground, respectively, while the final stage 101d of the delay line is disconnected from the first stage 101 a by means of switches s₃ and s₄. Therefore, the oscillator's power consumption is determined by the leakage currents of the inverters 102a-d. Opening switches 1_s and s₂. and closing switches s₃ and s₄. configures the delay line as an oscillator whose output frequency depends on the control voltages V_p and V_n. Most of the power dissipation of the oscillator is due to switching events (i.e. is proportional to CV²). To synthesize the desired frequency, the per-stage delay is tuned to 1/8 of the desired RF cycle period by means of the DAC current source I_DAC which sets the two voltages V_p and V_n. The DCO start-up delay must be small with respect to the reference period. This requires that C_p and C_n be large capacitors and that the currents through the diodes M₉ and M₁₁ be large enough to set voltages V_p and V_n in a short time. To achieve this while maintaining a low power consumption, a preset phase preferably precedes the DCO's actual start-up. During this preset phase, which preferably starts one reference clock cycle before the DCO is started (shown in the timing diagram in <figref idref="f0005">figure 7</figref>), switches s5, s6, s7 and s8 are enabled and the generated current I_DAC sets the voltage V_p and V_n. When the DCO is started, the required voltages are already preset to their correct values, thus mitigating output frequency variations. The DCO is kept running for the required pulse period, typically one reference cycle, and then shut down by means of switches s1, s2, s3 and s4, which together configure the DCO again as an open-loop delay line. Switches s5, s6, s7 and s8 are opened to preserve the charge stored on capacitors C_p and C_n and the DAC is turned off to save power. In a general aspect therefore, the duty cycle module 66 is configured to provide a control signal to enable the digital controlled oscillator 61 in a preset phase using a digital control word stored by the feedback loop of circuit one or more reference clock cycles prior to enabling the output frequency signal from the synthesiser.

0063The oscillator as outlined above has been realized in a baseline TSMC 65nm CMOS process. The output frequency can be programmed from 200 MHz to 1.2 GHz. The DCPLL output consisting of a train of bursts at 1 GHz with a 10% duty-cycle is shown in <figref idref="f0007">figures 11a and 11b</figref>, with <figref idref="f0007">figure 11b</figref> showing a magnified view of a portion of the signal shown in <figref idref="f0007">figure 11a</figref>. The total current consumption at 1.3 V supply voltage is 200 µA (100 µA for the DCO; 60 µA for the current DAC; and 40 µA for the counter and PLL logic). The measured PLL settling time is shown in <figref idref="f0007">figure 12</figref>. Each point on the curve in <figref idref="f0007">figure 12</figref> represents the average frequency within a single burst. After the generation of 15 bursts, or equivalently 7.5 µs, the output frequency settles to the programmed frequency with an error of around 0.1%. In the case shown, the initial frequency was set to 300 MHz by storing the appropriate DCW in the accumulator. After one calibration, the correct DCW is stored in the two accumulators 63a, 63b (<figref idref="f0004">figure 6</figref>) and the DCPLL is started from the correct condition. The DCPLL continuously monitors the output frequency to follow any temperature and voltage variations. <figref idref="f0008">Figure 13</figref> illustrates the frequency deviation from the programmed frequency (1 GHz in the present case or FCW=50) for 40 consecutive bursts after one process calibration. Each point represents the average frequency within each burst, while the two bold lines represent the 1σ error, i.e. the boundary lines of a single standard deviation from the mean frequency. The absence of the systematic 'bang-bang' frequency jumps confirms that the accuracy in the generated frequency is limited by the DCO phase noise. The simulated open loop DCO phase noise at 1 MHz offset is, indeed, -73 dBc/Hz resulting in a DCO period jitter of 7 ps (rms). After 50 DCO periods, the accumulated jitter for the (FCW +1)^th edge is 50 ps, giving a time uncertainty of 0.1% with respect to the reference clock. This is in accordance with the measured 0.1 % frequency error observed in <figref idref="f0008">figure 13</figref>. It can be seen that the fine tuning loop significantly improves the achieved accuracy; an error of 20 MHz (2%) would be obtained with only the main loop. The standard deviation of the frequency error represents an important parameter for the burst-mode frequency synthesizer since it replaces the closed-loop PLL phase noise.

0064To characterize the DCO's performances, its instantaneous DCO frequency during a burst was measured, the results of which are shown in <figref idref="f0008">figure 14</figref>, together with the interpolated frequency (taking a running average over two successive samples) and the mean frequency over a burst period. The DCO starts at approximately the correct frequency and takes a few DCO periods to settle. The DCPLL is not sensitive to this systematic variations but it tries to tune the average frequency (shown in <figref idref="f0008">figure 14</figref> as dashed line). However, the deviation from the target frequency is maintained within few percent due to the preset strategy.

0065The above exemplary embodiment illustrates a fully-integrated duty-cycled frequency synthesizer, in which frequency multiplication inaccuracy due to noise amounts to around 0.1% (or 1σ). Such a PLL operating in burst mode can be used to generate an high frequency signal accurate enough for WSN applications while maintaining a low power, as for example required by energy autonomous sensor nodes.

0066The exemplary PLL described above can be operated at low duty-cycles, since it employs a fast start-up DCO, resulting in a highly energy-efficient synthesizer. The proposed PLL can be configured to generate signals having frequencies that range from several hundreds of MHz to more than 1 GHz, while maintaining a power consumption of a few hundreds of µW.

0067In conclusion the present invention is suitable for a pulse-based RF transceiver, in which the total power consumption is decreased by a factor equal to the duty-cycle of the signal, while remaining relatively insensitive to PVT variations.

0068Applications for the frequency synthesiser according to the invention include radio transmitters and/or receivers based on impulse radio modulation scheme.

0069Other embodiments are intentionally within the scope of the invention as defined by the appended claims.

References

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