Method and structure for SOI body contact FET with reduced parasitic capacitance

<u>Field of Invention</u>

0001The present invention relates to semiconductor-on-insulator (SOI) devices and methods for fabricating the same. More particularly, a body contact is provided to a semiconductor-on-insulator device that may result in reduced parasitic capacitance to the device.

<u>Background of the Invention</u>

0002Silicon-on-insulator (SOI) technology has become an increasingly important technique utilized in the fabrication and production of semiconductor devices. SOI technology deals with the formation of transistors in a relatively thin monocrystalline semiconductor layer, which overlays an insulating layer. In other words, the active devices are formed in a thin semiconductor disposed on an insulator layer rather than in the bulk semiconductor of the device.

0003In a typical SOI transistor, the body is generally isolated from the silicon substrate and usually kept floating. This may result in problems for current-sensitive circuit applications, since the body typically retains charge from the previous time the transistor was utilized. The retained charge within the body interferes with subsequent use of the device. A variety of solutions have been proposed to address the problems associated with the SOI semiconductor device. For example, the use of a body contact in the SOI device addresses this problem, and also allows the threshold voltage to be changed so that standby power can be reduced for low-power applications. The body contact in the SOI device has conventionally been made by the use of a T-shaped or a H-shaped polysilicon structure on an active area, thereby creating three distinct regions including a source region, a drain region, and a body contact region.

0004The T-shaped or H-shaped polysilicon layer includes a polysilicon gate portion and a polysilicon dummy portion that produces high gate capacitance and typically results in poor performance.

<u>Summary of the Invention</u>

0005In one aspect, a semiconductor device is provided that includes a substrate having a semiconductor layer present overlying an insulating layer, wherein a silicide body contact reduces floating gate effects with an enhancement in parasitic capacitance and gate leakage that is not provided in prior semiconductor structures.

0006Broadly, a semiconductor device is provided that includes: a substrate including a semiconducting layer positioned overlying an insulating layer, the semiconducting layer including a semiconducting body having a first portion and a second portion; isolation regions present about a perimeter of the semiconducting body; a gate structure overlying an upper surface of the first portion of the semiconducting body; and a silicide body contact that is in direct physical contact with the second portion of the semiconducting body, said silicide body contact is separated from the first portion of the semiconducting body by a non-silicide semiconducting region.

0007In another aspect, a method is provided for forming the above-described semiconductor device. Broadly, the method includes the steps of: providing a substrate comprising a semiconducting layer positioned overlying an insulating layer, the semiconducting layer including a semiconducting body and isolation regions present about a perimeter of the semiconducting body; forming a gate structure overlying a portion of the semiconducting body; forming a dielectric spacer abutting the gate structure and atop a portion of the semiconducting body, wherein a remaining portion of the semiconducting body is exposed; forming a silicide on the remaining portion of the semiconducting body; and removing a portion of the dielectric spacer that is adjacent to the silicide to expose a portion of the upper surface of the semiconducting body between the gate structure and the silicide.

0008In another example, the method of forming a semiconductor device includes: providing a substrate comprising a semiconducting layer positioned overlying an insulating layer, the semiconducting layer comprising a semiconducting body and isolation regions present about a perimeter of the semiconducting body; forming a gate structure overlying a portion of the semiconducting body; forming dielectric layer overlying the gate structure and atop a portion of the upper surface of the semiconducting body adjacent to the portion of the upper surface of the semiconducting body underlying the gate structure; removing a portion of the dielectric layer, wherein a remaining portion of the dielectric layer is positioned on a sidewall of the gate structure; and forming a silicide on the semiconductor body adjacent the remaining portion of the dielectric layer.

<u>Brief Description of the Drawings</u>

0009The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, wherein like reference numerals denote like elements and parts, in which: <ul id="ul0001" list-style="none"><li><figref idref="f0001">Figure 1A</figref> is a top planar view of one embodiment of a semiconductor device, in accordance with the present invention.</li><li><figref idref="f0001">Figure 1B</figref> is a side cross-sectional view of the structure depicted in <figref idref="f0001">Figure 1A</figref> along section line A-A, in accordance with the present invention.</li><li><figref idref="f0002">Figure 2A</figref> is a top planar view of another embodiment of a semiconductor device, in accordance with the present invention.</li><li><figref idref="f0002">Figure 2B</figref> is a side cross-sectional view of the structure depicted in <figref idref="f0002">Figure 2A</figref> along section line A-A, in accordance with the present invention.</li><li><figref idref="f0003">Figure 3A</figref> is a top planar view of an initial structure including a gate structure atop a semiconductor-silicon-on-insulator substrate, as used in accordance with the present invention.</li><li><figref idref="f0003">Figure 3B</figref> is a side cross-sectional view of the structure depicted in <figref idref="f0003">Figure 3A</figref> along section line A-A, in accordance with the present invention.</li><li><figref idref="f0004">Figure 4A</figref> is a top planar view depicting forming a dielectric spacer abutting the gate structure, forming a silicide body contact, and forming a photoresist mask (shown in <figref idref="f0004">Figure 4B</figref>), in accordance with the present invention.</li><li><figref idref="f0004">Figure 4B</figref> is a side cross-sectional view along section line A-A of <figref idref="f0004">Figure 4A</figref> that depicts forming a photoresist mask atop the initial structure following the formation of the silicide body contact, in accordance with the present invention.</li><li><figref idref="f0005">Figure 5A</figref> is a top planar view of the structure depicted in <figref idref="f0004">Figure 4A</figref> following an etch step to remove a portion of the gate structure using the photoresist mask as an etch mask, in accordance with the present invention.</li><li><figref idref="f0005">Figure 5B</figref> is a side cross-sectional view of the structure depicted in <figref idref="f0005">Figure 5A</figref> along section line A-A, in accordance with the present invention.</li><li><figref idref="f0006">Figure 6A</figref> is a top planar view of a second embodiment of the present invention, in which a dielectric layer is formed atop the structure depicted in <figref idref="f0003">Figure 3A</figref>, followed by the formation of a photoresist mask, in accordance with the present invention.</li><li><figref idref="f0006">Figure 6B</figref> is a side cross-sectional view of the structure depicted in <figref idref="f0006">Figure 6A</figref> along section line A-A, in accordance with the present invention.</li><li><figref idref="f0007">Figure 7A</figref> is a top planar view depicting etching the dielectric layer to provide a hard mask, in accordance with the present invention.</li><li><figref idref="f0007">Figure 7B</figref> is a side cross-sectional view of the structure depicted in <figref idref="f0007">Figure 7A</figref> along section line A-A, in accordance with the present invention.</li><li><figref idref="f0008">Figures 8A</figref> is a top planar view depicting forming a silicide body contact, in accordance with the present invention.</li><li><figref idref="f0008">Figure 8B</figref> is a side cross-sectional view of the structure depicted in <figref idref="f0008">Figure 8A</figref> along section line A-A, in accordance with the present invention.</li><li><figref idref="f0009">Figure 9A</figref> is a top planar view depicting etching the hard mask, in accordance with the present invention.</li><li><figref idref="f0009">Figure 9B</figref> is a side cross-sectional view of the structure depicted in <figref idref="f0009">Figure 9A</figref> along section line A-A, in accordance with the present invention.</li></ul>

<u>Detailed Description of the Drawings</u>

0010Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the invention that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments of the invention are intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention.

0011The embodiments of the present invention relate to novel methods and structures relating to body contacts to semiconducting devices, in which the inventive body contact reduces parasitic resistance and gate leakage. When describing the following structures and methods, the following terms have the following meanings, unless otherwise indicated.

0012As used herein, "semiconducting body" refers to an intrinsic semiconductor material that has been doped, that is, into which a dopant has been introduced, giving it different electrical properties than the intrinsic semiconductor material. Doping involves adding dopant atoms to an intrinsic semiconductor, which changes the electron carrier concentration and hole carrier concentration of the intrinsic semiconductor. Dominant carrier concentrations in an extrinsic semiconductor classify it as either a p-type or n-type semiconductor.

0013As used herein, a "P-type" refers to the addition of trivalent impurities that create deficiencies of valence electrons to an intrinsic semiconductor, such as boron, aluminum or gallium to an intrinsic Si substrate.

0014As used herein, an "N-type" refers to the addition of pentavalent impurities that contribute free electrons to an intrinsic semiconductor substrate, such as antimony, arsenic or phosphorous dopants to an intrinsic Si substrate.

0015As used herein, "dopant region" refers to portions of the semiconducting body in which the electrical conductivity of the material is dependent upon n-type or p-type dopants.

0016A "body contact" is a conductive structure to the semiconductor body and not present overlying the source and drain regions of the device. The body contact is electrically contacted.

0017As used herein, the term "drain" means a doped region in semiconductor substrates located at the end of the channel in field effect transistors, in which carriers are flowing out of the transistor through the drain.

0018As used herein, the term "source" is a doped region from which majority carriers are flowing into the channel.

0019As used herein, the term "channel" is the region between the source and drain of a metal oxide semiconductor transistor that becomes conductive when the transistor is turned on.

0020A "gate structure" means a structure used to control output current (i.e., flow of carriers in the channel) of a semiconducting device, such as a field effect transistor (FET).

0021As used herein, a "gate dielectric" is a layer of an insulator between the semiconductor device substrate and the gate conductor.

0022As used herein, a "metal" is an electrically conductive material, wherein metal atoms are held together by the force of a metallic bond, and the energy band structure of metal's conduction and valence bands overlap, and hence, there is no energy.

0023As used herein, the "insulating" and/or "dielectric" denote a material having a room temperature conductivity of less than about 10^-10(Ω-m) ^-1.

0024The term "anisotropic etch" denotes a material removal process in which the etch rate in the direction normal to the surface to be etched is greater than in the direction parallel to the surface to be etched.

0025"Electrically conductive" and/or "electrically communicating" as used through the present disclosure means a material having a room temperature conductivity of greater than 10^{- 8}(Ω-m)^-1

0026For purposes of the description hereinafter, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the invention, as it is oriented in the drawing figures. Further, it will be understood that when an element as a layer, region or substrate is referred to as being "atop" or "over" or "overlying" or "below" or "underlying" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly over" of in "direct physical contact" with another element, there are no intervening elements present.

0027References in the specification to "one embodiment", "an embodiment", "an example", etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

0028<figref idref="f0001">Figures 1A and 1B</figref> depict one embodiment of a semiconductor device 100, in accordance with the present invention. The semiconductor device 100 may include a substrate 5 including a semiconducting layer 6 positioned overlying an insulating layer 4. The semiconducting layer 6 as shown, includes a semiconducting body 10. Isolation regions 11, are also shown about a perimeter of the semiconducting body 10. That is, the isolation regions 11 are laterally abutting the semiconducting body 10. The inventive structure may also include a gate structure 50 overlying the semiconducting layer 6 of the substrate 5. The gate structure 50 may be present on a first portion 15 of an upper surface of the semiconducting body 10, and a silicide body contact 60 that is in direct physical contact with a second portion 25 of the semiconducting body 10 that is separated from the first portion 15 of the semiconducting body 10 by a non-silicide semiconducting region 70.

0029The substrate 5 may be a semiconductor-on-insulator substrate, as depicted in <figref idref="f0001">Figure 1B</figref>. The gate structure 50 that is present on the upper surface of the semiconducting body 10 may include a gate dielectric 51 that is present on a portion of the upper surface of the semiconducting body 10 and a gate conductor 52 present overlying the gate dielectric 51. A gate contact silicide 53 may be present atop the gate conductor 52.

0030The gate structure 50 may include a portion that extends onto a surface of an isolation region 11 that is opposite a portion of the gate structure 50 that is in closest proximity to the silicide body contact 60. The portion of the gate structure 50 that overlies the isolation region 11 may have a dimension D1 ranging from about 5 nm to about 30 nm. In one embodiment, the portion of the gate structure 50 that overlies the isolation region 11 includes a substantially co-planar sidewall S1. The term "co-planar" as used to describe the substantially co-planar vertical sidewall S1 means that the sidewall of the gate dielectric 51 is aligned to the sidewall of the gate conductor 52 to provide a planar surface. The gate dielectric 51 typically has a first width W₁ and the gate conductor 52 has a second width W₂, wherein the first width W₁ is greater than the second width W₂.

0031A dielectric spacer 45b may be present abutting the sidewall S1 of the gate structure 50 opposite the portion of the gate structure 50 that is in closest proximity to the silicide body contact 60.

0032The silicide body contact 60 may be present on the upper surface of a second portion 25 of the semiconductor body 10 and extends to a depth of the semiconductor body 10 that is consumed during the silicidation process that provides the silicide body contact 60. The silicide body contact 60 may be positioned on a portion of the semiconductor body 10 that is adjacent to source 101, drain 102, and channel regions of the semiconducting body 10. The silicide body contact 60 may be composed NiSi₂, TiSi₂, CoSi₂, MoSi₂, PtSi₂, TaSi₂, WSi or a combination thereof.

0033The non-silicide semiconducting region 70 that separates the first portion 15 of the semiconducting body 10 from the second portion 25 of the semiconducting body 10 can be a p-type semiconductor region. The non-silicide semiconducting region 70 may have a width W₄ ranging from about 5 nm to about 100 nm. In one embodiment, the non-silicide semiconducting region 70 has a width W₄ ranging from about 10 nm to about 50 nm. In an even further embodiment, the non-silicide semiconducting region 70 has a width W₄ ranging from about 10 nm to about 20 nm.

0034<figref idref="f0002">Figures 2A and 2B</figref> depict an embodiment of the inventive semiconducting device, in which a dielectric spacer 80 is present atop the non-silicide semiconducting region 70.

0035The various components of the structure shown in <figref idref="f0001">Figures 1A-1B</figref>, as well as one embodiments of a method that can be used in forming the same will now be described in greater detail referring to <figref idref="f0003 f0004 f0005 f0006 f0007 f0008 f0009">Figures 3A-10B</figref>.

0036<figref idref="f0003 f0004 f0005">Figures 3A-5B</figref> depict one method for forming a semiconductor device similar to the semiconducting device 100 that is depicted in <figref idref="f0001">Figures 1A-1B</figref>. The method of forming a semiconducting device may begin with providing a substrate 5 including a semiconducting layer 6 positioned overlying an insulating layer 4, the semiconducting layer 6 including a semiconducting body 10. Isolation regions 11 are present about a perimeter of the semiconducting body 10. In a following process step, a gate structure 50 is formed overlying a portion 10 of the semiconducting body 10. The gate structure 50 may include a gate dielectric 51 present on an upper surface of the portion of the semiconducting body 10 and a gate conductor 52 present overlying the gate dielectric 51. Thereafter, dielectric spacers 45a, 45b are formed abutting the gate structure 50 and atop the semiconducting body 10, wherein a remaining portion of the semiconducting body 10 is exposed. In a following process step, a silicide body contact 60 is formed on the remaining portion of the semiconducting body 10. Thereafter, a portion of the dielectric spacer 45a is removed that is adjacent to the silicide body contact 60 to expose a portion of the upper surface of the semiconducting body 10 between the gate structure 50 and the silicide body contact 60.

0037Referring to <figref idref="f0003">Figures 3A and 3B</figref>, one example of an initial structure is depicted including a gate structure 50 atop a substrate 5. The substrate 5 may include a semiconducting layer 6 atop an insulating layer 4. The substrate 5 may be a silicon-on-insulator substrate, wherein an upper Si-containing layer of the SOI substrate provides the semiconducting layer 6 and the buried insulator layer of the SOI substrate provides the insulating layer 4. The substrate 5 is hereafter referred to as an SOI substrate 5; the semiconducting layer 6 is hereafter referred to as the upper Si-containing layer 6; and insulating layer 4 is hereafter referred to as the buried insulating layer 4.

0038In one embodiment, the SOI substrate 5 includes a bottom Si-containing layer (not shown), a buried insulating layer 4, such as an oxide or nitride, located on an upper surface of the bottom Si-containing layer, and an upper Si-containing layer 6 (also referred to as an SOI layer 6), located on the buried insulating layer 4. The term "Si-containing layer" denotes any material that includes silicon. Illustrative examples of Si-containing materials include, but are not limited to: Si, SiGe, SiGeC, SiC, polysilicon, i.e., polySi, epitaxial silicon, i.e., epi Si, amorphous silicon, i.e., a:Si, and multilayers thereof.

0039The upper Si-containing layer 6 of the substrate 5 may be a doped layer, which may contain an n-type or p-type dopant. Doping can be introduced into the SOI layer 6 prior to, or after the formation of the SOI substrate 5. The dopant concentration within the upper Si-containing layer 6 may range from about 1E 17 atoms/cm³ to about 1E 19 atoms/cm³. In one embodiment, the first portion 15 of the SOI layer 6 is doped with an n-type dopant, i.e. n⁺ dopant, wherein the first portion 15 of the SOI layer 6 contains the source 101 and drain regions 102 of the device. Another embodiment, the second portion 25 of the SOI layer 6 is doped with a p-type dopant, i.e., p⁺ dopant, wherein the second portion 25 of the upper Si-containing layer 6 contains the subsequently formed silicide body contact 60 to the device. In a further embodiment, the portion of the upper Si-containing layer 6 that is subsequently processed to provide the non-silicide semiconducting region is doped with a p-type dopant, i.e., p⁺ dopant.

0040The upper Si-containing layer 6 of the SOI substrate 5 may have a thickness ranging from about 10 nm to about 1000 nm. In another embodiment, the upper Si-containing layer 6 of the SOI substrate 5 has a thickness ranging from about 50 nm to about 500 nm. The thickness of the buried insulating layer 4 may range from about 100 to about 1000 nm. In another embodiment, the buried insulating layer 4 has a thickness that ranges from about 120 nm to about 200 nm.

0041The SOI substrate 5 can be formed using a layer transfer process or a bonding process. In another embodiment, a technique referred to as separation by implanted oxygen (SIMOX) wherein ions, typically oxygen or nitrogen, are implanted into a bulk Si-containing substrate and then the substrate containing the implanted ions is annealed under conditions that are capable of forming a buried insulating layer 4 can be employed.

0042After providing the substrate 5, a pad oxide layer (not shown) is typically formed on an upper exposed surface of the SOI substrate 5 by a thermal oxidation process. The pad oxide layer may also be formed by a deposition process, such as chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition, evaporation or solution deposition. The pad oxide layer formed at this point of the present invention typically has a thickness ranging from about 5 nm to about 20 nm. Embodiments of the present invention have been contemplated in which the pad oxide layer is omitted.

0043In a following process step, isolation regions 11 may be formed into the SOI substrate 5 by forming a hardmask (not shown) on the surface of the pad oxide layer and then utilizing lithography and etching. The lithographic step employed in the present invention may include applying a photoresist (not shown) to the hardmask material layer; exposing the photoresist to a pattern of radiation (in the present case a trench pattern is employed); and developing the pattern into the photoresist utilizing a conventional resist developer. The etching step, which may be used to transfer the trench pattern first into the hardmask and then into the pad oxide layer and the SOI substrate 5, includes any dry etching process, such as reactive-ion etching, ion beam etching, plasma etching, laser ablation or any combination thereof. In one embodiment, a single etching process may be employed, or in another embodiment, more than one etching process may be employed to form trenches in the SOI substrate 5. After the pattern has been transferred into the hardmask, the photoresist is typically removed from the structure and then pattern transfer continues using the hardmask as an etch mask. In one embodiment, the depth of the trenches formed may stop within the SOI layer 6 of the SOI substrate 5, or in another embodiment, the depth of the trenches may extend down to the buried insulating layer 4.

0044After trenches have been formed in the SOI substrate 5, the trenches are filled with a trench dielectric material such as high-density plasma (HDP) oxide or TEOS (tetraethylorthosilicate) using a deposition processes. The filled trenches form isolation regions 11 in the structure that serve to isolate various device regions from each other. In some embodiments of the present invention, the walls of the trenches are lined with a liner material, such as SiO₂ or Si₃N₄, prior to filling with the trench fill material. After the filling process, a planarization process and/or densification may be performed on the structure. The planarization process can be stopped on the hardmask and thereafter the hardmask may then be removed by utilizing an etching process that selectively removes the hardmask material from the structure. In the embodiments of the present invention, in which the pad oxide layer is present, the pad oxide layer may be removed from the surface of substrate 5 using a stripping process that is highly selective in removing oxide.

0045Still referring to <figref idref="f0003">Figures 3A and 3B</figref>, the gate structures 50 may formed using deposition, photolithography and selective etching processes. The gate structures 50 include a gate conductor 52 atop a gate dielectric 51. In one embodiment, the gate conductor 52 material is polysilicon. In another embodiment, the gate conductor 52 may also be composed of elemental metals, metal alloys, metal silicides, or other conductive materials. The gate conductor 52 layer may be formed using chemical vapor deposition, such as plasma enhanced chemical vapor deposition, or physical vapor deposition, such as plating or sputtering. The gate conductor 52 layer may have a thickness ranging from about 10 nm to about 100 nm.

0046The gate dielectric 51 may be a low-k dielectric material (having a dielectric constant equal to or less than 4.0) such as SiO₂ or SiON or a high-k dielectric (having a dielectric constant greater than about 4.0), such as oxides of Ta, Zr, Al or combinations thereof. Hf containing high-k dielectrics are also contemplated and are within the scope of the present invention. The thickness of the gate dielectric layer 51 is typically from about 1 nm to about 10 nm. More typically, the gate dielectric 51 has a thickness of from about 1.5 to about 2.5 nm. The gate dielectric 51 may be formed using a deposition method, such as chemical vapor deposition. The gate dielectric layer 8 may also be formed using a thermal growth method, such as thermal oxidation.

0047The gate structure 50 can be formed from the material layers of the gate dielectric 51 and the gate conductor 52 using photolithography and etch processing steps. For example, a pattern is produced by applying a photoresist to the surface to be etched; exposing the photoresist to a pattern of radiation; and then developing the pattern into the photoresist utilizing conventional resist developer. Once the patterning of the photoresist is completed, the sections covered by the photoresist are protected, while the exposed regions are removed using a selective etching process that removes the unprotected regions.

0048<figref idref="f0004">Figures 4A and 4B</figref> depict the formation of a dielectric spacer 45a, 45b adjacent the sidewalls S₁, S₂ of the gate structure 50 in accordance with one embodiment of the present invention. The dielectric spacer 45a, 45b may be composed of an oxide, nitride or oxynitride material. The dielectric spacer 45a, 45b is typically composed of silicon nitride and is formed in direct physical contact with the sidewalls of the gate conductor 52. The dielectric spacer 45a, 45b may be formed using deposition and etch processes, and may have a width W₃ ranging from about 2 nm to about 70 nm. In another embodiment, the dielectric spacer 45a, 45b may be formed using deposition and etch processes, and may have a width W₃ ranging from about 6 nm to about 30 nm. The thickness of the dielectric spacer 45a, 45b may be selected to dictate the dimension of separation between the subsequently formed silicide body contact 60 and the gate structure 50.

0049A thin spacer (not shown) may be formed on the sidewall of the gate structure 50 prior to the formation of the dielectric spacer 45a, 45b. In one embodiment, in which the dielectric spacer 45a, 45b is composed of silicon nitride, a thin spacer composed of an oxide may be formed using a conformal deposition process on the sidewall of the gate structure 50 prior to the formation of the dielectric spacer 45a, 45b. The thin spacer may be formed using thermal oxidation and may have a thickness ranging from about 1 nm to about 5 nm.

0050In a following process step, a silicide that provides the silicide body contact 60 is formed on the portion of the upper surface of the semiconductor body 10 that is not covered by the spacer 45a, 45b or the gate structure 50. Silicide formation typically includes depositing a metal layer, such as a refractory metal, onto the surface of a Si-containing material. The metal layer may be deposited using physical vapor deposition (PVD), such as plating or sputtering, or may be deposited using chemical vapor deposition (CVD). The metal layer may be composed ofNi, Ti, Co, Mo, Pt, Ta, W or a combination thereof. Following deposition, the structure is then subjected to an annealing step using conventional processes such as, but not limited to, rapid thermal annealing. During thermal annealing, the deposited metal reacts with Si forming a metal semiconductor alloy, which is also referred to as a metal silicide. In one embodiment, the silicide, i.e., silicide body contact 60, is composed NiSi₂, TiSi₂, CoSi₂, MoSi₂, PtSi₂, TaSi₂, WSi or a combination thereof. A gate contact silicide 53 may also be formed atop the gate conductor 52. Following thermal anneal, the unreacted portions of the metal layer may be removed with a selective etch process.

0051<figref idref="f0004">Figures 4A and 4B</figref> also depict one embodiment of forming an photoresist mask 90 for removing a portion of the dielectric spacer 45a, 45b that is adjacent the silicide body contact 60 to expose the upper surface of the semiconductor body 10 that is present between the gate structure 50 and the silicide body contact 60. The step of removing a portion of the dielectric spacer 45a, 45b may include forming a photoresist mask 90 overlying the gate structure 50 and exposing the portion of the dielectric spacer 45a, 45b that is to be removed in order to expose the upper surface of the semiconductor body 10 between the gate structure 50 and the silicide body contact 60.

0052It is noted that the portion of the upper surface of the semiconductor body 10 that is exposed during this process step corresponds to the non-silicide semiconducting region 70 that separates the first portion 15 of the semiconducting body 10 from the second portion 25 of the semiconducting body 10. The photomask 90 may also expose a portion of the gate structure 50. In one embodiment, the exposed portion of the gate structure 50 has a length ranging from about 2 nm to about 60 nm, as measured from the sidewall of the gate structure 50 that is adjacent to the portion 45b of the dielectric spacer 45a, 45b that is exposed by the photoresist mask 90. In another embodiment, the exposed portion of the gate structure 50 has a length ranging from about 5 nm to about 20 nm, as measured from the sidewall of the gate structure 50 that is adjacent to the portion 45b of the dielectric spacer 45a, 45b that is exposed by the photoresist mask 90.

0053A process sequence for producing the photoresist mask 90 may begin with depositing a layer of photoresist material atop the surface to be etched via spin coating or similar processes. The photoresist material may be composed of dielectrics including carbon, oxygen, and various inorganic materials. Following application of the photoresist layer, the photoresist is softbaked, where the solvents of the photoresist layer are evaporated via heating.

0054In a following process step, the layer of photoresist is then patterned utilizing photolithography and development process steps to provide patterned photoresist mask 90. Specifically, a pattern may be formed using a reticle or photomask and transferred into the surface of the layer of the photoresist. First, the pattern on the reticle or photomask is transferred onto a layer of photoresist on the surface to be etched, wherein light is passed through the opaque pattern of the reticle, which in turn produces a patterned image on the layer of photoresist. The photoresist layer is a light or radiation sensitive material and exposure to light causes changes in the photoresist structure. For example, exposure to light may change the exposed portions of the photoresist from a soluble condition to an insoluble one.

0055Following exposure the pattern is developed utilizing a resist developer, such as a chemical solvent. The developer leaves a hole in the resist layer that corresponds to the opaque pattern of the reticle. An alternative resist strategy, commonly referred to as a negative resist, leaves a pattern in the resist opposite to that on the mask. Development of the pattern is conducted using development techniques including, but not limited to: continuous spray development and puddle development. Following development, the portion of the dielectric spacer 45a adjacent the silicide body contact 60 is exposed, wherein the remaining portion of the photoresist layer is present overlying the silicide body contact 60 and at least a portion of the gate structure 50.

0056<figref idref="f0005">Figures 5A and 5B</figref> depict an etch step to remove a portion 45a of the dielectric spacer 45a, 45b that is adjacent the silicide body contact 60 and expose the upper surface of the semiconductor body 10 that corresponds to the non-silicide semiconducting region 70, which separates the silicide body contact 60 from the gate structure 50. The etch process may be a selective etch. As used herein, the term "selective" in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied. In one embodiment, in which the silicide gate contact 53 is present, the etch step removes the exposed portion of the dielectric spacer 45a selective to the photoresist etch mask 90, the silicide gate contact 51 and the semiconducting body 10. When the dielectric spacer 45a is composed of silicon nitride, the etch chemistry of the selective etch process may include a wet hot phosphoric acid or a reactive ion etch using an etch chemistry that may include CH₃, CH₄, or NF₃. In a following process, a selective etch step is conducted to remove the exposed portion of the silicide gate contact 53 and the portion of the gate conductor 52 underlying the exposed portion of the silicide gate contact 53 selective to the photoresist mask 90, the gate dielectric 51 and the semiconductor body 10. When the silicide gate contact 53 is composed of NiSi₂, and the gate conductor 52 is composed of silicon, the gate dielectric 51 is composed of SiO₂, the selective etch chemistry may be composed of HBr/O₂.

0057The etch process may be an anisotropic etch process, such as reactive ion etch (RIE). Reactive ion etching is a form of plasma etching, in which during etching the surface to be etched is placed on an RF powered electrode, wherein the surface to be etched takes on a potential that accelerates the etching species that is extracted from a plasma towards the surface to be etched, in which a chemical etching reaction is taking place in the direction normal to the surface. In a following process step, the photoresist mask 90 may be removed using a stripping process, such as oxygen ashing to provide the final structure depicted in <figref idref="f0001">Figures 1A and 1B</figref>.

0058<figref idref="f0006 f0007 f0008 f0009">Figures 6A-9B</figref> depict one embodiment of method for forming a semiconductor device 100 similar to the semiconducting device depicted in <figref idref="f0002">Figures 2A-2B</figref>. The method of forming a semiconducting device may begin with providing a substrate 5 including a semiconducting layer 6 positioned overlying an insulating layer 4. The semiconducting layer 6 of the substrate may include a semiconducting body 10. Isolation regions 11 are present about a perimeter of the semiconducting body 10. Thereafter, a gate structure 50 may be formed overlying a portion of the semiconducting body 10. The gate structure 50 may include a gate dielectric 51 present on an upper surface of the portion of the semiconducting body 10 and a gate conductor 52 present overlying the gate dielectric 51. In a following step, a dielectric layer 55 may be formed overlying the gate structure 50 and atop a portion of the upper surface of the semiconducting body 10 adjacent to the portion of the upper surface of the semiconducting body 10 underlying the gate structure 50. A portion of the dielectric layer 55 may then be removed, wherein a remaining portion 56 of the dielectric layer 55 is positioned on a sidewall S₂ of the gate structure 50. Thereafter, a silicide body contact 60 can be formed on the semiconductor body 10 adjacent the remaining portion 56 of the dielectric layer 55.

0059The step of removing a portion of the dielectric layer 55 may include forming a photoresist etch mask 95 that exposes the portion of the dielectric layer 55 that is to be removed and etching the exposed portion of the dielectric layer, wherein the portion of the dielectric layer 55 underlying the etch mask 95 is protected to provide the remaining portion 56 of the dielectric layer that is positioned on the sidewall S₂ of the gate structure 50.

0060<figref idref="f0006">Figures 6A and 6B</figref> depict forming a dielectric layer 55 atop the structure depicted in <figref idref="f0003">Figure 3A</figref> followed by the formation of a photoresist mask 95. It is noted that the above description corresponding to <figref idref="f0003">Figure 3A</figref> is applicable to the present embodiment of the invention.

0061The dielectric layer 55 may be composed of an oxide, a nitride or an oxynitride. The dielectric layer 55 can be a stress-inducing material. In one example, the dielectric layer 55 is composed of silicon nitride. The dielectric layer 55 may be formed using chemical vapor deposition, such as plasma enhanced chemical vapor deposition, or thermal growth. In one embodiment, the dielectric layer 55 has a thickness ranging from about 10 nm to about 100 nm. In another embodiment, the dielectric layer 55 has a thickness ranging from about 30 nm to about 60 nm.

0062The photoresist mask 95 may be formed utilizing photolithography and development process steps. A pattern is produced by applying a photoresist layer to the surface to be etched; exposing the photoresist layer to a pattern of radiation; and then developing the pattern into the photoresist layer utilizing resist developer. Once the patterning of the photoresist layer is completed, the sections covered by the photoresist layer are protected, while the exposed regions of the dielectric layer 55 are removed.

0063<figref idref="f0007">Figures 7A and 7B</figref> depict etching the dielectric layer 55 to provide a hard mask. The etch step to remove the portions of the dielectric layer 55 that are exposed by the photoresist mask 95, may be a selective etch step that removes the exposed portion of the dielectric layer 55 selective to the photoresist mask 95, the gate conductor 52 and the semiconducting body 10. When the dielectric layer 55 is composed of silicon nitride, the etch chemistry of the selective etch process may include wet hot phosphoric acid or a reactive ion etch using an etch chemistry that may include CH₃, CH₄, or NF₃. The etch process can be an anisotropic etch process, which may include reactive ion etch (RIE). In a following process, the photoresist mask 95 is removed using a stripping process, such as oxygen ashing.

0064<figref idref="f0008">Figures 8A and 8B</figref> depict forming a silicide body contact 60 atop the upper surface of the semiconductor body 10 that is adjacent the remaining portion 56 of the dielectric layer that is abutting the sidewall S₂ of the gate structure 50, and forming a silicide gate contact 53 atop the exposed portion of the gate conductor 52 that is adjacent the remaining portion of the dielectric layer 55 that is overlying the upper surface of the gate conductor 52. The silicide that provides the silicide body contact 60 and the silicide gate contact 52 may be positioned on the upper surface of the semiconductor body 10 and the gate conductor 52 that is not covered by the remaining portion 56 of the dielectric layer 55. Silicide formation typically includes depositing a metal layer, such as a refractory metal, onto the surface of a Si-containing material. The metal layer may be deposited using physical vapor deposition (PVD), such as plating or sputtering or may be deposited using chemical vapor deposition (CVD). The metal layer may be composed of Ni, Ti, Co, Mo, Pt, Ta, W or a combination thereof. Following deposition, the structure is then subjected to an annealing step using conventional processes such as, but not limited to, rapid thermal annealing. During thermal annealing, the deposited metal reacts with Si forming a metal semiconductor alloy, which is also referred to as a metal silicide. In one embodiment, the silicide, i.e., silicide body contact 60 and the silicide gate contact 53, are composed NiSi₂, TiSi₂, CoSi₂, MoSi₂, PtSi₂, TaSi₂, WSi or a combination thereof.

0065<figref idref="f0009">Figures 9A and 9B</figref> depict recessing the remaining portion 56 of the dielectric layer that is positioned on the sidewall S₂ of the gate structure 50. The remaining portion 56 can recessed until the remaining portion 56 of the dielectric layer is removed from the upper surface of the gate structure 50 that is adjacent to the silicide gate contact 53. The remaining portion 56 of the dielectric layer 55 may be recessed using a selective etch process. The remaining portion 56 of the dielectric layer 55 is recessed with an etch chemistry that removes the material of the dielectric layer 55 selective to the gate conductor 52, the silicide gate conductor 53, and the silicide body contact 60. In one embodiment, the remaining portion 56 of the dielectric layer 55 is recessed to a height ranging from about 2 nm to about 20 nm. The recessed remaining portion 56 of the dielectric layer is hereafter referred to as a dielectric spacer 80.

0066In a following process step, an anisotropic etch step removes the portion of the gate conductor 52 that is not underlying the silicide gate contact 53, wherein the anisotropic etch step may include reactive ion etch. The anisotropic etch step may include a selective etch chemistry that removes the gate conductor 52 without substantially etching the silicide gate contact 53, the silicide body contact 60, or the dielectric spacer 80. In one embodiment, in which the silicide body contact 60 is composed of NiSi₂, the silicide gate contact 53 is composed of NiSi₂, the dielectric spacer 53 is composed of silicon nitride, and the gate conductor 52 is composed of polysilicon, the anisotropic etch includes an etch chemistry composed of CF₃, CH₄, and/or NF₃. The anisotropic etch step may expose a portion of the gate dielectric 51, as depicted in <figref idref="f0002">Figures 2A and 2B</figref>.

0067At this point, BEOL (back-end-of-the-line) processes may be performed to provide on the final structure shown in <figref idref="f0001 f0002">Figures 1A-2B</figref>. For example, a layer of insulating material such as BPSG (boron doped phosphorus silicate glass) can be formed over the structure by deposition and planarization. Contact openings can be formed into the insulating layer by lithography and etching and thereafter the contact holes can be filled with a conductive material, such as, for example, Cu, Al, W, polysilicon and other like conductive materials.

0068While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

0069Various aspects of the subject-matter described herein are set out in the following clauses that constitute a part of this detailed description of the preferred embodiments:

0070The semiconductor device as described above, wherein the substrate comprises a semiconductor-on-insulator substrate.

0071The semiconductor device as described above, wherein the silicide body contact comprises NiSi₂, TiSi₂, CoSi₂, MoSi₂, PtSi₂, TaSi₂, WSi or a combination thereof.

0072The semiconductor device as described above, wherein the gate dielectric has a first width and the gate conductor has a second width, the first width being greater than the second width.

0073The method as described above, wherein the metal layer comprises Ni, Ti, Co, Mo, Pt, Ta, W or a combination thereof.