Quick pixel rendering processing

BACKGROUND

I. Field

0001The present disclosure relates generally to image processing, and more specifically to techniques for a three-dimensional (3D) graphics pipeline for providing quick pixel rendering processing without a dedicated hardware graphics accelerator.

II. Background

0002Converting information about 3D objects into a bit map that can be displayed is known as pixel rendering, and requires considerable memory and processing power. In the past, 3D graphics were available only on powerful workstations, but now 3D graphics accelerators are commonly found in personal computers (PC). The hardware graphics accelerator contains memory (e.g. instruction random access memory (IRAM)) and a specialized microprocessor to handle many of the 3D rendering operations. Open GL® (Open Graphics Library) for desktops defines an application programming interface (API) for writing applications that produce 3D and 2D computer graphics. The API includes hundreds of functions for drawing complex three-dimensional scenes from primitives.

0003OpenGL® ES is a subset of the desktop OpenGL® which creates an interface between software and graphics. The 3D Graphic Engine (OpenGL®ES) is implemented into generally two parts. The first part includes those functions which process the vertex and is typically implemented in the digital signal process (DSP) firmware. The second part includes those functions for pixel rendering and are implemented in a dedicated hardware graphics accelerator. The second part which performs the pixel rendering is the last pipeline stage of a conventional 3D graphic engine. The last pipeline stage processes input triangle sets to produce a pixel representation of the graphic image. However, the last pipeline stage is typically the performance bottle neck of the entire 3D graphic pipeline in the engine. Therefore, it is very important to improve the performance (in pixel per second) of the last pipeline stage for pixel rendering.

0004Typically, during pixel rendering operations, each input triangle needs to be processed sequentially, in the same order as the triangles are input. Thus, a processor with multi-threads is prevented from utilizing interleaved parallel processing to process an input triangle.

0005Furthermore, the hardware graphic accelerators are not generally flexible or easily scalable. Thus, the hardware graphic accelerators cannot easily add new features, support higher versions of the 3D graphics standard (such as OpenGL®ES 1.0, 1.1 ...), support different application configurations and customize requirements. Furthermore, the hardware graphic accelerators are not easily scaled for different performance requirements (frame rate, screen size, pixel rate, triangle rate, etc...), to optimize silicon cost and system power consumption.

0006As can be readily seen, a dedicated hardware graphics accelerator takes up silicon area in small handheld computing devices, such as a mobile or cellular telephone. Accordingly, a dedicated hardware graphics accelerator increases the overall cost of a handheld computing device by the inclusion of the dedicated hardware graphics accelerator and IRAM used. The use of a dedicated hardware graphics accelerator also produces data traffic with the DSP which adds overhead and consumes power.

0007There is therefore a need in the art for techniques for a three-dimensional (3D) graphics pipeline which provide quicker pixel rendering processing without a dedicated hardware graphic accelerator. Document "<nplcit id="ncit0001" npl-type="s"><text>Software-based geometry operations for 3D computer graphics" by Mihai Sima et. al. in Proceedings SPIE 7513, vol. 6074, 2-2-2006</text></nplcit> discloses a multi-threaded 3D rendering architecture based on Sandbridge.

SUMMARY

0008Techniques for a three-dimensional (3D) graphics pipeline which provide quicker pixel rendering processing without a dedicated hardware graphic accelerator are described herein. The invention is defined by the appended claims. In an embodiment, a three-dimensional (3D) graphics pipeline includes a vertex processing stage operable to output vertex information for a 3D graphics image. A display sub-dividing stage divides pixels in a display area, having the output vertex information superimposed thereon, into sub-screens, the sub-screens forming a sub-screen task list. A pixel rendering stage processes in parallel and independently multiple sub-screen tasks in the sub-screen task list.

0009In another aspect, a wireless device has a digital signal processor having a plurality of processing threads, a shared memory accessed by the processing threads, and a processor. The processor is operable to perform pixel rendering without a dedicated graphics accelerator by processing in parallel and independently those pixels in multiple sub-screen tasks in a sub-screen task list stored in the shared memory. The sub-screen task includes a portion of pixels of a display area having superimposed vertex output information.

0010Various aspects and embodiments of the disclosure are described in further detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

0011Aspects and embodiments of the disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. <ul id="ul0001" list-style="none" compact="compact"><li><figref idref="f0001">FIG. 1</figref> illustrates a general block diagram of a 3D imaging apparatus.</li><li><figref idref="f0002">FIG. 2</figref> illustrates an interleaved multi-threading processor interfaced with shared memory.</li><li><figref idref="f0003">FIG. 3</figref> illustrates details of the interleaved multi-threading processor with details of each thread shown.</li><li><figref idref="f0004">FIG. 4</figref> illustrates a graph of the execution time versus the core pipeline of the interleaved instructions processed by the multi-threading processor with six threads.</li><li><figref idref="f0005">FIG. 5</figref> illustrates two parallel instruction sets processed by two threads.</li><li><figref idref="f0006">FIG. 6</figref> illustrates a general flow diagram of the 3D graphics pipeline in an exemplary 3D imaging apparatus.</li><li><figref idref="f0007">FIG. 7</figref> illustrates a general block diagram of the processes of the 3D graphics pipeline.</li><li><figref idref="f0008">FIG. 8A</figref> illustrates the display space being sub-divided into a MxN grid where M> 1 and N> 1.</li><li><figref idref="f0008">FIG. 8B</figref> illustrates the TASK list for processing the sub-divided display space of <figref idref="f0008">FIG. 8A</figref>.</li><li><figref idref="f0009">FIG. 9</figref> illustrates the display space being sub-divided into a MxN grid where M = 1 and N>1.</li><li><figref idref="f0010">FIG. 10</figref> illustrates the display space being sub-divided into a MxN grid where M >1 and N=1.</li><li><figref idref="f0011">FIG. 11</figref> illustrates a triangle defined by vertex coordinates with a plurality of pixels.</li><li><figref idref="f0012">FIG. 12</figref> illustrates a graphical representation of the instruction operations for processing a triangle in an area sub-divided into a set of four sub-divided areas.</li><li><figref idref="f0013">FIG. 13</figref> illustrates the flowchart of the 3D graphic pipeline method using a multi-threading processor.</li></ul>

DETAILED DESCRIPTION

0012The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

0013Many game applications, require three-dimensional (3D) graphics applications with display 3D objects in a two-dimensional (2D) space (e.g., a display screen). The pixels in a 2D graphic have the properties of position, color, and brightness while a 3D pixel adds a depth property that indicates where the point lies on an imaginary Z-axis. Texture is created as 3D pixels are combined, each with its own depth value.

0014Referring now to <figref idref="f0001">FIG. 1</figref>, an embodiment of a 3D imaging apparatus, generally designated at 10, is shown. The 3D imaging apparatus 10 includes a communication unit 12, a digital signal processor (DSP) 20, screen 16 with a display area 18, a memory 24 and Input/output (I/O) units 45. The shared memory 24 may store game applications or other applications (i.e. for two-way communications with wired or wireless networks, and other software applications) as desired by the user or to support the feature set of the apparatus 10. The I/O units 45 may include a keypad, keyboard or data communication ports. The screen 16 is operable to display in the display area 18 2D information as well as 3D graphics.

0015The 3D imaging apparatus 10 may include one of a personal digital assistant (PDA), and a mobile, cellular or satellite telephone, a laptop, Notebook, Tablet PC, Palm Pilot, wireless communications device or the like.

0016Referring now to <figref idref="f0002 f0003 f0004 f0005">FIGS. 2-5</figref>, in the exemplary embodiment, the DSP 20 includes an interleaved multi-threading processor 22. The interleaved multi-threading processor 22 has a plurality of processing threads (PT) PT1, PT2, ... PTX. Each processing thread (PT) PT1, PT2, ... PTX shares the same memory denoted as shared memory 24. Each processing thread 1, ... X includes a respective one set of instructions 26₁... 26_X, a core 27₁... 27_X (processing unit) and a register file 28₁... 28_X. The output of each core 27₁... 27_X communicates with the shared memory 24. The instructions 26₁... 26_X include the programming code for carrying out the operations defined below and other operations for carrying out the feature set, such as multi-media) of the 3D imaging apparatus 10. The core 27₁... 27_X executes the instructions 26₁... 26_X.

0017The register file 28₁... 28_X is a set of general purpose registers and is the center stage of the DSP 20 or a microprocessor. These register files 28₁... 28x hold all the operands (typically loaded from memory), that is, hold all the results from all operations (such as arithmetic op, logic op, etc.) before storing the results into the shared memory 24.

0018Some DSP architectures have four threads. Nevertheless, the DSP 20 can have more than four threads such as, without limitation, six processing threads which run in parallel. In the exemplary embodiment, each thread (PT) PT1, PT2, ... PTX in parallel provides 100 million instruction packets per second (MIPS). Each instruction packet can be four (4) instructions, two (2) instructions (Sup-scalar) or just one instruction. However, one instruction is not recommended for efficiency, because the architecture of the DSP 20 removes the inefficiency caused by inter-instruction data dependency.

0019The terms thread or multi-threading are used to describe concurrent task execution. Instead of a single path of execution, a program (Operations) may be split into multiple execution threads which execute simultaneously. In the exemplary embodiment, there is a starting thread which requires a function call (or instruction), and usually requires at least two arguments: (1) the address of the start instruction; and (2) a context argument. While a thread is operating and/or exiting, the thread needs to be able to do two basic jobs in relation to other processing threads: (1) acquire a shared resource and block other threads from using such resource; and (2) safely send messages to other threads (e.g. done, ready, etc.)

0020Referring now to <figref idref="f0004">FIG. 4</figref>, a graph of the interleaved multi-threading parallel processing is shown. In this example, there are six (6) processing threads PT1, PT2, PT3, PT4, PT5 and PT6. The first processing thread PT1 processes a first instruction set 1. This is represented by the first (top) row of the execution time line for the core pipeline. The core pipeline is denoted by cores 27₁, ... 27x. While the first instruction set 1 is processed by the first processing thread PT1, the second processing thread PT2 processes its first instruction set 1. This is represented by the second row of the execution time line. Thus, the first instruction sets 1 are being parallel processed.

0021The third processing thread PT3 processes its first instruction set 1 while the first and second processing threads PT1 and PT2 process their first instruction sets 1. This is represented by the third row of the execution time line for the core pipeline. The fourth processing thread PT4 processes its first instruction set 1. Meanwhile, the first, second and third processing threads PT1, PT2 and PT3 continue processing their associated first instruction sets 1. This is represented by the fourth row of the execution time line for the core pipeline.

0022The fifth processing thread PT5 processes its first instruction set 1 while the first, second, third and fourth processing threads PT1, PT2, PT3 and PT4 continue processing their first instruction sets 1. This is represented by the fifth row of the execution time line for the core pipeline. The sixth processing thread PT6 processes its first instruction set 1 while the first, second, third, fourth and fifth processing threads PT1, PT2, PT3, PT4 and PT5 continue processing their first instruction sets 1. This is represented by the sixth row of the execution time line for the core pipeline. Thus, the processing of instructions by the processing threads is interleaved.

0023Referring now to the seventh (bottom) row of <figref idref="f0004">FIG. 4</figref>, assuming that the first processing thread PT1 has completed its first instruction set 1, the first processing thread PT1 begins processing a second instruction set 2 while the second, third, fourth, fifth and sixth processing threads PT2, PT3, PT4, PT5 and PT6 continue processing their first instruction sets 1. Hence, the processing of each of the processing threads PT1, PT2, ...PTX are in parallel and interleaved.

0024Describing the interleaved processing for all processing threads is prohibitive. Thus, for illustrative purposes, the interleaved processing using instructions 26₁ and 26₂ is shown in <figref idref="f0005">FIG. 5</figref> as it relates to a mutex. A mutex is a tool that is "owned" by only one processing thread at a time. When a processing thread tries to acquire a mutex, it LOCKS the mutex. On the other hand, if the mutex is already LOCKED, that processing thread is halted. When the owning thread UNLOCKS the mutex, the halted thread is restarted and acquires ownership of the mutex. This process is shown in <figref idref="f0005">FIG. 5</figref>.

0025Starting with the first processing thread PT1, instructions 26₁ beings with step S22A where non-critical code is executed. Step S22A is followed by step S24A where the first processing thread PT1 executes a LOCK mutex 1 instruction (assuming, the mutex 1 is UNLOCKED). Thus, the first processing thread PT1 now owns the mutex 1. Step S24A is followed by step S26A where critical code is executed. Step S26A is followed by step S28A where after the critical code is completed, the first processing thread PT1 executes an UNLOCK mutex 1 instruction. Thereafter, the first processing thread PT1 resumes execution of non-critical code at step S30A.

0026In parallel with the first processing thread PT1, the second processing thread PT2 begins instructions 26₂ at step S22B where non-critical code is executed. Step S22B is followed by step S24B where the second processing thread PT2 wants to LOCK the mutex 1 at step S24B. However, the mutex 1 is in a LOCKED state. Thus, the operations of the second processing thread PT2 are halted until the first processing thread PT1 UNLOCKS the mutex 1 at step S28A. Then step 26B commences where the critical code may be executed. Step S26B is followed by step S28B where after the critical code is completed, the second processing thread PT2 executes an UNLOCK mutex 1 instruction. Other instructions may continue thereafter.

0027The mutex tool or another token tool is used to guarantee serial execution of critical sections in different processing threads only as needed. This is also serializing execution which means that certain code may not be executed in parallel when it could conflict with the execution of code by other threads. The mutex tool is helpful because a shared memory 24 (shared resource) is used.

0028Referring now to <figref idref="f0006">FIGS. 6</figref> and <figref idref="f0007">7</figref>, there is shown an embodiment of a general flow and block diagrams of the 3D graphics pipeline, generally designated at 100. The 3D graphics pipeline 100 divides the entire task of 3D representation in the display area 18 of screen 16 into generally three (3) pipeline stages: a vertex processing (VP) stage 110, a screen sub-dividing (SSD) stage 130 and a pixel rendering (PR) stage 140. In operation, the vertex processing (VP) stage 110 includes all the functions or a subset of the functions currently implemented in the OpenGL® or OpenGL®ES and is processed by a digital signal processor (DSP) 20. The line to the screen 16 is shown in phantom because the screen 16 is not part of the 3D graphics pipeline 100.

0029The VP stage 110 includes model view transform operations 112, projection operations 114, culling operations 116, lighting and coloring operations 118, primitive assembly operations 120, clipping (i.e. user-defined clipping) operations 122, and perspective division and viewport operations 124. Each of these operations of the VP stage 110 are well defined in the OpenGL® or OpenGL® ES.

0030In general, the model view transform operations 112 use math operations to place object models into desired positions and orientations. The projection operations 114 use math operations that make close things large and far things smaller. Occlusion draws near objects in front of far ones. Culling and clipping operations 116 and 122 discard things that are not in view. Lighting operations 118 calculate the effects of lights on surfaces.

0031In the exemplary embodiment, the VP stage 110 can be implemented with one processing thread (<figref idref="f0002">FIGS. 2</figref> and <figref idref="f0003">3</figref>). The vertex output information includes vertex information to define a triangle and its location in the display area 16. The vertex output information is superimposed on the display area 16 in that the pixels of the display area 16 include the vertex output information to define triangles in accordance with the OpenGL®, OpenGL® ES or other graphics libraries.

0032The screen sub-dividing (SSD) stage 130 includes screen sub-dividing operations 132 which divide the display area 18 into M ^∗ N sub-screens. The display area 18 is made up of a plurality of pixels P (<figref idref="f0011">FIG. 11</figref>) with the vertex output information superimposed. The vertex information from the VP stage 110 provides vertex information (such as V1, V2 and V3 of <figref idref="f0011">FIG. 11</figref>) defining triangles (such as, T1, and T2 of <figref idref="f0008">FIG. 8A</figref>) for superposition in the display area 18. The vertex information may include vertex coordinates and edge information. In general, the vertex output information for each triangle is just a set of mathematical descriptions to define a closed area. This set of math-descriptions is stored in the shared memory 24 so that each processing thread (PT1, PT2, ... PTX) can use the set of math descriptions to compute each pixel P (<figref idref="f0011">FIG. 11</figref>) within its own sub-screen task and decide if the pixel is inside a triangle or not.

0033<figref idref="f0008">FIG. 8A</figref> illustrates vertex output information superimposed on the display area 18. During the screen sub-dividing (SSD) stage 130 the display area 18 is sub-divided by dividing or grouping the pixels that makeup the display area 18 into MxN sub-screen tasks as best seen in <figref idref="f0008">FIG. 8B</figref>. The MxN sub-screen tasks are MxN independent tasks stored in the shared memory 24. The operations of the SSD stage 130 can be implemented using a processing thread which is separate from the processing thread used during the VP stage 110. Alternately, the operations of the SSD stage 130 can be combined with the operations of the VP stage 110 on the same processing thread.

0034In the embodiment shown in <figref idref="f0008">FIG. 8A</figref>, the display area 18 is divided into MxN sub-screens wherein M>1 and N>1 to create a grid. For illustrative purposes, <figref idref="f0009">FIG. 9</figref> shows the display area 18' divided into MxN sub-screens wherein M =1 and N>1. The arrows illustrate the scan or work flow direction. With reference to <figref idref="f0010">FIG. 10</figref>, the display area 18" is divided into MxN sub-screens wherein M>1 and N=1. Thus, the sub-screens of display area 18" form a series of columns.

0035The pixel rendering (PR) stage 140 includes rasterization, blending, and texture application operations 142 and hidden surface removal operations 144. Nevertheless, the pixel rendering stage 140 may include other operations defined by OpenGL® or OpenGL® ES. The PR stage 140 converts the information about 3D objects from the VP stage 110 into a bit map that can be displayed in the display area 18 of screen 16. The PR stage 140 processes input triangle sets to produce a pixel representation of a 3D graphic image.

0036A typical pixel rendering (PR) stage may first take a triangle from a list of the vertex output information. Next the PR stage would take a pixel from the display area and compute the pixel against the triangle to see if it is inside the triangle. If the pixel under evaluation is inside the triangle, the PR stage may perform coloring of the pixel with the corresponding color from the triangle. If the pixel under evaluation is not inside the triangle, the pixel is skipped. The PR stage would then pick the next pixel in the display area 18. The PR stage repeats the above process for other pixels in the display area 18 until all pixels have been evaluated or processed for a triangle. Thus, pixels are processed one at a time.

0037Then, the typical PR stage would move to the next triangle in the list of vertex output information and repeat the evaluation of the pixels for the current triangle.

0038The PR stage 140 works in a similar manner with multiple sub-screens or sub-screen tasks. The difference is that the sub-screens have a smaller number of pixels to evaluate or process and multiple sub-screens can be processed independently and in parallel by the processing thread (PT1, PT2, ... PTX). Thus, the processing time for the PR stage 140 is much quicker then a typical PR stage because less pixels are in each sub-screen and multiple sub-screens can be processed in parallel (with each processing thread working independently towards processing the pixels in a respective one sub-screen).

0039In the exemplary embodiment, the PR stage 140 is processed using a set of the multiple processing threads PR1, PR2, ... PRX of the interleaved multi-threading processor 22. The number of threads in the set used for the PR stage 140 may be 2 or more with a maximum of X threads.

0040In operation, each processing thread PR1, PR2, ... PRX assigned to the pixel rendering stage 140 seizes an available sub-screen task from the Task list 135 and removes it from the Task list 135. The set of processing threads PR1, PR2, ... PRX process, in interleaved parallel operations, input triangles to render the pixels in the sub-screens (convert the input triangle information into a bit map for display in the sub-screens). After, a respective one processing thread has completed the pixel rendering operations for the seized sub-screen task, the processing thread moves to the next available sub-screen task in the Task list 135. This operation is repeated until all sub-screens have been processed and the pixel rendering stage 140 is complete.

0041The interleaved multi-threading processor 22 allows the multi-thread processing to be scalable and homogeneous. The operation <i>Ô</i> can be defined by <maths id="math0001" num=""><math display="block"><mi>Ô</mi><mfenced separators=""><mi>A</mi><mo>+</mo><mi>B</mi></mfenced><mo>=</mo><mi>Ô</mi><mfenced><mi>A</mi></mfenced><mo>+</mo><mi>Ô</mi><mfenced><mi>B</mi></mfenced><mo>;</mo></math><img file="EP2122575B1_D0001.tif" /></maths> and <maths id="math0002" num=""><math display="block"><mi>Ô</mi><mfenced><mstyle displaystyle="true"><munder><mo>∑</mo><mi>i</mi></munder><msub><mi>T</mi><mi>i</mi></msub></mstyle></mfenced><mo>=</mo><mstyle displaystyle="true"><munder><mo>∑</mo><mi>i</mi></munder><mrow><mi>Ô</mi><mfenced><msub><mi>T</mi><mi>i</mi></msub></mfenced></mrow></mstyle></math><img file="EP2122575B1_D0002.tif" /></maths>

0042With reference to <figref idref="f0012">FIG. 12</figref>, a block of four sub-screens with a single triangle T is shown for pixel rendering. The operation <i>Ô</i> processes sub-screen tasks S₁₁, S₁₂, S₂₁ and S₂₂ represented as four (i) sub-screens each with a sub-divided portion (i) of a triangle T. The operation <i>Ô</i> is thus equal to operation <i>Ô</i>₁ of the sub-screen S₁₁ plus operation <i>Ô</i>₂ of the sub-screen S₁₂ plus operation <i>Ô</i>₃ of the sub-screen S₂₁ plus operation <i>Ô</i>₄ of the sub-screen S₂₂. If all of the operations <i>Ô</i>₁, <i>Ô</i>₂, <i>Ô</i>₃ and <i>Ô</i>₄ are processed in parallel, the overall peak performance for processing the pixel rendering stage 140 is thus the peak performance for a processing thread multiplied by the number of processing threads used. The sub-screen S₁₁ has a sub-divided portion T₁ of pixels for triangle T. The sub-screen S₁₂ has a sub-divided portion T₂ of pixels for triangle T. The sub-screen S₂₁ has a sub-divided portion T₃ of pixels for triangle T. The sub-screen S₂₂ has a sub-divided portion T₄ of pixels for triangle T. For illustrative purposes, the number of threads is four (4). Hence, in this example, the performance would be the performance for one processing thread multiplied by the number of the processing threads. Thus, the PR stage 140 is a quick pixel rendering stage by virtue of its ability to process in parallel pixels from multiple sub-screens.

0043In addition, the numbers of M and N can be configured after profiling with real application, so that the performance can be further optimized for different situations. Configuring M and N provides another dimension of greater flexibility and scalability. Profiling includes identifying the loading (tick count) of the processing thread or the size or complexity of the operational tasks. Profiling may also include evaluating other components such as parameters associated with the transfer of data and memory capacity from the shared memory 24. With profiling and adjustment, frame rate, screen size, pixel rate, triangle rate, etc. could be used to change or vary M and N and/or to vary the number of processing threads PR1, PR2, ... PRX for use in the PR stage 140. The remaining processing threads PR1, PR2, ... PRX are used for other applications which are running concurrently, such as game-audio.

0044Referring now to <figref idref="f0013">FIG. 13</figref>, the flowchart of the 3D graphics pipeline method 200 for use by the 3D graphics pipeline 100 is shown. The method 200 begins with step S202 where the vertex processing is performed to create vertex output information. Step S202 is followed by step S204 where the display area 18, having the vertex output information superimposed therein, is sub-divided into MxN sub-screens. For example, as best seen in <figref idref="f0008">FIG. 8A</figref>, the triangle T1 expands across the sub-screens S₁₁, S₂₁ and S₂₂ and is sub-divided into its respective sub-divided portions T1₁, T1₂, T1₃ shown in <figref idref="f0008">FIG. 8B</figref>. Thus, the Task list 135 in <figref idref="f0008">FIG. 8B</figref> illustrates the sub-divided portions of triangles T1 and T2 (only two triangles shown for illustrative purposes). As can be appreciated, those entries in the Task list 135 from the vertex output information that does not have associated therewith a triangle or has a smaller sub-divided portion of a triangle may be processed quicker. Hence, before the pixel rendering stage 140 displays a 3D image representative of the triangle on the display area 18, the processing for all sub-divided portions of the triangle should be complete.

0045Step S204 is followed by step S206 where the sub-screen tasks with or without sub-portions of the triangles are created and placed in the Task list 135. Step S206 is followed by step S208₁, 208₂, and 208_Y where Y is the number of the processing threads (2 or more) in the set used for the pixel rendering stage 140. At step S208₁, the first processing thread (hereinafter referred to as "thread 1") gets the (first) available sub-screen task (<figref idref="f0008">FIG. 8B</figref>), processes each pixel in the sub-screen task at step S210₁ (especially those pixels determined to be within or inside of a triangle or triangle portion associated with the task). Step S210₁ is followed by step S212₁ where a determination is made whether it is the end of the Task list 135. If the determination is "YES," the processing by thread 1 is ended. Otherwise, if the determination is "NO," step S212₁ returns to step S208₁. The operation of second processing thread (hereinafter referred to as "thread 2") is essentially the same. Thread 2 gets or seizes the next available sub-screen task in the Task list 135. Step S208₂ is followed by step S210₂ where the sub-screen task is processed. Step S208₂ is followed by step S210₂. Step S210₂ is followed by step S212₂. At step S212₂, a determination is made whether there are any more tasks in the Task list 135. If the determination at step S212₂ is "NO," the method ends. Otherwise, if the determination is "YES," step S212₂ returns to step S208₂.

0046Step S208_Y gets or seizes the Y^th available sub-screen task by thread Y. Step S208_Y is followed by step S210_Y where the sub-screen task is processed. Step S210_Y is followed by step S212_Y where a determination is made whether there are any more tasks in the Task list 135. If the determination is "NO," the method ends. Otherwise, if the determination is "YES," step S212_Y returns to step S208_Y.

0047The processing carried out during step S210₁, S210₂ and S210y performs the rasterization, blending, texture application operations 142 and the hidden surface removal operations 144. With specific reference to <figref idref="f0011">FIG. 11</figref>, the squares with a center dot denote pixels P. Some of the pixels P are inside of the triangle T11 while some pixels are outside of the triangle T11. Each vertex V1, V2 and V3 has a color value attached with smooth shading. Linear interpolation is used to calculate the color values at each pixel P. The vertexes V1, V2 and V3 are used to form triangle T11 and locate such triangle within the display area 18. The colors are calculated at each pixel center, denoted by the black dot, in the center of the square. Various parameters are interpolated including a Z-depth, alpha, fog and texture.

0048Referring again to <figref idref="f0002 f0003 f0004">FIGS. 2-4</figref>, in this example, there are six (6) threads PT1, PT2, PT3, PT4, PT5 and PT6. The first thread PT1 can be used to process the VP stage 110. The second thread PT2 can be used to process the SSD stage 130. The remaining four threads PT3, PT4, PT5 and PT6 would be used to process sub-screen tasks from the Task List 135 in parallel. Here, the processing thread PT3 would get the first available sub-screen task 1,1 and process the pixels in the seized first sub-screen task 1,1. The processing thread PT4 would get the next (2^nd) available sub-screen task 1,2 and process the pixels in the seized sub-screen task 1,2. The processing thread PT5 would get the next (3^rd) available sub-screen task 1,3 and process the pixels in the seized sub-screen task 1,3 (assuming M is greater than 3).

0049Assuming M is 4, the processing thread PT6 would get the next (4^th) available sub-screen task 1,M and process the pixels in the seized sub-screen task 1,M. As the processing threads PT3, PT4, PT5 and PT6 complete their each sub-screen task, additional sub-screen tasks would be seized and processed in parallel until the Task list 135 is empty.

0050If one processing thread performs 3 Mpixel/sec rendering, it would take approximately 30 instruction packets to process one pixel. This is about 100 instructions per pixel in average. Reserving two of the six threads for the VP stage 110 and the SSD stage 130, with the remaining four processing threads to do the pixel rendering, would support a VGA resolution which is four times the performance (12M pixel/sec) of a dedicated hardware graphics accelerator.

0051Because all processing threads share the same memory 24, the processing threads can all process the same set of input triangle data (sub-screen tasks) very efficiently (without duplication) using the mutex tool.

0052The pixel rendering stage 140 is the last pipeline stage of the 3D graphics pipeline 100. The PR stage 140 processes the input triangle list to produce a pixel representation of a 3D graphic image. The 3D graphics pipeline 100 described above improves the performance (in pixel per second) of the PR stage 140. The interleaved multi-thread processor 22 increases the performance by a multiple of the number of the processing threads running in parallel to process the Task list 135.

0053An advantage of the 3D graphics pipeline architecture is its flexibility in allowing adjustment of the numbers M and N. By increasing the number M and N, the MIPS requirement decreases for the pixel rendering stage 140. Because each sub-screen becomes smaller, the rendering task becomes simpler. This helps to increase the performance of multiple processing threads. The processing threads can also be used for other concurrent applications, such as audio.

0054As can be readily seen, the software implementation, described herein, for rendering 3D graphic images has a higher performance than hardware implementation of a dedicated graphics accelerator. In comparison to a hardware implementation of a graphics accelerator, the embodiment described herein is flexible and scalable. Because the embodiment is flexible, it is easy to extend the software code for adding new features, support higher versions of the 3D graphics standard (such as OpenGL ES 1.0, 1.1 ...), and support different application configurations and custom requirements. The scalable feature of the embodiment allows for different performance requirements (frame rate, screen size, pixel rate, triangle rate, etc...), to optimize silicon cost and system power consumption

0055This embodiment also enables the software implementation to be used with a low cost and low power processor, instead of using a high end processor with multi-GHz clock speed to reach the same performance.

0056In exemplary embodiments, the methods and processes described herein may be implemented in hardware, software, firmware, or any combination thereof in a form of a computer program product comprising one or more computer-executable instructions. When implemented in software, the computer program product may be stored on or transmitted using a computer-readable medium, which includes computer storage medium and computer communication medium.

0057The term "computer storage medium" refers herein to any medium adapted for storing the instructions that cause the computer to execute the method. By way of example, and not limitation, the computer storage medium may comprise solid-sate memory devices, including electronic memory devices (e.g., RAM, ROM, EEPROM, and the like), optical memory devices (e.g., compact discs (CD), digital versatile discs (DVD), and the like), or magnetic memory devices (e.g., hard drives, flash drives, tape drives, and the like), or other memory devices adapted to store the computer program product, or a combination of such memory devices.

0058The term "computer communication medium" refers herein to any physical interface adapted to transmit the computer program product from one place to another using for example, a modulated carrier wave, an optical signal, a DC or AC current, and the like means. By way of example, and not limitation, the computer communication medium may comprise twisted wire pairs, printed or flat cables, coaxial cables, fiber-optic cables, digital subscriber lines (DSL), or other wired, wireless, or optical serial or parallel interfaces, or a combination thereof.

0059The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the disclosure. Thus, the disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed by the claims.