EP2005477A4
Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor
3 sheets
Sheet 1 Sheet 2 Sheet 3
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| US2003230778A1 | Cites | United States of America | Search report |
| US2004075143A1 | Cites | United States of America | Search report |
| US2006030093A1 | Cites | United States of America | Search report |
| US5218213A | Cites | United States of America | Search report |
| US6690043B1 | Cites | United States of America | Search report |
| US6881635B1 | Cites | United States of America | Search report |
| See also references of WO 2007117775A2 | Non-patent | – | Search report |
11 members in 6 offices
Priority claims3
| Document | Office | Kind | Date |
|---|---|---|---|
| 393340 | United States of America | – | |
| 39334006 | United States of America | A | |
| 2007062559 | United States of America | W |
Members11
| Document | Office | Kind | |
|---|---|---|---|
| US2007238250A1 | United States of America | A1 | |
| WO2007117775A2 | World Intellectual Property Organization (WIPO) | A2 | |
| WO2007117775A3 | World Intellectual Property Organization (WIPO) | A3 | |
| TW200802624A | Taiwan Province of China | A | |
| KR20080108498A | Republic of Korea | A | |
| EP2005477A2 | European Patent Office (EPO) | A2 | |
| US7494856B2 | United States of America | B2 | |
| JP2009532875A | Japan | A | |
| EP2005477A4This record | European Patent Office (EPO) | A4 | |
| JP5203352B2 | Japan | B2 | |
| TWI447815B | Taiwan Province of China | B |
17 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Application deemed to be withdrawnWithdrawn18D | 18D | |
| Information on the status of an ep patent application or granted ep patentGrantedSTATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWNSTAA | STAA | |
| First examination report despatched17Q | 17Q | |
| Party data changed (applicant data changed or rights of an application transferred)RAP1 | RAP1 | |
| Request for extension of the european patent (deleted)DAX | DAX | |
| Supplementary search report drawn up and despatchedA4 | A4 | |
| Information provided on ipc code assigned before grantRIC1 | RIC1 | |
| Information provided on ipc code assigned before grantRIC1 | RIC1 | |
| Information provided on ipc code assigned before grantRIC1 | RIC1 | |
| Information provided on ipc code assigned before grantRIC1 | RIC1 | |
| Designated contracting states (corrected)RBV | RBV | |
| Information on inventor provided before grant (corrected)RIN1 | RIN1 | |
| Information on inventor provided before grant (corrected)RIN1 | RIN1 | |
| Information on inventor provided before grant (corrected)RIN1 | RIN1 | |
| Request for examination filed17P | 17P | |
| Designated contracting statesAK | AK | |
| Public reference made under article 153(3) epc to a published international application that has entered the european phaseORIGINAL CODE: 0009012PUAI | PUAI |
Numbers
- Publication
- 2005477
- Application
- 77573160
Titles3
- German
- HERSTELLUNGSVERFAHREN FÜR HALBLEITER MITTELS ÄTZSTOPPSCHICHT ZUR OPTIMIERTEN BILDUNG VON SOURCE-DRAIN-STRESSOR
- English
- SEMICONDUCTOR FABRICATION PROCESS USING ETCH STOP LAYER TO OPTIMIZE FORMATION OF SOURCE/DRAIN STRESSOR
- French
- PROCEDE DE FABRICATION DE SEMI-CONDUCTEUR UTILISANT UNE COUCHE D'ARRET DE GRAVURE POUR OPTIMISER LA CONSTITUTION D'ELEMENTS DE CONTRAINTE DE SOURCE/DRAIN
Classification
- CPC, 10
- H10D30/797
- H10D62/021
- H10D30/0323
- H10D30/6741
- H10P90/1916
- H10W10/181
- H10P90/1906
- H10W10/014
- H10W10/061
- H10W10/17
- IPC, 7
- H01L29 76
- H01L21 762
- H01L29 786
- H01L29 78
- H10D30 01
- H10D30 67
- H10D48 36
Designated states1
- Contracting states, 1
- United Kingdom
