Method for producing an integrated circuit

p0001The present invention relates to a method for manufacturing an integrated circuit comprising the steps of:<ul><li>Providing a semiconductor wafer having first and second surfaces,</li><li>Generating at least one circuit structure in a defined wafer section in the area of ​​the first surface, and</li><li>The wafer section is exposed in a first process sequence so that it is held on the remaining semiconductor wafer only by means of local, stepped connections at a lateral periphery of the wafer section, and the steplike connections are carried out in a second process sequence The first process step including forming a wafer cavity below the defined wafer portion.</li></ul>

p0002Such a method is known from <patcit id="pcit0001" dnum="EP1351292A2"><text>EP 1 351 292 A2</text></patcit> known.

p0003The present invention relates in particular to a method for producing so-called chips with an integrated electronic circuit, the chips or the chip material being very thin. Chips according to the invention can have a thickness of significantly less than 300 μm, advantageously a thickness of 50 μm and less. Such thin chips are well suited for the production of so-called 3D chips, in which several thin chips, each with an integrated circuit, are stacked on one another. Moreover, such thin chips have a certain flexibility due to the low material thickness so that they can be used on flexible carrier materials such as, for example, a plastic film.

p0004One way to produce such thin chips with an integrated circuit is to manufacture the integrated circuit first on a semiconductor wafer with a thickness of, for example, 500 μm to 1 mm. After manufacturing the integrated circuit, the back of the semiconductor wafer is ablated by a mechanical and / or chemical process. Subsequently, the semiconductor wafer, typically carrying a plurality of integrated circuits, must be isolated to the chips. Conventionally, this is done by sawing, cutting, cutting or scratching and breaking. A method for separating semiconductor wafers into chips is described in<patcit id="pcit0002" dnum="DE4029973A1"><text>DE 40 29 973 A1</text></patcit> Described.

p0005The described procedure has the disadvantage that a considerable part of the wafer material is lost by the removal unused. Furthermore, relatively large spacings between the individual chips must be provided on a wafer in order to provide sufficient space for sawing, separation loops, etc. Typical distances here are of the order of magnitude of 500 μm to 1 mm. All this has a detrimental effect on the cost of producing thin integrated circuits, ie chips with material thicknesses of less than 150 μm.

p0006<patcit id="pcit0003" dnum="WO2005104223A1"><text>WO 2005/104223 A1</text></patcit> Describes a method in which a plurality of vertical trenches are first produced on the first surface of the semiconductor wafer by an anisotropic etching process. Subsequently, the opened first surface is closed again by an epitaxial layer, and the semiconductor wafer is subjected to heat treatment (annealing). In this way, individual closed channels are to be formed below the first surface. In a further anisotropic etching process, vertical accesses to the hidden channels are then created. Subsequently, the inner walls of the channels and the vertical access points are provided with an oxide layer by an oxidation process. The channels and vertical access points surround a wafer section on the first surface, in which a circuit structure is then produced in a conventional manner. Subsequently, the oxide layer in the channels and vertical access points is removed by a further etching process, so that the wafer section is connected to the rest of the wafer only by means of spike connections on its underside. These connections are broken by tearing the wafer section upwards out of the remaining semiconductor wafer, a torsion movement being additionally proposed. With this method, chips with a thickness of less than 10 μm are to be produced.

p0007A disadvantage of this method is that the underside of the separated chips should have a strong roughness (compared to the material thickness of the chips) because irregular fracture edges of the former wire-like connections remain on the underside of the wafer section. In addition, the formation of the underlying oxide layers under the wafer section and their subsequent selective etching out is complicated and difficult.

p0008The above <patcit id="pcit0004" dnum="EP1351292A2"><text>EP 1 351 292 A2</text></patcit> Describes a method for fabricating an integrated circuit on an SOI wafer. After the integrated circuit is fabricated, in addition to the circuit, openings are formed in the overlying silicon layer and the underlying oxide layer. A material is subsequently introduced into these openings, which forms support piers in the subsequent process step. In this subsequent process step, the overlying silicon layer is re-opened to guide an etchant to the underlying oxide layer. The oxide layer under the integrated circuit is removed with the etch so that the integrated circuit "floats" over a cavity and is supported on the support arrows.

p0009An article by Overstolz et al. with the title "<nplcit id="ncit0001" npl-type="s"><text>A Clean Wafer Scale Chip Release Process Without Dicing Based On Vapor Phase Etching ", 17th IEEE International Conference on Micro Electromechanical Systems, January 2004, pages 717 to 720</text></nplcit>, It is known to remove a micromechanical sensor, namely a tilt knife, from a silicon material by means of different etching processes alone. An SOI wafer (Silicon on Insulator) is used as starting material. To remove the tilt sensor, trenches and holes are etched from both the front and rear surfaces of the wafer material. In addition, the oxide layer located in the semiconductor material is partially etched by applying a hydrofluoric acid vapor through the holes on the front and rear sides to the inside of the semiconductor wafer.

p0010<patcit id="pcit0005" dnum="US6165813A"><text>US 6,165,813</text></patcit> Discloses a method for loosening thin chips attached to a flexible substrate by bending the substrate. <patcit id="pcit0006" dnum="US6521068B"><text>US 6,521,068</text></patcit> Describes a method for separating chips from a substrate, wherein a region below the chip is heated with a laser.

p0011<patcit id="pcit0007" dnum="JP2002299500A"><text>JP 2002-299500</text></patcit> Describes the removal of chips with the aid of a so-called dummy substrate.

p0012Finally, the production and use of porous silicon is known in the art. <patcit id="pcit0008" dnum="DE19752208A1"><text>DE 197 52 208 A1</text></patcit> Discloses a process for producing a membrane sensor wherein a thin layer of silicon carbide or silicon nitride is deposited over a region of porous silicon. The porous silicon is subsequently removed as a sacrificial material with ammonia. As a result, a cavity is formed beneath the membrane layer of silicon carbide or silicon nitride, which thermally decouples the sensor membrane from the remaining substrate.

p0013Furthermore, porous silicon is used in the so-called ELTRAN process (epitaxial layer TRANsfer), with the aid of which SOI wafers are produced. The approach is described in a publication by T. Yonehara and K. Sakaguchi, entitled "<nplcit id="ncit0002" npl-type="s"><text>ELTRAN; Novel SOI wafer technology "in JSAP International No. 4, July 2001</text></nplcit> Has been published.

p0014Against this background, it is an object of the present invention to provide an alternative method for producing thin integrated circuits as cost-effectively as possible with good quality and yield.

p0015This object is achieved according to one aspect of the present invention by a method of the type initially mentioned, wherein a closed wafer cavity is produced by means of the following steps:<ul><li>Providing a substrate wafer with an upper side of a first semiconductor material, in particular a highly p-doped silicon,</li><li>Producing a plurality of porous regions in the first semiconductor material, each porous region having a surface expansion approximately equal to the area expansion of the defined wafer portion, and </li><li>Forming a cover layer on the top which covers the porous regions.</li></ul>

p0016The new process differs from the method of the initially mentioned <patcit id="pcit0009" dnum="WO2005104223A1"><text>WO 2005/104223 A1</text></patcit> In that the bearing circular connections, which hold the wafer section before the final singling, act substantially laterally on the wafer section. Preferably, the spotty links hold the wafer portion at a plurality of opposing corners or sides, surrounding the wafer portion. In some embodiments of the invention, the spotty connections are arranged at the corners of a rectangular wafer section. In other embodiments, the spotty connections can be located on the longitudinal sides of a rectangular wafer section. Moreover, the present invention is not limited to rectangular wafer portions (and corresponding chips). For example, stepped connections can also be arranged on the outer circumference of a wafer section that is round or elliptical in the base area.

p0017The present invention does not exclude the fact that individual steplike connections also exist below the wafer section to be triggered. However, depending on the method by which the wafer section is exposed in the first process sequence, this is a "residual effect" (to be explained below). In the first place, however, the wafer section according to the present invention is held by the local, star-studded connections at its lateral periphery.

p0018By the new way of "suspending" the wafer portion at its periphery, it is possible to push the wafer portion into the semiconductor wafer to break the spotty connections. The wafer section can thus be broken out of the remaining material of the semiconductor wafer by a pressing force from the top according to the new method. In contrast, in the method according to the initially mentioned method,<patcit id="pcit0010" dnum="WO2005104223A1"><text>WO 2005/104223 A1</text></patcit> A tensile force can be applied, and this tensile force must be so strong that it separates the spider-like connections in their longitudinal direction. In contrast to this, shear forces can be used in the new process in order to separate the spiked connections. Taking into account that the wafer section is very thin (material thickness smaller than 150 μm and preferably in the range below 50 μm) in preferred embodiments of the invention, it can be seen that the risk of damage to the wafer section is less in the new method. Moreover, the separators lie on the lateral periphery of the wafer section, which may be some distance from the sensitive circuit structures in the wafer section. On the other hand, in the case of the known method, the disconnected points are broken directly below the sensitive circuit structures.

p0019With the present invention, therefore, the risk that the wafer portion is damaged during dicing can be significantly reduced. Moreover, the singulation in preferred embodiments can be carried out in a very cost-effective manner with known devices which are used for the handling and assembly of SMD devices (surface mounted devices).

p0020In addition, the novel method has the advantage that the remaining semiconductor wafer can be re-used for the fabrication of integrated circuits by abrading the remaining stegrest on the first surface. This makes optimum use of the semiconductor wafer. The cost of manufacturing thin integrated circuits can be reduced.

p0021Finally, the new method has the advantage that the underside of the wafer sections is at least largely free of fracture points and artifacts, whereby the wafer section or the chip can be processed more easily and precisely, for example when stacking up a 3D chip or arranging On a thin film.

p0022The realization of the novel method with a closed cavity has the advantage that the semiconductor wafer can be stored in stock in spite of cavity (or with a plurality of such cavities for a plurality of such wafer sections), whereby the production process can be further rationalized and made even more cost-effective.

p0023Preferably, the cover layer covers the entire surface of the semiconductor wafer so that the semiconductor wafer is hardly distinguishable from the outside from a semiconductor wafer without cavities.

p0024With this embodiment, suitable wafer cavities can be produced very cost-effectively. This embodiment is therefore particularly advantageous for mass production of integrated circuits.

p0025Overall, the new process thus enables a cost-effective and high-quality production of thin integrated circuits. The object mentioned at the outset is thus completely solved.

p0026As already mentioned, in a preferred embodiment of the method, the spotty connections are broken up with the aid of a pressure from above on the first surface. As an alternative or as a supplement to this, the splayed connections can also be broken with the aid of a torsion movement.

p0027This embodiment allows the handling of the wafer sections with the aid of gripping tools, as are also used for handling SMD components. This makes a particularly cost-effective and rational production of thin chips possible.

p0028In a further embodiment, each porous region is produced with a large pore lower layer and a fine pore upper layer.

p0029The penetration depth and the pore size of the layers can be varied during the production of the porous regions, for example, by varying the current density of a current flowing through a solution of hydrofluoric acid and ethanol in which the substrate wafer of single-crystal silicon is arranged as an anode (cf. Mentioned publication by Yonehara / Sakaguchi). By producing a large pore lower layer and a fine pore upper layer, the wafer cavity can be closed more easily upwards. A large-pore lower layer ensures that the wafer section "floats" as freely as possible above the remaining wafer material. The larger the pore size here, the less is the wafer section connected to the underlying wafer material.

p0030In a further embodiment, the substrate wafer is heated after producing the porous regions to produce the cover layer.

p0031In this embodiment, the substrate wafer is subjected to a heat treatment (annealing) after the generation of the porous regions. This closes the pores at the top. In addition, the pore size in the lower regions can also be increased. A kind of reflow process takes place, with the aid of which the (preferably fine-pore) material is again transformed into a single-crystal structure at the top. The material required for this purpose comes from the lower, preferably large-pore layer. This embodiment is particularly advantageous in order to produce a suitable cavity in a cost-effective manner.

p0032In a further embodiment, a second semiconductor material is applied to the upper side in order to produce the cover layer. In preferred embodiments of the invention, an epitaxial layer is grown on the uppermost crystalline layer produced by the reflow process just described above the cavity.

p0033This configuration facilitates the later fabrication of the circuit structures in the wafer section because the circuit structures can be produced in a "normal" single-crystal semiconductor material. Therefore, in this embodiment, the new method can be integrated particularly easily into existing production processes.

p0034In a further embodiment, the substrate wafer has a third semiconductor material, preferably a low p-doped semiconductor material (for example silicon), which is arranged under the first semiconductor material (preferably highly p-doped silicon), the porous regions being arranged only in the first semiconductor layer, Semiconductor material.

p0035This embodiment is particularly advantageous in order to obtain a surface which is as flat as possible over the cavities. For the production of the porous layers, it is of advantage to use a highly p-doped silicon. In contrast, fewer highly doped regions are often required for the circuit structure. It is therefore advantageous to apply the already mentioned epitaxial layer on the upper side of the semiconductor wafer. However, different high dopings can cause stresses in the material due to different lattice constants. These voltages may cause the surface of the semiconductor wafer to become wavy. By producing the porous regions in a highly doped layer, which is arranged on a third semiconductor material, one can ensure by appropriate choice of the process parameters that the lattice constants of the materials are better adapted to one another after the production of the porous layer. As a result, stresses and consequent ripples can at least be reduced.

p0036In a further embodiment of the invention, the wafer section is exposed in the first process sequence from the second surface.

p0037In this embodiment, material below the wafer section to be extracted is removed from below, ie from the second surface. This can be done in addition to a cavity under the wafer section. However, this configuration is preferably realized without a cavity under the wafer section. Particularly preferably, this embodiment of the method is implemented with an SOI wafer, wherein the wafer section with the circuit structures is formed in the upper semiconductor layer of the SOI wafer, and the lower material layer (bulk silicon) is etched out before or after the generation of the circuit structures.

p0038This configuration is particularly advantageous in order to obtain a very smooth surface on the underside of the wafer section. Accordingly, this embodiment is particularly suitable for applications which place very high demands on the surface quality of the rear side of the singled chip. However, this embodiment also makes use of the fundamental advantages of the new method, in particular the possibility of separating and further processing the chips using conventional SMD gripping tools.

p0039In a further embodiment, the first process sequence includes the formation of trenches on the first surface of the semiconductor wafer after the circuit structure has been generated in the wafer section.

p0040In this embodiment, the first process sequence can be divided by at least two stages separated in time from one another. This is, for example, the case when the wafer portion is released by means of a cavity which is advantageously produced before the circuit structures are produced in the wafer portion. On the other hand, the trenches according to this embodiment of the method are etched or otherwise produced only after the circuit structure has been produced. However, the present embodiment is also advantageous in the alternative variants of the new method in which a cavity is dispensed with. In general, the embodiment has the advantage that the production of the integrated circuit can be integrated more easily and thus more cost-effectively into existing production processes, since the semiconductor wafer has a (at least largely largely) closed surface during the production of the circuit structures.

p0041In a further embodiment, the wafer section is arranged in the semiconductor wafer in the [100] or the (110) orientation and the spotting connections are arranged at the corners or at the side edges of the wafer section.

p0042Because, in particular, the breaking behavior of semiconductor wafers is different as a function of the position of a fracture edge relative to the crystal lattice, this embodiment can influence the forces required to separate the connections and also the formation of the separation points. With the preferred embodiments, an optimal triggering of the wafer section can be achieved.

p0043It goes without saying that the features mentioned above and the features to be explained below can be used not only in the respective combination indicated but also in other combinations or in a single setting without departing from the scope of the present invention.

p0044Exemplary embodiments of the invention are illustrated in the drawing and are explained in more detail in the following description. Show it:<dl id="dl0001"><dt>FIG</dt><dd>A simplified schematic representation for explaining a first exemplary embodiment of the novel method,</dd><dt>FIG</dt><dd>FIG. 10 is a simplified view for explaining a variant of the method in which a wafer cavity is formed under the wafer portion, and FIG</dd><dt>FIG</dt><dd>4 shows a schematic representation of the singulation of the chips in an exemplary embodiment of the novel method.</dd></dl>

p0045In <figref idrefs="f0001">FIG</figref> A semiconductor wafer is designated with reference numeral 10. The semiconductor wafer 10 has a first surface 12 and an opposing second (lower) surface 14. Beneath the first surface 12, a cavity 16 is arranged so that a wafer section 18 is suspended above the cavity "hanging". As in<figref idrefs="f0001">FIG</figref>), The semiconductor wafer has a plurality of such cavities 16 which are hidden inside the semiconductor material.

p0046In a first exemplary embodiment of the invention, such a semiconductor wafer 10 is provided (<figref idrefs="f0001">FIG</figref>). Subsequently, a circuit structure is produced in a conventional manner in the wafer sections 18 above the cavities 16. The circuit structure is shown in FIG<figref idrefs="f0001">FIG</figref> Is schematically indicated at reference numeral 20. In preferred embodiments, it is in the [100] or [110] direction relative to the crystal lattice of the wafer material. The wafer section 18 with the circuit structure 20 forms a future chip with an integrated circuit, which now has to be removed from the semiconductor wafer 10.

p0047This is done in the exemplary embodiment shown in that a plurality of trenches 22 are etched into the surface 12 of the semiconductor wafer 10, the individual trenches 22 being separated from each other by spike-like regions 24. In the preferred embodiment, the trenches 22 are distributed in a grid-like manner on the surface 12 of the semiconductor wafer 10 and form a pattern of vertical and horizontal trenches. Where a vertical and a horizontal trench 22 meet, a stepped region 24 remains which has not been etched. Four trenches each surround a wafer section 18 with the integrated circuit structure 20. Accordingly, each wafer section 18 is held at its four corners by the grooved connections 24. Alternatively, the wafer sections 18 could also be held over spigot-like connections, which are arranged not at the corners, but, for example, centrally at the side edges of each wafer section 18.

p0048As in <figref idrefs="f0001">1c</figref> , The individual wafer sections 18 can be broken out of the grid grid of the trenches 22, thus providing chips 26 with an integrated semiconductor structure.

p0049<figref idrefs="f0001">FIG</figref> 10 shows a preferred exemplary embodiment for a semiconductor wafer 10 according to FIG <figref idrefs="f0001">FIG</figref> Respectively. According to<figref idrefs="f0001">FIG</figref> A substrate wafer 32, which consists, for example, of single-crystalline, weakly p-doped silicon is provided. According to<figref idrefs="f0001">FIG. 2b</figref> The substrate wafer 32 is provided with a photomask 34 and exposed. The photomask 34 covers the surface of the substrate wafer 32 only partially, and the open locations can be processed in a known manner.

p0050In the exemplary embodiment shown, the substrate wafer 32 is p-doped through the mask 34 to obtain a high-p-doped semiconductor region 36. The underlying substrate material 32 'furthermore has only a lower p-type doping.

p0051According to <figref idrefs="f0001">FIG. 2c</figref> Porous layers 38, 40 are subsequently formed in the highly doped semiconductor material 36. For this purpose, in a preferred embodiment, the substrate wafer is placed as an anode in a solution of hydrofluoric acid and ethanol so that a current can flow through the solution to the substrate wafer. This forms porous silicon in the region of the highly doped semiconductor material 36, wherein the pore size can be varied by varying the current density. In the preferred embodiment, a fine pore layer 38 is formed on the surface of the substrate wafer and a large pore layer 40 is formed thereunder. A more detailed description of the preparation of these layers is given in the Yonehara / Sakaguchi publication, which is incorporated herein by reference.

p0052According to <figref idrefs="f0001">2d</figref> The photomask 34 is subsequently removed and the wafer 32 "is exposed to a heat treatment with the porous layers 38, 40. As a result, the pores in the upper fine-pore layer 38 at least partially close again and the upper layer 38 is re-immersed Largely uniform, monocrystalline layer 42, under which the large-pore layer 40 'is located, the pore size of which is still larger, and the large-pore layer 40 now forms the cavity, which in FIG <figref idrefs="f0001">FIG</figref> With reference numeral 16. Within this cavity, still separated webs (not shown here) can be left which connect the upper layer 42 to the underlying substrate material 32 ''. However, such webs are the result of process fluctuations and practical shortcomings in the production of the cavity Wafer section 18<figref idrefs="f0001">FIG</figref> Primarily by the webs 24 which remain laterally adjacent to the cavity 16 and which have remained on the basis of the mask structure 34.

p0053According to <figref idrefs="f0001">2f</figref> A further layer 44 is applied as a cover layer to the surface of the substrate material 32 " 'In a preferred exemplary embodiment, this is an epitaxial layer made of monocrystalline, moderately p-doped silicon, which is deposited on the layer 42 or on the entire surface Of the semiconductor wafer, thus obtaining a semiconductor wafer 10 which is suitable for the process steps according to FIG <figref idrefs="f0001">FIG</figref> As starting material.

p0054As from the summary of the <figref idrefs="f0001">1 and 2</figref> The lateral surface expansion of the porous layers 38, 40 corresponds approximately to the lateral surface expansion of the cavity 16 and, to this extent, also approximately to the lateral surface expansion of the wafer section 18 in which the circuit structure 22 is produced. The lateral area expansion of the porous layers 38, 40 also determines the chip area of ​​the subsequent chip 26.

p0055<figref idrefs="f0002">FIG</figref> Shows a preferred exemplary embodiment for separating the chips 26. The individual chips are then detected by means of a gripping tool 50 which sucks the chips 26 (more precisely the wafer sections 18, which still hang on the star-shaped connections 24) with vacuum. By pressure from above (arrow 52), the oblique connections 24 are broken by pressing the individual chip 26 downwards into the cavity. Subsequently, the chip 26 can be removed with the gripping tool 50 upwards and further processed. Alternatively or additionally, the chips 26 can also be broken out of the wafer 10 by tensile forces and / or torsional forces.

p0056To the advantages of the <figref idrefs="f0001">FIGS. 1 and 2</figref> It is necessary that the remaining semiconductor wafer 10 can be recycled after the removal of all the chips 26. For this purpose, the semiconductor wafer 10 is connected to the remaining web regions 24 (<figref idrefs="f0002">FIG</figref>) Is ground and polished at its top, as shown in FIG <figref idrefs="f0002">3e</figref> Is symbolically represented at reference numeral 54. This results in a (somewhat thinner) substrate wafer 32, which again rejects the process sequence<figref idrefs="f0001">FIG</figref> Can be subjected.

p0057As in <figref idrefs="f0002">FIG</figref> , The gripping tool 50 grasps the individual chips 26 to a large extent. The gripping tool 50 is approximately the same as the lateral surface extent of the chip 26 in the region of its lower gripping surface 56. As a result, the gripping tool 50 can hold the sensitive chips 26 securely. The risk of damage when breaking out from the semiconductor wafer 10 is further minimized.