Time multiplexed bidirectional bus

0001The present disclosure relates generally to data bus systems, and more specifically to utilizing time division multiplexing on a bidirectional data bus to reduce operating costs, system complexity, increase bus utilization, reduce noise, and/or to combine two or more data buses into one.

0002Bi-directional data buses are utilized by computing systems to transfer data and/or power among interconnected components (or "cards"). In a unidirectional bus system, typically only one device transmits data while the other devices receive data. In contrast, multiple devices may transmit and/or receive data in a bidirectional bus system. Bus addressing is used so that each receiving device knows whether or not the data being transmitted is intended for that device. The advantage of utilizing a bus rather than some other topology is because buses generally follow the design concept of allowing multiple devices to utilize the same physical medium, e.g., electrical wires. The device or devices that are utilized to transfer data are sometimes referred to as a datalink. A datalink may include one or more buses and/or a bus may be considered a type of datalink. A bus may include one or more wires that may be etched onto a PCB board. Most data bus systems utilize "standards" that may include specifications for connectors, frequency ranges, digital modulation techniques, collision avoidance algorithms, collision detection algorithms, and other features that comply with the standard. Utilization of a standard enables multiple manufactures to design competing and non-competing cards that may easily be connected to a bus via the standardized connector. As long as each of the cards connected to the bus comply with the standard, interoperability between the cards should exist.

0003Occasionally, certain aspects of a standard are not adopted and/or implemented. For example, if a manufacture wanted to utilize widely available integrated circuit devices following a bus standard but wanted to exclude using any connectors perhaps due to space constraints, the manufacture can utilize the bus standard only to the extent needed for their product. In this scenario, only a customized wire connection used in conjunction with the integrated circuit interface device is necessary. Using this approach can save development, manufacturing, and/or device costs because of the use of widely available integrated circuit interface devices, e.g., an integrated circuit bus transceiver.

0004However, this approach is not without limitations. For example, if space limitations inherent in the design prevented the use of the standardized connectors, finding other ways of connecting multiple devices to the bus may be necessary. Also, a situation may occur in which multiple datalinks are necessary to the product so as to provide all of the desired features. To that end, multiple datalinks may add unwanted complexity to a product because of the additional components needed. Also, having multiple datalinks in close proximity to each other may increase the likelihood of cross-talk because of undesired capacitive, inductive, or conductive coupling that can occur between one datalink to another. To mitigate the likelihood of cross-talk, additional grounding and/or shielding may be needed either between the two datalinks or between the datalink and free space. Furthermore, because government regulations limit the amount of electromagnetic energy a device may transmit, including multiple datalinks, this further increases the need for shielding and/or additional grounding. These and other aspects, such as increased power and increased heat, have created the need to limit the number of datalinks and/or buses that a device or system includes. Thus, there exists a need to enable the combining of two bi-directional buses without the above mentioned disadvantages.

0005According to a first aspect of the invention, a system comprises a datalink interface component configured to interface with a datalink and operate in at least one of a first data communication state, a second data communication state, and a wholly inactive state, wherein the first data communication state causes a first data communication component to communicate via the datalink interface and a second data communication component to be in an inactive state, wherein the second data communication state causes the first data communication component to exist in an inactive state and the second communication component to communicate via the datalink interface, and wherein the wholly inactive state causes the first and second data communication components to exist in the inactive state.

0006According to a second aspect of the invention, a method for time-multiplexing first and second bidirectional data communication components for a data bus comprises: <ul id="ul0001" list-style="none"><li>providing a datalink;</li><li>providing a clock signal for utilization by a datalink interface component, wherein the datalink interface component operatively connects to the datalink, wherein the datalink interface component operates in at least one of a first data communication state, a second data communication state, and a wholly inactive state;</li><li>partitioning the clock signal into at least three clock cycles;</li><li>transmitting data via the datalink from the first data communication component during the first data communication state, wherein the first data communication state exists during one of the at least three clock cycles;</li><li>transmitting data via the datalink from the second data communication component during the second data communication state, wherein the second data communication state exists during one of the at least three clock cycles; and</li><li>tri-stating the first and second data communication components during the wholly inactive state, wherein the wholly inactive state exists during one of the at least three clock cycles between that of the first and second data communication states.</li></ul>

0007According to aspects of the present disclosure, there is provided a system, and method thereof, for providing bidirectional communication for a datalink by time division multiplexing a bidirectional data bus that allows for a reduced number of pin connections and minimizes noisy environments and crosstalk associated with utilizing multiple buses, e.g., externally induced electrical noise and/or signal reflections due to mis-terminated transmission lines. Alternatively, the present disclosure may be viewed as a method for combining two or more bidirectional data buses into a single time multiplexed bidirectional bus interface to support continuous data streaming for the two or more data buses using time division multiplexing ("TDM"). As is well known in the art, TDM is a type of multiplexing in which two or more signals are transferred simultaneously as sub-channels in one communication channel, but physically are taking turns on the channel.

0008Some examples of systems according to the invention will now be described with reference to the accompanying drawings, in which:-

0009<figref idref="f0001"><b>FIG. 1</b></figref> is a block diagram of a system including a time multiplexed bidirectional data bus according to embodiments of the present disclosure;

0010<figref idref="f0002"><b>FIG. 2</b></figref> is a state diagram representing the operation of the time multiplexed bidirectional bus in accordance with the present disclosure; and

0011<figref idref="f0003"><b>FIG. 3</b></figref> is a timing diagram illustrating a functional simulation of the present disclosure.

0012The present disclosure provides a system for providing bidirectional communication for a datalink utilizing a time multiplexed bidirectional data bus that allows for a reduced number of pin connections and minimizes noisy environments and crosstalk associated with utilizing multiple buses, e.g., externally induced electrical noise and/or signal reflections due to mis-terminated transmission lines. Alternatively, the present disclosure may be viewed as a method for combining two or more bidirectional data buses into a single time multiplexed bidirectional bus interface to support continuous data streaming for the two or more data buses using time division multiplexing ("TDM"). As is well known in the art, TDM is a type of multiplexing in which two or more signals are transferred simultaneously as sub-channels in one communication channel, but physically are taking turns on the channel.

0013In embodiments of the present disclosure, two bidirectional busses <b>A</b> and <b>B are</b> combined into a single bus interface system <b>100</b> that represents a combination of data buses <b>A</b> and <b>B,</b> as shown in <figref idref="f0001"><b>FIG. 1</b></figref><b>.</b> System <b>100</b> may further include a single set of connector pins and grounds (not shown) to support continuous streaming of data through a datalink <b>110.</b> In accordance with the present disclosure, continuous streaming of data through datalink <b>110</b> may be accomplished by combining two bidirectional busses, such as bus <b>A</b> and bus <b>B,</b> and partitioning the data cycle of system <b>100</b> into a plurality of time slots or clock cycles utilizing TDM.

0014For example, <figref idref="f0003"><b>FIG. 3</b></figref> depicts a timing diagram <b>300</b> which illustrates an exemplary data cycle sequence resulting from a functional simulation of the system <b>100</b> of <figref idref="f0001"><b>FIG. 1</b></figref><b>.</b> In the present example, the data cycle of system <b>100</b> is partitioned into four parts, wherein a sequence of four timeslots or clock cycles is multiplexed. A first timeslot₁ and third timeslot₃ are allocated for bus <b>A</b> and bus B, respectively, to communicate data through system <b>100.</b> A second timeslot₂ and fourth timeslot₄ are allocated for wholly inactive states between first timeslot₁ and third timeslot₃ to allow sufficient time for bus settling and accommodation of bidirectional data flow, as would be understood in the art.

0015As to be appreciated, wholly inactive states in the data cycle of system <b>100</b> are commonly referred to as "tri-states" and may be a result, for example, of all I/O pins (not shown) of system <b>100</b> existing in a high impedance state during a specific timeslot<b>_n</b> or clock cycle. In use, for example, inactivity of bus <b>B</b> during timeslot₂ allows bus <b>A</b> sufficient time in which to tri-state system <b>100</b> following timeslot₁ during which bus <b>A</b> is communicating data. It should be appreciated that timing diagram <b>300</b> is illustrative only and other techniques to achieve continuous data streaming of bus <b>A</b> and bus <b>B</b> may be utilized to produce functional simulation results different from illustrated in <figref idref="f0003"><b>FIG. 3</b></figref> and are contemplated by the scope of the present disclosure.

0016Referring now to the drawings, <figref idref="f0001"><b>FIG. 1</b></figref> illustrates a block diagram of a system <b>100</b> providing a time multiplexed bidirectional data bus according to embodiments of the present disclosure. Data communication components <b>102</b> and <b>104</b> form bidirectional bus <b>A,</b> depicted as <b>A₁</b> and <b>A₂</b> respectively, and bus interface components <b>106</b> and <b>108</b> form bidirectional bus <b>B,</b> depicted as <b>B₁</b> and <b>B₂</b> respectively. Each of data communication components <b>102-108</b> may be, for example, an integrated circuit, a set of transistors, a microcontroller, a microprocessor or the like.

0017In addition or alternatively, any one of data communication components <b>102-108</b> may be, for example, a programmable logic device such as a Complex Logic Programmable Device (CLPD), a Field Programmable Gate Array (FPGA), and/or programmable array logic (PAL). Each of data communication components <b>102-108</b> may, for example, utilize software to assist in the TDM stored in RAM, ROM, EEPROM or other data and/or instruction retaining devices including devices that provide volatile and/or non-volatile memory storage. For example, software may be used to program the devices to recognize the present state of system <b>100</b> and instruct the device to respond accordingly.

0018With continued reference to <figref idref="f0001"><b>FIG. 1</b></figref><b>,</b> a first datalink interface component <b>112</b> and a second datalink interface <b>114</b> are configured to enable operative communication via datalink <b>110.</b> In use, datalink interface component <b>112</b> enables operative communication via datalink <b>110</b> between data communication components <b>102</b> and <b>104</b> and similarly, datalink interface component <b>114</b> enables operative communication between data communication components <b>106</b> and <b>108.</b> Datalink <b>110</b> may be any technology capable of communicating digital data, for example, a backplane providing digital communications between multiple devices such as data communication components <b>102-108.</b> For example, datalink <b>110</b> may be a VME backplane providing digital communications between components connected to datalink <b>110.</b>

0019In use, datalink interface component <b>112</b> enables data communication components <b>102</b> and <b>106</b> (<b>A₁</b> and <b>B₁</b>) to operatively connect to datalink <b>110.</b> Likewise, datalink interface component <b>114</b> enables data communication components <b>104</b> and <b>108</b> (<b>A₂</b> and <b>B₂</b>) to operatively connect to datalink <b>110.</b> As to be appreciated, each of the data communication components <b>102, 104, 106,</b> and <b>108</b> may exist in an inactive state or be tri-stated.

0020For example, data communication components <b>102-108</b> may include hardware that can increase the impedance between any one of data communication components <b>102-108</b> and datalink <b>110</b> to a level at which digital communication between datalink <b>110</b> and the data communication components is restricted. In use under this scenario, datalink interface component <b>112</b> prevents either of data communication components <b>102</b> and <b>106</b> from communicating with datalink <b>110</b> and datalink interface component <b>114</b> prevents either of data communication components <b>104</b> and <b>108</b> from communicating with datalink <b>110.</b> In embodiments, each of data communication components <b>102, 104, 106,</b> and <b>108</b> may provide the necessary hardware and/or software to enable existing in an inactive state or to be tri-stated.

0021Referring now to <figref idref="f0002"><b>FIG. 2</b></figref><b>,</b> a state diagram <b>200</b> is shown illustrating the operation of system <b>100</b> (<figref idref="f0001"><b>FIG. 1</b></figref>). In operation, system <b>100</b> may be in any one of a wholly inactive state <b>204</b> or <b>208</b> or a communication state <b>202</b> or <b>206.</b> System <b>100</b> (<figref idref="f0001"><b>Fig 1</b></figref>) sequentially progress from state <b>202,</b> to state <b>204,</b> to state <b>206,</b> to state <b>208,</b> and finally returns to state <b>202</b> restarting the sequence. When system <b>100</b> is active, the sequence discussed above may continue indefinitely regardless of whether data communications are occurring. A functional simulation of such operation is shown in <figref idref="f0003"><b>FIG. 3</b></figref><b>,</b> illustrating data communications taking place on datalink <b>110</b> in relation to the state of system <b>100</b> of <figref idref="f0001"><b>FIG. 1</b></figref><b>.</b>

0022During wholly inactive state <b>204</b> or <b>208,</b> each of datalink interface components <b>102, 104, 106,</b> and <b>108</b> exist in an inactive state or are tri-stated and, thus, are not able to access and/or transmit data via datalink 110. Referring to <figref idref="f0003"><b>FIG. 3</b></figref><b>,</b> this may be represented, for illustrative purposes, by timeslot₂ or timeslot₄. It should be understood that the inactive state or tri-state condition of datalink interface components <b>102, 104, 106,</b> and <b>108</b> may be due to datalink interface components <b>112</b> and <b>114</b> disconnecting corresponding data communication components. Alternatively and/or additionally, datalink interface components <b>112</b> and <b>114</b> may cause connections between corresponding data communication components to become inactive, thereby resulting in an inactive sate or tri-state condition. In <figref idref="f0003"><b>FIG. 3</b></figref><b>,</b> note that during timeslot₁, bus <b>A,</b> bus <b>B,</b> and datalink <b>110</b> are tri-stated.

0023With reference to <figref idref="f0003"><b>FIG. 3</b></figref> in conjunction with <figref idref="f0002"><b>FIG. 2</b></figref><b>,</b> communication state <b>202</b> initializes the sequence and corresponds to timeslot₁. During timeslot₁, bus <b>A</b> is active, i.e., data communication components <b>202</b> and <b>204</b> are communicating between each other utilizing datalink <b>110,</b> while bus <b>B</b> is inactive or in a tri-stated condition, i.e., data communication components <b>106</b> and <b>108</b> are placed in an inactive state or are tri-stated.

0024During communication state <b>204,</b> data communication components <b>102</b> and <b>104</b> may fully utilize datalink <b>110,</b> which is indicated by the label "data A" in <figref idref="f0003"><b>FIG. 3</b></figref> occupying the datalink portion of the timing diagram indicted by timeslot₁. It should be appreciated that during each of timeslots<b>₁</b> through <b>n</b>, a fixed amount of time is occupied by each of states <b>202, 204, 206,</b> and <b>208.</b> This is an example of one form of TDM. As is typical in the art, the synchronization of system <b>100</b> may be implemented by controlling a clock signal utilizing, for example, either an external clock or internal clock having clock mis-synchronization correction capability.

0025The communication that can occur between data communication components <b>102</b> and <b>104</b> during communication state <b>204</b> may include, but is not limited to, handshaking, packet communications, layered packet protocols and/or additional multiplexing techniques. In use, the communication may utilize asynchronous or synchronous communications and/or parallel or serial communications.

0026Still referring to <figref idref="f0003"><b>FIG. 3</b></figref> in conjunction with <figref idref="f0002"><b>FIG. 2</b></figref><b>,</b> the next state that occurs after the time allocated for timeslot<b>₁</b>, is wholly inactive state <b>204.</b> Wholly inactive state <b>204</b> corresponds to timeslot₂, in which both bus <b>A</b> and bus <b>B</b> are in an inactive state or tri-stated. This is indicated by timeslot₂, in which each of bus <b>A,</b> bus, <b>B</b> and datalink <b>110</b> are indicated as being in a tri-state condition. As to be appreciated, having a wholly inactive state <b>204</b> prevents collisions from occurring, in which more that one of data communication components <b>202, 204, 206,</b> and <b>208</b> attempt to drive datalink <b>110.</b> Absent wholly inactive states <b>204</b> and <b>208,</b> more than one of data communication components <b>202-208</b> may attempt to drive system <b>100</b> simultaneously, resulting in communication errors.

0027For example, if data communication component <b>102</b> was transmitting to data communication component <b>104</b> and, because of slight deviations of timing of the various components, data communication component <b>108</b> attempted to start "receiving" data from data communication component <b>106,</b> then some of the electrical signal being transmitted by data communication component <b>102</b> may be improperly intercepted by data communication component <b>108,</b> which may not be able to distinguish the origination of the data.

0028Additionally, the circuitry that "drives" datalink <b>110</b> may attempt to drive conflicting voltages. For example, if data communication component <b>102</b> attempted to place "5 volts" (corresponding to a "I") on a particular wire of datalink <b>110,</b> and data communication component <b>106</b> attempted to "ground" (corresponding to a "0") the same wire of datalink <b>110,</b> then data communication component <b>102</b> may increase the current as much as possible while data communication component <b>106</b> would simultaneously attempt to sink as much current as possible. This condition may result in a runaway condition in which components were damaged and/or destroyed. Even if such collisions were detectable, there may be reductions in the utilization of datalink <b>110</b> to compensate for these collisions.

0029Referring again to <figref idref="f0002"><b>FIG. 2</b></figref><b>,</b> communication state <b>206,</b> which corresponds to Timeslot₃ (<figref idref="f0003"><b>FIG. 3</b></figref>), is similar to communication state <b>202,</b> as discussed above, but with bus <b>B</b> being active. In use, during timeslot₃ (<figref idref="f0003"><b>FIG. 3</b></figref>) datalink <b>110</b> is being utilized by bus <b>B,</b> i.e., bus <b>B</b> is shown as being in an active state and bus <b>A</b> is shown as being inactive or tri-stated. During timeslot₃, communication between data communication components <b>106</b> and <b>108</b> is operative while data communication components <b>102</b> and <b>104</b> are inactive. During timeslot₃, bidirectional bus communications of bus <b>B</b> can take place and may include any known bidirectional bus communication known in the art.

0030State <b>206</b> is followed in the sequence by wholly inoperative state <b>208</b> as illustrated in state diagram <b>200</b> of <figref idref="f0002"><b>FIG. 2</b></figref><b>.</b> Wholly inoperative state <b>208</b> is similar to wholly inoperative state <b>204,</b> as discussed above, and corresponds to time slot₄ (<figref idref="f0003"><b>FIG. 3</b></figref>) in which all of data communication components <b>102-108</b> are inactive, thus, making datalink <b>110</b> inactive. Again, utilizing wholly inoperative state <b>208</b> prevents collisions and more efficiently utilizes datalink <b>110.</b> After wholly inoperative state <b>208,</b> the data cycle proceeds to communication state <b>202,</b> thereby reinitializing the sequence. The sequence may continue indefinitely.