Microcontroller waveform generation

Description of equivalent WO 2007023456 A2

MICROCONTROLLERWAVEFORM GENERATION

The present invention relates to electronic devices, and more particularly, but not exclusively, relates to generation of waveforms with a microcontroller. There is a frequent desire to generate sequential bit patterns with predictable timing and/or frequency with a microcontroller. Unfortunately, generation of such desired patterns as a direct consequence of Central Processing Unit (CPU) instruction execution is often impractical because of variation in CPU instruction timing, higher priority CPU tasks, asynchronous interrupt servicing, and the like. Indeed, the operating system and other overhead tasks of many microcontroller applications often preclude direct sequential bit pattern generation with the CPU.

Thus, there is an ongoing demand for further contributions in this area of technology.

One embodiment of the present invention is a unique electronic device for generating bit patterns. Other embodiments of the present invention include unique devices, methods, systems, and apparatus to generate waveforms with a microcontroller.

A further embodiment includes providing a microcontroller integrated circuit that has a programmable processor, an embedded memory operatively coupled to the processor, waveform control circuitry operatively coupled to the processor and the memory, and several terminals for coupling to external circuitry. In accordance with programming executed by the processor, a waveform bit pattern is stored in the memory. The waveform circuitry controls synchronous transmission of the waveform bit pattern stored in the memory through one or more of the terminals in accordance with designated timing. During this transmission, an instruction sequence for a different process can be executed by the processor.

Still a further embodiment includes: providing a microcontroller integrated circuit having a programmable processor, an embedded memory, waveform control circuitry, and several input/output pins; executing a first instruction sequence with the processor; initiating transmission of a waveform bit pattern stored in the memory through one or more of the pins and controlling timing of the transmission; and executing a second instruction sequence with the processor during this transmission.

Yet another embodiment is directed to an apparatus comprising: a microcontroller integrated circuit device that includes an embedded memory, waveform control circuitry operatively coupled to the memory, several input/output pins, and a programmable processor. The input/output pins are each structured to be selectively switched between the memory and at least one different embedded device. The processor includes means for executing a first sequence of instructions to store a waveform bit pattern in the embedded memory and designate timing for the waveform bit pattern. The waveform circuitry includes means for controlling synchronous transmission of the waveform bit pattern stored in the memory through one or more of the input/output pins in accordance with the timing while the processor executes a second sequence of instructions to perform a different process. One object of the present invention is to provide a unique electronic device for generating bit patterns.

Another object of the present invention is to provide a unique device, method, system, or apparatus to generate waveforms with a microcontroller.

Further objects, embodiments, forms, features, benefits, and advantages of the present invention shall become apparent from the description and figures included herewith.

Fig. 1 is a diagrammatic view of a electronic device system.

Fig. 2 is a flowchart corresponding to operation of the system of Fig. 1.

While the present invention may be embodied in many different forms, for the purpose of promoting an understanding of the principles of the invention, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended. Any alterations and further modifications in the described embodiments, and any further applications of the principles of the invention as described herein are contemplated as would normally occur to one skilled in the art to which the invention relates.

One embodiment of the present invention is directed to a microcontroller integrated circuit including an embedded memory operatively coupled to the processor, waveform control logic operatively coupled to the memory, and a programmable processor. This processor executes a first process that includes storing a waveform bit pattern in the embedded memory with designated waveform transmission timing. Transmission of the waveform bit pattern from the memory through one or more terminals is performed under control of the waveform logic. The processor executes a different process as the transmission occurs. Fig. 1 depicts another embodiment of the present invention in the form of electronic device system 20. System 20 includes microcontroller integrated circuit 22 that is of a solid state variety and may be manufactured using standard photolithographic techniques. Microcontroller circuit 22 defines microcontroller 24 that includes embedded circuitry operable to perform various microcontroller operations. This circuitry includes processor 30, interrupt control logic 32, input/output configuration registers 34, and other embedded devices 36. Processor 30 is of a programmable type that executes a sequence of instructions of a Complex Instruction Set Computing (CISC) type, a Reduced Instruction Set Computing (RISC) type, or different type as would occur to one skilled in the art. In one form, instructions are stored in memory coupled to processor 30 via a local bus. Such memory can include Static Random Access Memory (SRAM) memory, nonvolatile flash memory, Dynamic Random Access Memory (DRAM), and/or such different type as would occur to those skilled in the art.

Interrupt control logic 32 manages internal and external interrupts associated with microcontroller 24, and may be coupled to processor 30 by an appropriate internal bus.

Devices 36 include any of various standard input devices, output devices, Input/Output (I/O) devices, and/or different dedicated circuit devices. Devices 36 can include one or more timers, real-time clocks, analog-to-digital (AfO) converters, digital-to- analog (D/A) converters, Universal Asynchronous Receiver/Transmitter (UART) interfaces and/or various other serial communication ports, external interrupt pathways, pulse-width modulators, or the like, just to name a few. A high-speed internal bus can be used to couple processor 30 and devices 36 together to provide selective bidirectional communication therebetween. In one variation of this form, the bus is coupled to processor 30 via an interlace bridge (not shown). Philips Semiconductors model LPC2114 and model LPC2124 are nonlimiting examples of microcontroller configurations that include processors, interrupt control logic, I/O and various dedicated embedded devices of a type that could be included in microprocessor circuit 22.

Microcontroller 24 further includes waveform generation circuitry 40. Circuitry 40 includes waveform bit pattern storage memory 42 and waveform control logic circuitry 44 coupled to processor 30 by bus 38. Processor 30 has read/write access to memory 42. Memory 42 can be the same or different than other memory coupled to processor 30 for programming and/or processor data storage, and bus 38 can be the same or different than buses coupled to such processor memory, to interrupt control logic 32, to devices 36, or the like. Waveform logic 44 is operatively coupled to memory 42 to provide control thereof without adding appreciable traffic along bus 38. Waveform logic 44 includes at least one timer 46 that is synchronized to operation of processor 30 in a standard manner. For example, processor 30 and timer 46 can share a common clock and/or different time-base circuitry (not shown). Waveform logic 44 is responsive to input received from processor 30 via bus 38 to control certain aspects of waveform generation based on the pattern information stored in memory 42, as will be described in greater detail in connection with Fig. 2 hereinafter.

Microcontroller 24 also includes several shared input/output pins 48 more specifically designated pins PO, Pl, ... , and PN; where the variable "N" relates to the total N+l number of pins. Each pin 48 is connected to a pin-level logical selection block 50 designated PIN SEL 0, PIN SEL 1, ... , and PIN SEL N in Fig. 1, with the vertical ellipsis of Fig. 1 representing pin P2 through pin PN-I, and block PIN SEL 2 through block PIN SEL PN-I . Reference numerals 50a, 50b, and 50c are also provided referring more specifically to blocks PIN SEL 0, PIN SEL 1 , and PIN SEL N; respectively.

Blocks 50 are each configured to select from among memory 42 and "x" number of pathways from other devices 36, where x is an integer value of at least one. Some, all, or none of the outputs of Block 42 may also be connected directly to the input/output pins. Selection, or "switching between" memory 42 and devices 36 is performed based on a selection bit input value stored in and provided from one of registers 34, as loaded by processor 30. While the arrowhead directions represent outgoing signals from other devices 36, it should be appreciated that one or more of these may be inputs through pins 48 for certain embodiments, where at least a portion of pins 48 are switchable between input and output operation. In one particular, nonlimiting embodiment, some or all of pins 48 are of a general purpose input/output type. Likewise, in other embodiments, some or all of pins 48 can be dedicated only to output. Alternatively or additionally, at least some of "x" number of pathways may be associated with memory or other arrangements besides devices 36 (not shown). Pins 48 correspond to terminals 52 of microcontroller circuit 22 that are more specifically designated terminals 52a, 52b, and 52c in correspondence to pins PO, Pl, and PN. Pins 48 (terminals 52) are arranged to be coupled to circuitry and/or signal pathways external to microcontroller integrated circuit 22.

External to microcontroller circuit 22, bus 60 is coupled to pins 48 and circuit device 62. Bus 60 is also coupled to input data latch 70. Latch 70 is embedded in microcontroller integrated circuit 22. It should be appreciated that latch 70 could be included among devices 36; however, it is shown separately in Fig. 1 to preserve clarity. Furthermore, the input to latch 70 from bus 60 and/or device 62 can be provided via general purpose input/output pins or the like. Latch 70 also receives input from device 62. In one specific arrangement, device 62 includes a memory and bus 60 is utilized to strobe data into latch 70 from this external memory.

Fig. 2 depicts one type of operating procedure 120 for system 20 in flowchart form; where like reference numerals refer to like features previously described. Procedure 120 begins with operation 122. In operation 122, processor 30 executes programming, including a routine with a sequence of instructions that directs generation of a desired waveform over bus 60 through one or more of pins 48 with a desired timing/frequency relationship. Rather than directly generate this waveform from instructions as they are executed by processor 30, waveform generation circuitry 40 is utilized. Specifically, the routine executed by processor 30 directs storage of data in memory 42 via bus 38. This data provides a waveform bit pattern to be transmitted onto bus 60. In one nonlimiting application, this waveform bit pattern is selected to appropriately strobe data into latch 70 from device 62.

From operation 122, procedure 120 continues with operation 124, which further sets-up waveform generation. In operation 124, waveform generation set-up includes storage of selection data in one or more of registers 34 to select memory 42 with blocks 50 as an input source. Correspondingly, output from memory 42 through blocks 50 is provided to bus 60 via selected pins 48 (terminals 52). It should be appreciated, the selection blocks 50 can be used to vary the number of pins 48 receiving input from memory 42 in operation 124. Alternatively, this quantity can be fixed for a given embodiment. From operation 124, operation 126 is performed. In operation 126, waveform logic

44 responds to input from processor 30 to initiate transmission of the waveform bit pattern from memory 42 through pins 48. This input could include one or more commands directing a number of aspects of the transmission, such as frequency or other transmission timing parameters. For example, the transmission could be specified as a "one time only" type or set to repeat. In one embodiment of the repeating type, microcontroller 24 can be arranged with a processor command structure recognized by waveform circuitry 44 that specifies a finite number of repetitions or that repetition be indefinite. Alternatively or additionally, processor 30 and waveform logic 44 can be arranged to provide a variable delay before starting transmission and/or repeating transmission. Waveform logic 44 utilizes timer 46 to control frequency and other timing aspects (if present), such that the waveform bit pattern transmission to bus 60 is synchronous, at least with respect to the operation of processor 30. From operation 126, procedure 120 continues with operations 130 and 140 that at least partially overlap one another in time - typically being performed for the most part concurrently (i.e. in parallel). In operation 130, transmission of the waveform is performed under control of waveform logic 44. In parallel, processor 30 continues to execute a different segment or instruction sequence of the routine in operation 140 that may correspond to a different process or function as the waveform is independently transmitted by circuitry 40. In one particular form, the different process includes or is directed to servicing an interrupt in operation 140 as waveform generation continues in operation 130.

Procedure 120 continues with conditional 145 that tests whether to continue operation. If the test of conditional 145 is true (affirmative), procedure 120 halts. If the test of conditional 145 is false (negative), procedure 120 continues with conditional 150. It should be appreciated that the test of conditional 145 can be software and/or hardware driven such that it may come from the routine being executed by processor 30, or independent of it.

Conditional 150 tests whether to send a different waveform. If the test of conditional 150 is true (affirmative), procedure 120 loops back to operation 122 to store the next bit pattern for generation of a different waveform, and repeats operations 122, 124, 126, 130 and 140 for the new waveform. If the test of conditional 150 is false (negative), procedure 120 proceeds to conditional 160.

Conditional 160 tests whether to terminate waveform transmission. If the test of conditional 160 is true (affirmative), waveform transmission terminates in operation 162. In one embodiment, the waveform transmission termination of operation 150 is performed by waveform logic 44 without iurther input or direction via bus 38 and/or processor 30. In another embodiment, processor 30 provides one or more inputs via bus 38 that cause waveform logic 44 to terminate transmission. From operation 162, procedure 120 returns to conditional 145. If the test of conditional 160 is false (negative), procedure 120 returns to operation 130 and 140. It should appreciated that conditionals 150 and/or 160 could be implemented through programming of processor 30; however, such tests and results may be implemented through hardware input or otherwise as would be known to those skilled in the art.

Many other embodiments of the present application are envisioned. For example, the teachings of the present application can be applied in many different integrated circuit configurations. Another example includes providing an integrated circuit with a programmable processor, memory, waveform logic operatively coupled to the processor and the memory, and several terminals; controlling transmission of the waveform bit pattern stored in the memory through one or more of the terminals in accordance with designated timing; and during this transmission, executing an instruction sequence for a different process with the processor.

Still a further example includes an integrated circuit with a programmable processor, memory operatively coupled to the processor, waveform control circuitry operatively coupled to the processor and memory, and several terminals. The processor includes means for storing a waveform bit pattern in the memory in accordance with a first instruction sequence and executing a second instruction sequence for a different process during transmission of a waveform corresponding to the bit pattern under control of the waveform logic. The waveform logic includes means for controlling transmission of the waveform bit pattern stored in the memory through one or more of the terminals in accordance with desired timing. Any theory, mechanism of operation, proof, or finding stated herein is meant to further enhance understanding of the present invention, and is not intended to limit the present invention in any way to such theory, mechanism of operation, proof, or finding. While the invention has been illustrated and described in detail in the drawings and foregoing description, the same is to be considered as illustrative and not restrictive in character, it being understood that only selected embodiments have been shown and described and that all equivalents, changes, and modifications that come within the spirit of the inventions as defined herein or by the following claims are desired to be protected.