Rotary flash adc

Description of equivalent WO 2006020431 A2

ROTARY FLASH ADC

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to and incorporates by reference Great Britain application GB 0416803, filed July 27, 2004.

This application is related to U.S. Application, titled "DOUBLE FEEDBACK RTWO DRIVEN SAMPLER CIRCUITS", SN 11/051,989, filed Feb. 3, 2005.

The publication, Rotary Traveling- Wave Oscillator Arrays: A New Clock Technology, J. Wood, T.C. Edwards, and S. Lipa, IEEE Journal of Solid-State Circuits, vol. 36, pp. 1654-1665, is incorporated by reference into the present application.

FIELD OF THE INVENTION

The present application relates generally to analog-to-digital converters and more particularly to an analog-to-digital converter with a rotary oscillator.

DESCRIPTION OF THE RELATED ART

At the speeds (in the GHz range) envisaged, only flash ADC architectures have been practical. Flash converters tend to require a large amount of both power and area and are difficult to calibrate.

BRIEF SUMMARY OF THE INVENTION

This invention uses multiphase clocks (preferably rotary clock technology as described in U.S. Patents 6,556,089, 6,816,020, and 6,525,618) to implement a high speed time-to-digital based analog-to-digital converter on top of a self-calibrating single-slope ADC. These new rotary clocked devices promise an order of magnitude less power consumption and the potential to improve resolution by one to three bits.

One embodiment of the present invention is a system for converting an analog signal to a digital signal. The system includes a multiphase oscillator, a sample and hold circuit, an integrator, and a time-to-digital converter. The multiphase oscillator has a period of oscillation and provides a plurality of phase signals, each oscillating at the period of the multiphase oscillator. The sample and hold circuit is operative to capture and hold the analog signal in response to a phase signal of the multiphase oscillator. The integrator converts the held analog signal into a pulse having a duration that is proportional to the magnitude of the analog signal. The time-to-digital converter is operative to convert the pulse into a digital signal and includes a plurality of sampling elements, each activated by the pulse and capturing one of the phases of the multiphase oscillator, and a binary counter for counting the periods of the multiphase oscillator. The plurality of flip-flops and the binary counter provide the digital signal.

Another embodiment of the present invention is a method for converting an analog signal to a digital signal. The method includes (i) sampling and holding the analog signal in response to one of a number of phase signals of a multiphase oscillator, and after holding the analog signal, (ii) creating a first transition of a pulse, (iii) integrating a constant reference current until the hold analog signal has a known voltage value to create a second transition of the pulse, and between the first and second transitions of the pulse, (iv) counting oscillator cycles and capturing the state of the oscillator phase signals, where the count of the oscillator cycles and the captured state of oscillator phase signals become the digital signal.

One advantage of the present invention is that conversion happens very quickly as the conversion time is the sum of the sample time and the time-to-digital conversion time. If the sample time is 500 pS and the time conversion time is equal to the sample time, then a full analog-to-digital conversion would occur in about 1 nS.

Another advantage is that there is no need for a calibration cycle that makes the converter unavailable, hi the present invention, calibration occurs while the converter is operational and does not interfere with normal operation.

Yet another advantage is that the conversion is highly accurate, the accuracy limit being set by the number of phases of the multiphase clock.

BRIEF DESCRIPTION OF THE DRAWINGS These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:

FIG. 1 is the simplified diagram of a sampler and converter technique in accordance with the present invention; FIG. 2 shows an embodiment of a time-to-digital converter system in accordance with the present invention;

FIG. 3 shows an embodiment by which a highly nonlinear line is constructed;

FIG. 4 shows a technique for interleaving and control for transparent self-calibration; and

FIG. 5 shows a tuned power network for high 2F and other harmonic impedance.

DETAILED DESCRIPTION OF THE INVENTION Overall Operating Principle

The basic operating principle is that of single-slope ADC conversion using a track- and-hold sampler on the input and a multiphase time-to-digital conversion on the output. Fragmentation and interleaving of the ADC construction allows for transparent self- calibration while conversions are in progress. FIG. 1 is the simplified diagram of the new sampler and converter technique constructed on a low cost digital CMOS process where only the PFETs have independent wells (NFET circuits could be used on a true twin-tub process). At the front-end is a voltage buffer and a track and hold circuit. An input multiplexer (not a sampler) is provided to allow auto-calibration, etc. The track and hold circuit shown is a PFET source follower and the sampler capacitor is chosen to be a PFET enhancement mode capacitance formed in transistor PHOLD (which also doubles as the comparator transistor). Of course, a true capacitor could be used.

After the sampler, a single-ramp conversion is performed on the sampled voltage by using a current source iramp to slew the unknown voltage up past a threshold detected by a voltage comparator (or in this case just the PFET turning off with a current sink load). This is the well-known single-slope or "time-to-digital" ADC conversion process. This invention features the high resolution, low power method of implementing the time-to-digital conversion. The ramp is very fast compared to the older single-slope ADCs and slews in the order of 1 volt per nanosecond.

The multiphase time-to-digital conversion block uses many of the potentially infinite number of clock phases to determine the exact time the output edge of the comparator transitioned. Because many phases are available, the time resolution can be made very small. With 1 GHz numerical example, 1000 pS, spread over 10 mm of rotary wire, and with a minimum tapping resolution of 1 micron (via size), there are potentially 10,000 phases available, each phase being 0.1 pS apart in time. It will be explained later how an Nx over- speed rotary clock simplifies the number of phases required.

The main blocks for implementing an embodiment of the ADC include a multiplexer, a source follower, a track and hold circuit, and a time-to-digital converter. Multiplexer

A multiplexer ahead of the source follower allows the ADC input to be switched between input signals and various calibration reference signals. This is not the sampler transistor.

Source Follower

This circuit is a standard source follower and is gated on and off using n-type transistor. Transistors nmnx and pshift also affect the operation of the source follower. The input range is approximately 0 v to 0.75 volts on a typical 0.18 u CMOS process @ 1.8 Volt supply. Output is approximately 0.9 volts higher than the input signal level due to Vth of the PFET. As shown, the circuit suffers from non-linearity due to current source non-linearity and the problem of varying VDS over the input range giving further non-linearity and less than unity gain. Many well-known circuit methods exist to offset these effects and are not shown.

Track/Hold

The most noticeable feature is the use of a PFET transistor pchold whose poly gate capacitor acts as the sampling capacitor "chold". This is permissible because the FET is always operating in the enhancement region of operation and the gate is therefore a quality capacitance. Other capacitor types are possible, but are not present on low-cost CMOS. The voltage vfollow tracks the input voltage during the time samp level is high. The gate capacitance of pchold stores this signal by virtue of the gate being grounded through nsamp.

Sampler Transistor

The hold/sample transistor nsamp is configured in an unconventional way. Because it holds the gate of pchold to ground during the signal-track phase of operation, it operates without any significant VDS voltage. This has many advantages and is especially important during the hold phase of operation where the turn-off charge-injection becomes constant, since the drain voltage is zero and independent of input signal. The sampler transistor can connect directly to the rotary clock for a very fast edge rate (several pS) and high stability (low phase noise). An optional charge injection nullification transistor is not shown for clarity.

Transistor nhelp is significantly smaller than nsamp and waveform help makes the rotary clock ring more decoupled from the input signal. The resistor indicates a non-adiabatic tap for this smaller transistor (more likely through a buffer from the clock), which is present to ensure that the main NFET (directly rotary clocked) is switched on with nearly zero Vds (rum off is already guaranteed to be a zero Vds). Since samp comes directly from the rotary clock signal, coupling from drain to gate is to be avoided especially around the locally most sensitive ISF (Impulse Sensitivity Function) point of the oscillator in the rotary clock period.

To make use of the voltage stored on vhold the opposite side of the "chold" capacitance, i.e., vfollow must be referred to some known reference. That is the purpose of transistor pshift, which pulls vfollow to VDD after the sample is completed. hi operation of the track and hold circuit, the input voltage is translated and level- shifted according to the relation, Vhold = VDD - Vin - Vgs (psf).

Ramp Timer/Comparator

Transistor pramp provides a current for turning the sampled voltage into time interval through the equation CV=IT. Vhold ramps towards VDD once samp-delayed goes low.

Charge is taken out of the gate capacitance of pchold (the sampler capacitance) until the gate voltage is no longer able to sustain the drain current imposed by the ncompare current sink path. At this point, the time of which is proportional to the sampled input voltage, vcompare goes negative, indicating the end of the ADC conversion process.

Time-To-Digital Converter

The time-to-digital converter circuit shown in FIG. 2 is similar to the circuits that are currently in use in particle physics where time-to-digital techniques measure the arrival time of signals from particle detectors. Another use of time-to-digital is in time-of- flight measurements for devices like optical range-finders. To measure a time period of a digital signal, the edge of the pulse must be timed. By using a multiphase array of sampling elements (typically D flip-flops) with each data input driven by a different phase of a multiphase clock and the clock of all FFs driven by the input pulse, it is possible to determine the time (or clock phase) at which the edge occurred to a high sensitivity, at least more sensitive than counting integer clock counts. The time-to-digital converter for use in this ADC application uses a rotary clock loop which has an infinite number of phases available thereby, in principle, giving infinite time resolution for the converter. The output is a bargraph or thermometer code representing the digitized result. Practically speaking, the limits are given by the rise and fall times achievable on the rotary clock and on the vcompare signal. Extremely rapid rise and fall times are needed to allow the sampling elements (in this case D-type flip-flops) to come to an unambiguous decision as to the captured logic state. Ultimately, the metastability resolves itself, but unless the edges are defined sharply, the thermometer code may have "bubbles" and could be non¬ monotonic. Taps on the rotary clock need not be linearly spaced and could advantageously be made at non-linear consecutive phase tappings. This can account for any known non-linearity of the transfer function of Vin→time out.

The circuit shown in FIG. 2 uses standard flip-flops but optimized flip-flops that take advantage of the non-overlapping clocks can resolve smaller time differences.

Non-Linear Transmission Line (NLTL)

One well-known method of increasing the sharpness of an edge beyond the capability of the CMOS inverter rise time (the fastest conventional component in a CMOS process) is the use of a non-linear transmission line.

In FIG. 3, a method of constructing a highly non-linear line is shown. During passage of a pulse edge, the capacitance seen by the transmission line pulse drops sharply as the line passes (VDD- Vth) of the NFET, at which point the gate oxide capacitance becomes disconnected and only the depletion capacitance is seen. This means the lines operate in a shock-wave mode and can achieve sub-picosecond rise times. VDD can be changed to change the onset of non-linear behavior and control the edge rate.

For sharpening of the vcompare pulse, an artificial NLTL is created which can feed into a conventional CPW line to drive the sampler elements. Note that the closing velocity of the vcompare and rotary clock pulses is now important when the vcompare is distributed as a transmission-line. Typically, because of loadings, the CPW is much faster than the RTWO speed.

Self-Calibration Requirements/Technique CMOS circuits have well-known problems with low noise operation especially at low power levels and especially with 1/f low frequency noise. To obtain high accuracy at low power consumption on CMOS requires some kind of calibration scheme that can correct for low frequency drift in the components. Usually, calibration of ADCs is performed at power- up prior to operation, when the ADC input is able to be switched between various known reference voltages and the results are recorded be a control circuit. By applying various digitally-controlled feedback to the internal components of the ADC, a closed-loop self- correction scheme can overcome most of the initial imperfections of ADC construction due to process variation.

Fragmentation And Interleaving

FIG. 4 shows an alternative self-calibration system is proposed here for the ADC. The self-calibration system operates at all times and can therefore correct for low frequency 1/f noise and for supply and temperature variation.

The system is a response to two observations. First, it is observed that the sizes of transistors and capacitors used in an ADC circuit are determined mainly by noise requirements. For example, the sampling capacitor must be large enough for the kT/q sampling noise to be below 1 LSB, where k is the Boltzmann constant, T is the absolute temperature, and q is a standard charge. Another example is the sizing of the source-follower transistor which is determined by the noise contribution of the transistor. Larger devices exhibit less noise simply because of the averaging effect of the larger channel.

Second, it is observed that sizing on CMOS layouts is achieved for each transistor by paralleling multiple "stripes" of transistors together to make up the required channel width. Each stripe is identical to the other stripes. Similarly, with capacitors and resistors, a predefined layout is repeated and paralelled together.

In this embodiment, the ADC is made up of multiple identical fragments which would ordinarily be wired in parallel to make up the sizing. These "undersized" (for noise at least) ADC circuits fragments when in parallel form a low noise ADC. The parallelization of fragments is made "soft" and can be controlled by a sequencer that connects the fragments together at multiple electrical points using Mosfet switches. When connected together, averaging of the circuit voltages and currents occur and noise is reduced in the usual way. In a typical array of 10 fragments, 9 fragments are operated in low-noise parallel mode, while one fragment is self calibrating, either with input = zero or input = maximum (or intermediate points for multipoint slope correction - not described ). The selected calibration fragments are sequenced in turn so that over many complete ADC cycles, all fragments are passed through the zero and full scale calibration cycles. This is transparent to the overall external operation of the converter. On any given ADC conversion, 9 converter fragments form the result, reducing the noise. The overhead is therefore quite small.

Description Of The Fragmentation Diagram

A controller circuit is clocked by the rotary clock and contains a simple state machine to sequence the fragments as outlined above.

If fragment 0 is to be trimmed, output Join_A becomes 0 and Join_B..H are active high to parallel fragments B.. H and these units work together in parallel, noise-averaging mode to do the conversion.

Fragment A can self-correct for min or max range input reference. If the min- voltage is to be auto trimmed, trimsel is high and cal0_A is high, cahmax_A is low, as are mux_A and cal0_B...cal0_H and calmax_B...calmax_H. Signals muxθ...2 are at code 0. All the converter fragments go through their sample and hold and monostable analog→pulse width. Fragment A in this case has its time output compared with the rotary clock phase which corresponds to the zero ADC code. A standard edge-triggered PFD (phase frequency detector) is used and the charge pump output is routed to the trimAjrefO node. The state machine ensures that similar self-correction occurs for full-scale reference input with output to trimA refmax (a charge integration node) at the appropriate later time slot (alternating with zero trims) and compares with the Max tap rotary clock phase at the PFD.

The state machine moves through all the fragments and operates for zero and max analog reference voltages. This occurs at such a fast rate that there is effectively a servo feedback system trimming the gain and offset of all ADC fragments independently. This eliminates the low frequency 1/f noise and temperature and process drift of the converter. Because all the fragments are servo 'ed to the same reference points, then, during the joining/parallelization of the fragments, there are only small differences in nominal signal levels except for the high-frequency (on the order of many cycles periodicity) changes which the parallelization averages out.

Note that rotary tapmax and rotary tapO are shown for the simplistic multiphase rotary clock and need to be augmented with logic to work with the multiple-rotation time circuits which use MSB counters.

Low Noise Rotary Clock

ADCs require the lowest possible jitter in the sampling clocks. Jitter is analogous to phase noise, hi a paper in IEEE JSSC, titled "A Filtering Technique to Lower LC Oscillator", Emad Hegazi, et al. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001. pp 1921-1930, Hegazi finds that, by eliminating power energy to a resonant circuit at even harmonics (particularly the 2nd harmonic), phase noise (and consequently jitter) can be greatly reduced. One option is to add LC resonant circuits at each of the back-back inverters in the power rails, but the area overhead of this approach would be prohibitive and the LC circuit would only be responsive at one harmonic.

Because rotary clocks are not resonant in the conventional sense, a rotationally equivalent power sourcing network with the appropriate frequency selectivity is required.

FIG. 5 shows how this can be achieved. A ring structure is formed for the Vplus and Vneg power supply wires that supply the back-to-back inverters of the rotary clock circuit with power. Inductance is part of the wire characteristic and the capacitance is added to tune the power line to match the rotary clock time (adjusted for the 2F vs. IF frequency difference).

The closed electromagnetic path of the power network is frequency selective. For example, in the two-wire non-Mobius version of the power network, when a supply demand occurs by one of the back-to-back inverters (the switching elements that maintain the traveling wave) at one instant in time to top up the edge of a clock wave traveling in the independent RTWO loop, the inverters cause a voltage dip in the local vplus, vneg levels (where the magnitude determined by the current and 1/2 of the impedance of the power transmission line). This dip propagates around the power supply loop at the characteristic velocity arriving back at the same location in one rotation time of the power loop (which should be set to be twice as fast as the rotary clock time constant). Assuming this rotation time could be made to be 1/2 * (1/Fclock), then the power network is unable to supply power at 2x the rotary clock frequency, thereby achieving the effect desired in the Hagazi reference. This effect applies to all switching elements (such as back-to-back inverters) tapped onto the power loop because of rotational positional and time domain symmetry of the lines. Unlike LC resonant circuits, the rotational circuits are responsive to multiple harmonics.

For maximum impulse-sensitivity function (ISF) immunity, the two rotational operating speeds of Rotary Loop and Power Network can be designed slightly offset from simple multiples. This can promote the 'top-up' of energy at the minimum ISF sensitivity point.

There are two options for constructing the power supply transmission line loop. Mobius and non-Mobius are both shown. The Mobius version uses large coupling capacitors to induce a signal inversion for AC signals on the loop (DC levels un-affected). This configuration doubles the electrical length of the line for purposes of analyzing the time of flights and might be useful to reduce the amount c loading.

Note that the signals vplus and vneg are not identical at all points of the ring because of the rotating currents and voltages on the line.

Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred versions contained herein.