Method for forming a semiconductor memory device with a recessed gate
Abstract
Method for forming a semiconductor memory device with a recessed gate. A substrate (208), having a plurality of deep trench capacitors (206) therein, is provided wherein upper portions of the deep trench capacitor devices are revealed. Spacers (226) on sidewalls of the upper portions of the deep trench capacitors are formed to form a predetermined region surrounded by the deep trench capacitor devices. The predetermined region of the substrate is etched using the spacers and the upper portions of the deep trench capacitors serve as a mask to form a recess (228), and a recessed gate (230,232) is formed in the recess.

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Every citation, both ways
| Document | Relation | Office | Category | Cited during | Relevant claims |
|---|---|---|---|---|---|
| US2001044189A1 | Cites | United States of America | XY | Search report | 1-11,13-16 |
| US2005079661A1 | Cites | United States of America | A | Search report | 1-16 |
| US6037194A | Cites | United States of America | A | Search report | 1-16 |
| US6190971B1 | Cites | United States of America | XY | Search report | 1-11,13-16 |
| US6236079B1 | Cites | United States of America | Y | Search report | 12 |
| US6844591B1 | Cites | United States of America | A | Search report | 1-16 |
39 members in 6 offices; this record represents the family
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 141656 | United States of America | – | |
| 14165605 | United States of America | A |
Members39
| Document | Office | Kind | |
|---|---|---|---|
| US2006270149A1 | United States of America | A1 | |
| US2006270150A1 | United States of America | A1 | |
| US2006270151A1 | United States of America | A1 | |
| TW200642043A | Taiwan Province of China | A | |
| KR20060124597A | Republic of Korea | A | |
| CN1873948A | China | A | |
| EP1729338A2 | European Patent Office (EPO) | A2 | |
| CN1877813A | China | A | |
| CN1877814A | China | A | |
| EP1732124A2 | European Patent Office (EPO) | A2 | |
| EP1732125A2 | European Patent Office (EPO) | A2 | |
| KR20060127746A | Republic of Korea | A | |
| KR20060127747A | Republic of Korea | A | |
| JP2006339648A | Japan | A | |
| TW200644174A | Taiwan Province of China | A | |
| TW200644175A | Taiwan Province of China | A | |
| JP2006344962A | Japan | A | |
| JP2006344963A | Japan | A | |
| KR100740949B1 | Republic of Korea | B1 | |
| KR100740952B1 | Republic of Korea | B1 | |
| KR100749035B1 | Republic of Korea | B1 | |
| US7316952B2 | United States of America | B2 | |
| US7316953B2 | United States of America | B2 | |
| CN100388464C | China | C | |
| CN100388465C | China | C | |
| CN100407405C | China | C | |
| TWI300973B | Taiwan Province of China | B | |
| TWI300974B | Taiwan Province of China | B | |
| US7429509B2 | United States of America | B2 | |
| TWI302363B | Taiwan Province of China | B | |
| EP1729338A3This record | European Patent Office (EPO) | A3 | |
| EP1732124A3 | European Patent Office (EPO) | A3 | |
| EP1732125A3 | European Patent Office (EPO) | A3 | |
| JP4362127B2 | Japan | B2 | |
| JP4362128B2 | Japan | B2 | |
| JP4427037B2 | Japan | B2 | |
| EP1732125B1 | European Patent Office (EPO) | B1 | |
| EP1729338B1 | European Patent Office (EPO) | B1 | |
| EP1732124B1 | European Patent Office (EPO) | B1 |
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Numbers
- Publication
- 1729338
- Application
- 60100914
Titles3
- German
- Verfahren zur Herstellung einer Halbleiterspeichervorrichtung mit einem versenkten Gate
- English
- Method for forming a semiconductor memory device with a recessed gate
- French
- Procédé de fabrication d'un dispositif de mémoire semiconducteur avec porte encastrée
Classification
- CPC, 5
- H10B12/053
- H10P10/00
- H10B12/34
- H10B12/37
- H10B12/488
- IPC, 4
- H01L21 8242
- H01L27 108
- H10D30 01
- H10B12 00
Designated states2
- Contracting states, 1
- Türkiye
- Extension states, 1
- Yugoslavia, later Serbia and Montenegro (until 2006)