Circuit for controlling parameter of an electrical signal

description

Circuit and method for correcting the duty cycle value of a digital data signal

The invention relates to a circuit and to a method for correcting the duty cycle value Dc of a digital data signal. Below a duty cycle value Dc, the ratio between the bit length t_bit ("High") of a "high" signal and the bit length t_bit ("Low") understood a "low" signal. It therefore applies:<maths id="math0001" num=""><math display="block"><mrow><mi mathvariant="normal">Dc</mi><mo>=</mo><mfrac><mrow><msub><mrow><mi mathvariant="italic">t</mi></mrow><mrow><mi mathvariant="italic">bit</mi></mrow></msub><mo mathvariant="italic">(</mo><mi mathvariant="italic">high</mi><mo mathvariant="italic">)</mo></mrow><mrow><msub><mrow><mi mathvariant="italic">t</mi></mrow><mrow><mi mathvariant="italic">bit</mi></mrow></msub><mo mathvariant="italic">(</mo><mi mathvariant="italic">high</mi><mo mathvariant="italic">)</mo><mo mathvariant="italic">+</mo><msub><mrow><mi mathvariant="italic">t</mi></mrow><mrow><mi mathvariant="italic">bit</mi></mrow></msub><mo mathvariant="italic">(</mo><mi mathvariant="italic">low</mi><mo mathvariant="italic">)</mo></mrow></mfrac><mn>,</mn></mrow></math><img file="EP1633043A2_D0001.tif" /></maths>

State of the art:

From the document "CMOS Digital Duty Cycle Correction Circuit For Multi-Phase Clock" (Y. C. Jang, S. J. Bae, H. J. Park; "Electronics Letters" 18. September 2003, vol. 39, no. 19, pages 1383 to 1384) is a circuit for correcting the duty cycle of a digital data signal known. The prior art circuit includes a duty cycle corrector having a rising edge generator and a falling edge generator. The edge drop detector is preceded by a controllable phase shifter, which can be controlled by means of a control signal. The controllable phase shifter is driven by a duty cycle detector, which measures the duty cycle value of the data signal at the signal output of the duty cycle correction device and transmits such a control signal to the controllable phase shifter that a predetermined duty cycle value from the data signal is achieved at the signal output of the duty cycle correction device.

The duty-cycle detector of the previously known circuit has two current integrators, which are connected in parallel. At the output of the two current integrators, a comparator is connected to which a digital counter is connected downstream. The two current integrators are analog components.

Object of the invention:

Based on the known prior art, it is an object of the invention to provide a circuit or a method for correcting the duty cycle value of a digital data signal. The circuit and the method should be insensitive to noise and work reliably with very small signal levels.

Summary of the invention:

This object is achieved by a circuit having a duty cycle correction device and a duty cycle detector. The duty cycle detector controls the duty cycle correction device with a control signal such that the digital data signal at the signal output of the duty cycle correction device reaches a predetermined duty cycle value. According to the invention, the duty cycle detector for forming the control signal has a digital integrator.

An essential advantage of the circuit according to the invention is that it is particularly resistant to interference due to the use of the digital integrator. Even very small signal levels can therefore be processed reliably with the circuit according to the invention. The particularly high immunity to interference is inventively achieved in that the previously known in connection with the correction of duty cycle analog integrators, such as those contained in the circuit of the document mentioned above - are replaced by a digital integrator, a full digital Processing of the data signal allows.

Another essential advantage of the circuit according to the invention is that due to the use of the digital integrator, the pulse lengths of the digital data signal can vary greatly without adversely affecting the correction of the duty cycle value thereof.

A third significant advantage of the circuit according to the invention is that, prior to the correction of the duty cycle value, no averaging of the pulse lengths of the pulses of the data signal has to be carried out in advance; because due to the use of the digital integrator also data signals can be processed with widely varying pulse lengths.

A fourth significant advantage of the circuit according to the invention is the fact that quasi arbitrary duty cycle values ​​can be set. There is no restriction to a duty cycle value of substantially 50%.

According to an advantageous embodiment of the invention, it is provided that the duty-cycle detector has a digital averaging circuit which determines the times at which the respective output signal of the digital integrator is used to form and update the control signal. The averaging circuit effects, on the one hand, an averaging of the sampling error caused by the at least one digital integrator and, on the other hand, an averaging of the variable data bit lengths of the digital data signal, thereby significantly reducing measurement and control errors in the correction of the duty cycle value.

The digital averaging circuit preferably has a signal edge counter which counts the signal edges of the corrected data signal and triggers the generation of the digital control signal as a function of its count with a trigger signal. The signal edge counter thus determines over what period of time the digital integrator should integrate.

Particularly simple and thus advantageous the signal edge counter generates the trigger signal in each case when it has counted again after a previously performed triggering process a predetermined number of newly occurred - ie newly occurring after the last trigger time - signal edges.

The digital averaging circuit preferably has a latch module which is connected on the input side to an output of the digital integrator and switches on the output signal of the digital integrator as the control signal of the duty cycle correction device if a trigger signal of the signal edge counter is applied to a control connection of the latch component. The latch module thus operates as a kind of memory which makes a switching through of the output signal of the digital integrator in each case when the signal edge counter has reached a corresponding counter reading.

The digital integrator preferably has a clock generator and an up and down counter connected to the clock generator. The up and down counter counts up or down at a "high" level of the corrected data signal and at a "low" level of the corrected data signal in the opposite direction. This means that in the case of a count-up in the case of a "high" level, a count-down takes place in the case of a "low" level; instead, a count-up may also occur in the case of a "low" level and a count-down in the case of a "high" level.

The up and down counter is preferably connected on the output side to the digital averaging circuit already mentioned, which determines the times at which the respective output signal of the digital integrator is used to form and update the control signal.

The up and down counter is preferably connected on the output side to an input of the latch module of the digital averaging circuit, wherein the latch module adopts the respective counter reading of the up and down counter to form and update the control signal and outputs it at its output, if a trigger signal is present at a control terminal of the latch module is applied.

Incidentally, it is considered advantageous if the duty-cycle correction device has an edge rise detector and a fall-off detector whose output signals are used to form the corrected data signal.

Preferably, the edge rise detector and the edge fall detector each have a phase shifter upstream, at the input side of which the data signal is present. At least one of the two phase shifters, preferably the phase shifter upstream of the edge drop detector, is designed to be controllable by means of a control connection, so that an external control is possible.

The control of the controllable phase shifter is preferably carried out with the latch module of the digital integrator.

In addition, it is considered advantageous if at the output of the edge rise detector and at the output of the edge drop detector, an RS (reset / set) latch module is connected, which forms the corrected data signal with the output signals of the edge rise detector and the edge drop detector.

Between the signal output of the duty cycle correction device and the output of the RS latch module, one or more buffer or amplifier modules can be arranged electrically, through which the corrected data signal is passed before it at the signal output of the duty cycle correction device is delivered.

The invention also relates to a method for duty cycle correction of a digital data signal.

With regard to such a method, it is provided according to the invention for the purpose of achieving the object stated at the outset that two auxiliary signals having a predetermined phase shift from one another are formed from the data signal. With the two auxiliary signals, a data signal corrected with respect to the duty cycle value is obtained by determining the deviation of the duty cycle value of the corrected data signal from a default value by means of a duty cycle detector and adjusting the phase shift between the auxiliary signals, that the deviation of the duty cycle value from the default value becomes minimal. For this purpose, a digital integration is carried out with the duty-cycle detector according to the invention.

With regard to the advantages of the method according to the invention, reference is made to the above statements in connection with the circuit according to the invention, since the advantages of the circuit according to the invention essentially correspond to the advantages of the method according to the invention.

With regard to advantageous embodiments of the method according to the invention, reference is made to the dependent claims to the independent method claim.

To illustrate the invention:

<dl id="dl0001"><dt>FIG. 1</dt><dd>an embodiment of a circuit according to the invention for correcting the duty cycle value of a digital data signal, with the circuit can also perform the inventive method;</dd><dt>FIG. 2</dt><dd>an embodiment of a digital duty cycle detector for the circuit of Figure 1;</dd><dt>FIG. 3</dt><dd>the mode of operation of the circuit according to FIG. 1 and of the digital duty-cycle detector according to FIG. 2 on the basis of signal characteristics;</dd><dt>FIG. 4</dt><dd>a characteristic curve for controlling a controllable phase shifter of the circuit according to Figure 1 and</dd><dt>FIG. 5</dt><dd>a table that exemplifies digitally coded control signals for driving the phase shifter according to the figure 1.</dd></dl>

FIG. 1 shows a circuit for correcting the duty cycle value of a digital data signal "Data Input". One recognizes a duty-cycle correction device 20, at whose signal input E20 the digital data signal "Data Input" is present.

At a signal output A20 of the duty cycle correction device 20, a corrected data signal with a corrected duty cycle value is generated by the latter; the corrected data signal carries the reference character "Data Output" in FIG.

With the signal output A20 of the duty cycle correction device 20, a digital duty cycle detector 30 is connected to an input E30. An output A30 of the duty cycle detector 30 is connected to a control input S20 of the duty cycle correction device 20 and controls it via a control signal L.

The duty cycle correction device 20 has on the input side two phase shifters 40 and 50, which are both the input side of the data signal "Data Input" acted upon. The one phase shifter 40 causes a fixed phase shift of, for example, t_bit/ 2.

The further phase shifter 50 is a controllable phase shifter whose phase shift Δφ is set by the control signal L of the digital duty cycle detector 30 at the control input S50.

The one phase shifter 40 is followed by a rising edge detector 60, which in turn is connected on the output side to a set input S70 of an RS latch module 70.

A reset input R70 of the RS latch 70 is connected to an output A80 of a falling edge detector 80 ("Falling Edge Detector"). The falling edge detector 80 is connected to an input E80 and to an output A50 of the controllable phase shifter 50 in connection.

An output A70 of the RS latch 70 is connected to the signal output A20 via two inverters 90 and 100 acting as buffer elements and amplifiers.

FIG. 2 shows the structure of the digital duty cycle detector 30. One recognizes the input E30 at which the corrected data signal "Data Output" is applied to the digital duty cycle detector 30.

An input E200 of a digital signal edge counter 200 is connected to the input E30 of the duty cycle detector 30. In addition, the input E30 of the digital duty cycle detector 30 is connected to a control terminal S210 of a digital integrator 210.

An output A210 of the digital integrator 210 is connected to an input E220 of a latch module 220 whose output A220 forms the output A30 of the duty cycle detector 30 according to FIG. A control terminal S220 of the latch module 220 is connected to an output A200 of the signal edge counter 200 and is triggered by the latter via a trigger signal G.

As can be seen from FIG. 2, the digital integrator 210 consists of a clock generator 230, whose output is connected to an input E240 of an up and down counter 240. The up and down counter 240 has a control connection S240, which forms the control connection S210 of the digital integrator 210 and is supplied with the corrected data signal "Data Output". The output A240 of the up and down counter 240 forms the output A210 of the digital integrator.

In addition, it can be seen in FIG. 2 that the signal edge counter 200 has an edge counter 250 (edge ​​counter) and a downstream gate generator 260. At the output of the gate generator 260, the trigger signal G is formed for the latch module 220.

The latch module 220 as well as the signal edge counter 200 formed by the edge counter 250 and the gate generator 260 form a digital averaging circuit 270 which cooperates with the digital integrator 210.

The operation of the circuit for correcting the duty cycle value of the digital data signal "data input" will now be explained below with reference to the data signals occurring in the circuit, which are shown in FIG.

It can be seen in Figure 3, the time course of the data signal "Data Input". It can be seen that the "high" level of the data signal "data input" is one bit length "t_bit" having.

The data signal "Data Input" is fed to the Duty Cycle Correction device 20 at the signal input E20 and reaches the two phase shifters 40 and 50, which cause a phase shift. Since one phase shifter 40 is a phase shifter with a fixed phase shift, the signal A arises at the output of the phase shifter 40 with a phase shift that is invariable with respect to the data signal.

The signal B is produced at the output of the controllable phase shifter 50. It can be seen that three signal rising edges 300, 310 and 320 are shown in FIG. 3 for the signal B:

The first rising edge 300 shows the signal edge rise in the event that with the control signal L, a phase shift of the phase shifter 50 is caused, which is smaller than the phase shift of the phase shifter 40.

The mean rising edge 310 represents the rising edge for the case in which the control signal L is used to set a phase shift in the phase shifter 50 which corresponds to the phase shift of the phase shifter 40. In such a case, therefore, the signal rise edge 310 of the signal B and the rising edge 310 'of the signal A occur at the same time.

The reference numeral 320 symbolizes the signal rising edge of the signal B in the event that the control signal L, a phase shift of the phase shifter 50 is caused which is greater than the phase shift of the phase shifter 40.

Similarly, numerals 330, 340, and 350 symbolize the associated signal falling edge of signal B, respectively, for the smaller, medium, and larger phase shifts of phase shifter 50.

The output signal A generated by the one phase shifter 40 arrives at the edge rise detector 60 which forms a signal A 'therefrom. The signal A 'is a pulse which occurs at the time when the signal A has its signal rise.

The output signal B generated by the further phase shifter 50 reaches the edge drop detector 80, which thus forms a signal B '. The signal B 'is also a pulse-shaped signal and always occurs when the signal B at the input E80 of the edge drop detector 80 has a falling signal edge. In FIG. 3, three signal pulses 360, 370 and 380 are shown in this regard: The pulse 360 ​​refers to the signal falling edge 330 of the signal B; the middle pulse 370 refers to the falling edge 340 of the signal B and the pulse 380 to the falling edge 350 of the signal B. This assignment is shown in FIG. shown sinusoidal arrows.

The two signals A 'and B' of the edge rise detector 60 and the edge fall detector 80 reach the RS latch module 70, which thus forms the corrected data signal "Data Output". Specifically, a "high" signal is generated at the output A70 of the RS latch module 70 when a signal pulse is present at the set input S70 of the RS latch module 70. The corrected data signal "Data Output" is switched back to a "low" level as soon as the signal B 'at the reset input R70 its pulse 360, 370 or 380 having.

In summary, it can be stated that the bit length t '_bit the "high" level of the corrected data signal "Data Output" depends on which phase shift is set at the control terminal S50 of the controllable phase shifter 50.

The control of the further phase shifter 50 at the control terminal S50 is effected by means of the duty cycle detector 30 in the following manner: At the input E30 of the duty cycle detector 30, the corrected data signal "Data Output" in the digital averaging circuit 270 and at a control terminal S210 fed to the digital integrator 210. The clock generator 230 present in the digital integrator 210 generates a clock signal Clk whose clock frequency is greater than the data rate of the data signal "Data Input". of the corrected data signal is "Data Output". As a result, an oversampling of the data signal "data output" will be ensured as will become clear below.

Advantageously, the clock frequency f_Clk of the clock signal Clk is a multiple of the data rate of the data signal "Data Ouput". It therefore applies:<maths id="math0002" num=""><math display="block"><mrow><msub><mrow><mi mathvariant="normal">f</mi></mrow><mrow><mi mathvariant="normal">Clk</mi></mrow></msub><mo>=</mo><mi mathvariant="normal">N</mi><mo>*</mo><mn>1</mn><mo>/</mo><msub><mrow><mi mathvariant="normal">t</mi></mrow><mrow><mi mathvariant="normal">bit</mi></mrow></msub><mn>,</mn></mrow></math><img file="EP1633043A2_D0002.tif" /></maths> where t_bit indicates the bit length of the data signal Data Input or Data Output. N is any real number greater than one. For example, N can be an integer.

The up and down counter 240 connected downstream of the clock generator 230 now counts the clocks of the clock signal Clk of the clock generator 230. In this case, the counting direction of the up and down counter 240 is determined by the corrected data signal "Data Output" applied to the control terminal S210 of the digital duty cycle detector 210 and thus to the control terminal S240 of the up and down counter 240. If the corrected data signal "Data Output" has a "high" level, the up and down counter, for example, counts up. If the corrected data signal "Data Output" has a "low" level, it is counted down accordingly.

Alternatively, the counting direction of the up-down and down-counter 240 may also be exactly the opposite: this means that at a "high" level of the corrected data signal, "data output" is counted down and counted up at a "low" level of the corrected data signal "data output" becomes.

The up and down counter 240 performs a kind of integration based on the count direction changing depending on the level of the corrected data signal "Data Output" whose integration value indicates the duty cycle value of the corrected data signal "Data Output": namely, the bit length t_bit("high") of a "high" level as long as the bit length t_bit("low") of a "low" level, so will appear at the output A240 of the up and down counter 240 as a count zero, because as long as "counted up" as "counted down". With a duty cycle value of 50%, a zero therefore arises at the output of the up and down counter 240.

If the duty-cycle value of the corrected data signal Data Output shifts to higher or lower values, then the output A240 of the up-down and down-counter 240 will have a non-zero number.

If, as will be assumed below by way of example, in the case of a "high" level of the corrected data signal "Data Output" is counted up and down at a "low" level of the corrected data signal "Data Output", then in the case of a duty cycle Value Dc below 50% of the counter "longer" down than count up, so that at the output A240 of the up and down counter 240 will form a negative count.

As already mentioned, the duty cycle value Dc is calculated according to: <maths id="math0003" num=""><math display="block"><mrow><mi mathvariant="normal">Dc</mi><mo>=</mo><mfrac><mrow><msub><mrow><mi mathvariant="italic">t</mi></mrow><mrow><mi mathvariant="italic">bit</mi></mrow></msub><mo mathvariant="italic">(</mo><mi mathvariant="italic">high</mi><mo mathvariant="italic">)</mo></mrow><mrow><msub><mrow><mi mathvariant="italic">t</mi></mrow><mrow><mi mathvariant="italic">bit</mi></mrow></msub><mo mathvariant="italic">(</mo><mi mathvariant="italic">high</mi><mo mathvariant="italic">)</mo><mo mathvariant="italic">+</mo><msub><mrow><mi mathvariant="italic">t</mi></mrow><mrow><mi mathvariant="italic">bit</mi></mrow></msub><mo mathvariant="italic">(</mo><mi mathvariant="italic">low</mi><mo mathvariant="italic">)</mo></mrow></mfrac><mn>,</mn></mrow></math><img file="EP1633043A2_D0003.tif" /></maths>

On the other hand, if the duty cycle exceeds a value of 50%, "longer" is counted up than down, so that a positive counter reading will form at the output A240 of the up and down counter 240.

In summary, it can be seen that the count at the output A240 of the up and down counter 240 represents the duty cycle value of the data signal "Data Output".

The count C at the output A240 of the up and down counter 240 is referred to in Figure 3 as "Counter Jams C". It can be seen that the count fluctuates and increases when the data signal "Data Output" has a "high" level and reduces when the corrected data signal "Data Output" has a "low" level.

In FIG. 3, the case is shown by means of a solid line, that the duty cycle value is exactly 50%. The dashed, so upper line indicates the course of the count C in the event that the duty cycle value is greater than 50% or too large. The dash-dotted, so lower line indicates the count C in the event that the duty cycle value is less than 50%.

The respective counter reading C is now not directly switched to the control terminal S50 of the phase shifter 50, but instead fed to the digital averaging circuit 270. Concretely, the counter reading C reaches the latch module 220, which always forwards the counter reading C as control signal L to the duty cycle correction device 20 at those times to which a trigger signal G is applied to the control connection S220 of the latch module 220. The trigger signal G is always generated by the gate generator 260 of the signal edge counter 200 when the edge counter 250 of the signal edge counter 200 a predetermined number of edge changes or Has detected bit changes.

This can be seen in FIG. 3, since in FIG. 3 the trigger signal G is also drawn. It can be seen that when the trigger signal G occurs, the respective counter reading C of the up-down and down-counter 240 is taken over to the output A220 of the latch module 220 and thus the control signal L, which represents the counter reading C, is formed.

The control signal L is also shown in FIG. It can be seen that the height of the control signal L depends on the respective counter reading C of the up and down counter 240.

In summary, it can be seen that the clock generator 230 and the up and down counter 240 form a digital integrator, which performs a digital integration of the corrected data signal "Data Output". Characterized in that the clock frequency of the clock signal Clk is a multiple of the data rate of the data signal "Data Output", an oversampling is achieved, by which the sampling error is reduced in the digital integration. Specifically, the temporal sampling error is T_ABT:<maths id="math0004" num=""><math display="block"><mrow><msub><mrow><mi mathvariant="normal">T</mi></mrow><mrow><mi mathvariant="normal">ABT</mi></mrow></msub><mo>=</mo><mfrac><mrow><mn>1</mn></mrow><mrow><msub><mrow><mi mathvariant="normal">ƒ</mi></mrow><mrow><mi mathvariant="italic">Clk</mi></mrow></msub></mrow></mfrac><mo>.</mo></mrow></math><img file="EP1633043A2_D0004.tif" /></maths> so that as the clock frequency increases, the sampling error becomes smaller.

Incidentally, as part of the digital integration of the digital integrator 210, a large number of data bits are taken into account by the digital averaging circuit 270. Depending on the coding of the data signal "Data Input", it can happen that a large number of "high" or "low" levels are transmitted in succession. To avoid such a stringing of identical signal levels resulting in a false integration result in the digital integrator 210, the digital averaging circuit 270 is provided which forces an averaging over a longer period of time. Specifically, in fact, the integration in the digital integrator 210 is always carried out as long as this is specified by the signal edge counter 200. The signal edge counter 200 thus ensures that a given number of different signal levels is always taken into account in the digital integration. So it is a "minimum integration time" by the signal edge counter 200 or forced by the digital averaging circuit 270.

In order to achieve that a suitable phase shift value is set with the further phase shifter 50, the duty cycle detector 30 must form a suitable feedback loop. This requires the duty-cycle detector 30 to have a "negative" characteristic or a negative feedback of the control loop.

Such a negative characteristic or negative feedback is shown in FIG. FIG. 4 shows the phase shift Δφ ("delay") caused by the further phase shifter 50 as a function of the control signal L.

The control signal L is determined by a digital number, which is represented by a predetermined number of bits. If the up and down counter 240 is a four-bit counter, coding of the control signal L may be, for example, as shown in the table of FIG. It can be seen in FIG. 5 that, given a count of zero ("0000"), the further phase shifter 50 is activated in such a way that it causes a phase shift of<maths id="math0005" num=""><math display="block"><mrow><mi mathvariant="normal">Δφ</mi><mo>=</mo><mn>1</mn><mo>/</mo><mn>2</mn><mo>*</mo><msub><mrow><mi mathvariant="normal">t</mi></mrow><mrow><mi mathvariant="normal">bit</mi></mrow></msub></mrow></math><img file="EP1633043A2_D0005.tif" /></maths> causes. For counter readings greater than zero, the phase shift ΔΦ produced by the further phase shifter 50 is reduced. For example, with a count of 2 (digital value "0010"), a phase shift of only occurs<maths id="math0006" num=""><math display="block"><mrow><mi mathvariant="normal">Δφ</mi><mo>=</mo><mo>(</mo><mn>1</mn><mo>/</mo><mn>2</mn><mo>-</mo><mn>2</mn><mo>/</mo><mn>16</mn><mo>)</mo><mo>*</mo><msub><mrow><mi mathvariant="normal">t</mi></mrow><mrow><mi mathvariant="normal">bit</mi></mrow></msub></mrow></math><img file="EP1633043A2_D0006.tif" /></maths> on.

Negative counter readings, for example a count of -1, are taken into account by an overflow of the counter. A count of -1 thus corresponds to a count of 15 in the case of a four-bit counter, so that forms a digital number "1111" as a count. Such a count tells the other phase shifter 50 that a phase shift<maths id="math0007" num=""><math display="block"><mrow><mi mathvariant="normal">Δφ</mi><mo>=</mo><mo>(</mo><mn>1</mn><mo>/</mo><mn>2</mn><mo>+</mo><mn>1</mn><mo>/</mo><mn>16</mn><mo>)</mo><mo>*</mo><msub><mrow><mi mathvariant="normal">t</mi></mrow><mrow><mi mathvariant="normal">bit</mi></mrow></msub></mrow></math><img file="EP1633043A2_D0007.tif" /></maths> should be set.

The remaining negative counter readings are achieved by counting down, as can be seen in the table according to FIG. For example, at a count of -2 ("1110") the further phase shifter 50 is informed that a phase shift of<maths id="math0008" num=""><math display="block"><mrow><mi mathvariant="normal">Δφ</mi><mo>=</mo><mo>(</mo><mn>1</mn><mo>/</mo><mn>2</mn><mo>+</mo><mn>2</mn><mo>/</mo><mn>16</mn><mo>)</mo><mo>*</mo><msub><mrow><mi mathvariant="normal">t</mi></mrow><mrow><mi mathvariant="normal">bit</mi></mrow></msub></mrow></math><img file="EP1633043A2_D0008.tif" /></maths> should be generated.

In order to achieve that there can be no phase shift with a change of the digital value from "1000" to "1001" or from "1001" to "1000", the respective phase value ΔΦ is stored and recorded, if at a count of "8" is counted upwards and at a count of "9" down. If, therefore, the phase range which can be set by means of the further phase shifter 50 is left, then the latch module 220 ensures that the maximum phase shift value<maths id="math0009" num=""><math display="block"><mrow><mi mathvariant="normal">Δφ</mi><mo>=</mo><mo>(</mo><mn>1</mn><mo>/</mo><mn>2</mn><mo>+</mo><mn>7</mn><mo>/</mo><mn>16</mn><mo>)</mo><mo>*</mo><msub><mrow><mi mathvariant="normal">t</mi></mrow><mrow><mi mathvariant="normal">bit</mi></mrow></msub></mrow></math><img file="EP1633043A2_D0009.tif" /></maths> or the minimum phase shift value<maths id="math0010" num=""><math display="block"><mrow><mi mathvariant="normal">Δφ</mi><mo>=</mo><mo>(</mo><mn>1</mn><mo>/</mo><mn>2</mn><mo>+</mo><mn>8th</mn><mo>/</mo><mn>16</mn><mo>)</mo><mo>*</mo><msub><mrow><mi mathvariant="normal">t</mi></mrow><mrow><mi mathvariant="normal">bit</mi></mrow></msub></mrow></math><img file="EP1633043A2_D0010.tif" /></maths> is maintained.

Latch 220 may be equipped with an internal or external processor for this functionality.

In order to ensure trouble-free operation of the circuit according to FIGS. 1 and 2, the counter length of the up and down counter 240, the bit length of the latch module 220 and the resolution of the phase shifter 50 are matched with respect to the number of bits; this means that these components preferably work with the same bit length.

Finally, it should be mentioned that about the counter lengths of the signal edge counter 200 and the up and down counter 240 and by means of the clock frequency f_Clk of the clock signal Clk of the clock generator 230, the control times of the duty cycle correction device can be adjusted.

LIST OF REFERENCE NUMBERS

<dl id="dl0002" compact="compact"><dt>10</dt><dd>Circuit for correcting the duty cycle value of a data signal</dd><dt>20</dt><dd>Duty cycle corrector</dd><dt>30</dt><dd>Duty cycle detector</dd><dt>40</dt><dd>phase shifter</dd><dt>50</dt><dd>Controllable phase shifter</dd><dt>60</dt><dd>Rising edge detector</dd><dt>70</dt><dd>RS-latch block</dd><dt>80</dt><dd>Roll-off detector</dd><dt>90/100</dt><dd>buffer elements</dd><dt>200</dt><dd>Signal edge counter</dd><dt>210</dt><dd>Digital integrator</dd><dt>220</dt><dd>Latch block</dd><dt>230</dt><dd>clock generator</dd><dt>240</dt><dd>Up and down counter</dd><dt>250</dt><dd>edge counter</dd><dt>260</dt><dd>gate generator</dd><dt>270</dt><dd>Digital averaging circuit</dd><dt>A</dt><dd>Output signal of the phase shifter 40</dd><dt>B</dt><dd>Output signal of the controllable phase shifter 50</dd><dt>A '</dt><dd>Output signal of the edge rise detector 60</dd><dt>B '</dt><dd>Output signal of the edge drop detector</dd><dt>Data Output</dt><dd>Corrected data signal</dd><dt>G</dt><dd>Trigger signal G of the signal edge counter 200</dd><dt>Clk</dt><dd>Clock signal of the clock generator 230</dd><dt>Counter Status C</dt><dd>Count of the up and down counter 240</dd><dt>L</dt><dd>Digital control signal at the output of the latch module 220</dd></dl>