Memory architecture with segmented write lines

The present invention relates generally to the field of integrated circuit memories, and more particularly, memory circuit integrated architecture having to write lines segmented. The invention applies typically, but not exclusively, to RAMs MRAM magnetic type having such architecture.

More specifically, the invention relates in a first aspect, a memory device, comprising at least a segmented write line, with programming means controlled by row addressing means write mode of the memory device to program at least one cell memory coupled to said segmented write line, a read bit line being connected to a reading circuit for reading the contents of said mode cell reading of the memory device. In the context of the present invention, means segmented write line, a write line formed of at least one Writing segment.

The description of the following invention is made with reference to a MRAM memory type , few reminders of its operation are presented below.

The magnetic random access memory MRAM (Anglo-Saxon acronym for "Magnetic Random Access Memory") are non-volatile memories, wherein each memory cell is formed of a magnetic tunnel junction. This guy memory has all the combined advantages of semiconductor memories currently existing: speed as writing that they have read, low power consumption, non-volatility and insensitivity to radiation. These strengths are more combined with an opportunity for increased integration due to the small size of cells.

Typically, a magnetic random access memory device comprises a matrix of memory cells arranged in rows and columns, through which are routed metal tracks dedicated to writing and reading. Metal write tracks extending along rows of cells memory are called word write lines and metal tracks extending along the columns of memory cells are called bit write lines. Each memory cell thus placed at the intersection of a word line and a bit line stores an information bit form of guidance of magnetization.

In the standard architecture, addressing of memory cells for writing is thus effected by means of magnetic fields induced by a matrix array of metal lines subject to current pulses, only the memory cell at the intersection of two lines of writing selected before turning around. To the reading, a low amplitude current is sent through a line read bit and a CMOS drive transistor for example, to read the resistance of the junction. Note that in this type of memory circuitry reading is at least partially dissociated from the write circuitry.

Each of the memory cells is in fact consists of two layers magnetic, separated by a dielectric layer. Each magnetic layer has its own orientation of magnetization. The orientation of the magnetization of a layer, said free layer is changed, while the orientation of the magnetization of the other layer, said pinned layer is fixed in a particular orientation. The orientations of magnetization of the two layers can be in two situations: either parallel, that is to say aligned in the same direction, or anti-parallel, that is to say aligned in directions opposed. These two orientations, parallel and anti-parallel, represent logical values ​​"1" and "0", respectively. Alternatively, the parallel state can be interpreted as a logic "0" and the anti-parallel state such as a "1" logic.

Therefore, writing to such a memory cell is to position the orientation of magnetization in the free layer in function of the logic state desired, in a state either parallel or anti-parallel relative to the direction of magnetization of the pinned layer.

Typically, external magnetic fields are applied to a selected cell to switch the orientation of magnetization in the layer free of this cell from one state to another. To do this, a write current is respectively applied on the word line and the write bit line intersecting at the location of the selected memory cell. The write currents and applied to the word line and the selected bit line create fields magnetic, which when combine with the intersection of the word line and the bit line, for switching the orientation of magnetization of the free layer of the selected memory cell from parallel to anti-parallel state, or vice versa, depending on the data to be written into the cell.

The changeover from one state to another in a selected memory cell writing requires high magnetic fields, which requires to circulate sufficiently strong write currents of the order of ten milliamperes, at the metal paths constituting the write lines of word and bit at the intersection of which is the selected memory cell writing.

However, the conductive tracks constituting the write lines are by nature resistive. The fact of passing a strong current of the order of ten milliamps on a writing line will inevitably cause a fall the potential at the terminals thereof, by applying Ohm's law. A tension therefore relatively high power is required at the circuit write control to compensate for the potential drop across lines metal writing.

However, future memory topologies, including responding to increased integration constraints, prevent the use of high transistors voltage to the control circuits of the write current. In this perspective, thus looking increasingly to converge to a voltage single nominal power, for example of the order of 1.2 volts.

In this context, one can consider a MRAM memory architecture to word write lines and / or segmented bit. Indeed, in such architecture, as shown for example in the patent document US6,594,191, the plurality of memory cells is arranged in segments along the memory array. The bit write lines and / or word through the plane memory are themselves segmented, creating current paths Shorter writing. This architecture implies a resistive load equivalent of the lowest entry lines, allowing a voltage Power supply of lower nominal since the line losses are lower. A Such architecture segmented writing line also minimizes the wrong tilt probability cells in unselected memory writing. Indeed, only the memory cells on the path of the line segment selected write will then be subjected to the magnetic field generated by the passing the write current to the segment, instead of the entire row and / or column of memory cells.

However, the implementation of such an architecture with lines Word writing and / or segmented bit involves a number of constraints, relating in particular to the addressing of different segments of writing line.

To illustrate this, here we refer to figure 1, describing a way Simplified part of an MRAM type memory array architecture as a matrix segmented bit write line. A memory array of the type Consequently it comprises a plurality of bit write lines and segmented a plurality of word write lines arranged in matrix as a architecture column, typically 64, 128 or 256 lines at the intersection which are positioned type MRAM memory cells. In order to simplify the explanation, simply shows two columns and a row of memory cells.

Thus, only two segments of bit write lines 10 and 20, extending along two columns of the memory array, are shown with their circuitry associated with writing. Two memory cells 30 and 40 are disposed at the intersection a word write line 50 and each of the segments of write lines of Bit 10 and 20. One could envisage an architecture further comprising write lines of segmented word. The write circuitry associated with bit write line segments that will be described hereinafter would end of Similarly the level of the word line segments. The circuitry of reading associated including read word lines including role convey line decode information, which can be reused for the purpose writing.

First, the segments of bit write lines 10 and 20 are connected by one of their ends to a power supply 60, for example 1.2 volts. For send a write column among a plurality of decoding means column address are provided. These means are constituted by a bus of 70 addresses, conveying such six column address signals in the For a memory array comprising 64 columns, associated circuits decoding 80 address for each column, made in static logic. The output of each column decoding circuit 80 is provided to drive programming means 90 associated with the bit write line segment address. These programming means 90, also for switching the line to ground segment are symbolically represented by a transistor, whose source is connected to a ground line 100, the drain is connected to write line segment 10 and the gate is controlled by the output of the circuit column decode 80.

With respect to the read circuitry, it is dissociated to part of the write circuitry and we will return in more detail later in the Description.

At this point, it should first be noted that a plurality of segments unrepresented bit write line, such as segment 10, is the cascaded along each column of the memory array. For each line segment bit write cascaded, it is necessary to provide means to programming and it will therefore necessarily provide the decoding means associated address.

The major drawback of such a write line architecture segmented lies in the necessary redundancy decoding means address to each occurrence of write line segment, to select write segment of the plurality of segments.

However, in view of a segmented architecture, and taking into account the design requirements up to a higher density memories, it is not desirable to reproduce the specific logic level address decoding All writing line segments of which are indeed quite strong consumer space on the memory array.

The present invention aims to overcome the disadvantages previously cited by proposing a write lines memory device segmented, wherein the write addressing of the various line segments Writing does not lead to an overload decoding means to address line, and that is not detrimental in terms of density of the memory array.

To this end, the invention relates to a memory device, comprising at least a segmented write line formed of at least one write segment, with programming means, said programming means being controlled by row addressing means in the write mode of said device memory, for programming at least one memory cell coupled to said segmented write line, a read bit line being connected to a circuit reading to read the contents of that cell in read mode of said device memory, characterized in that said read bit line cooperates mode writing with the said row addressing means for controlling said means programming said segmented write line.

According to one characteristic of the invention, the segmented write lines include bit write lines.

According to a preferred embodiment, the memory device is organized in matrix form in bit writing lines and word writing lines, memory cells being positioned at the intersection of said write lines.

Alternatively, the word write lines are segmented.

Advantageously, the reading circuit comprises means for selecting column, and means for circulating in write mode Information column selection on the read bit line to the means address programming means associated with the write line segmented.

According to one embodiment, the addressing means means programming associated with segmented writing line, include a line selection conveying segment selection information and a means for logically combining having a first input connected to said line segment selection, a second input is connected to the read bit line and whose output is provided to activate said associated programming means said segmented writing line.

According to a particular embodiment, the read bit line includes a global read bit line connected to at least one bit line intermediate reading via selection means lines intermediate read bit, said intermediate read bit line accessing in reading in the memory cell by means of an access transistor of the cell.

Preferably, the global read bit line is shared by two columns of memory device, said global read bit line being connected to intermediate two read bit lines for read access respectively to each of the two columns.

Preferably, the memory cells are the type of MRAM.

The invention further relates to an integrated circuit comprising a device memory as described above.

Other characteristics and advantages of the present invention will more clearly on reading the following description, given by way of example non-limiting illustration and with reference to the appended figures wherein:<ul><li>Figure 1, already described, shows a portion of a type of memory map MRAM according to a matrix architecture segmented bit write line, illustrating the problem to be solve the present invention; </li><li>Figure 2 is a diagram illustrating an embodiment of the device of Memory according to the present invention;</li><li>Figure 3 is a variant of the memory device according to the present invention, wherein a reading circuitry with global bit lines and intermediate is carried out.</li></ul>

Back to Figure 1, to be interested now more specifically to means for reading the memory cells of the memory array. According to the example of embodiment of Figure 1, for each column of the memory array, there is provided a read bit line associated respectively 150 and 160, constituted by a metal track intended to convey a sense current. Each bit line Reading has the distinction browse the entire memory array. A word line reading conveying a signal wl &lt;i&gt; is used to select the read row of memory cells, in particular comprising the cells 30 and 40 represented by means of read access transistors, respectively 170 and 180. The simultaneous use of the bit line 150, for example, allows driving a read current through the selected memory cell 30 by through the access transistor 170 activated by a signal in the high state applied to the selection word line wl &lt;i&gt;.

To do this, each read bit line 150, 160 is connected at one of its ends at a read circuit 110, formed by a sense amplifier 120 associated with column decode means 130, for selecting a read column among a plurality of columns.

It therefore follows from the above that the material resources in work in playback mode are largely completely separate part of material resources implemented in the memory write mode. Furthermore, the reading means are facing the same problem as the means writing, for decoding a column of the memory array from a plurality of columns. The present invention therefore aims to take advantage of the fact that the reading means already incorporate means decoding columns 130 at the read circuit 110, permitting to select a column among a plurality of columns for reading.

Also, in an architectural context in segmented lines of writing, and more particularly to segmented bit lines, the concept of the invention He is to reuse material resources already present in the map memory and normally assigned reading in order to avoid redundancy ways to address the write-selected cells decoding at each bit write line segment instance. It should be noted that the concept of the present invention would apply equally well to architecture where the write lines are formed of a single write segment, returning to consider non-segmented lines.

2 shows for this purpose an embodiment of the device of Memory according to the present invention. The elements in common with Figure 1 keep the same references. In Figure 2, there is shown this time two columns and two row of memory cells, each belonging to a segment different handwriting.

Thus, two segments of said additional bit write lines 10 'and 20 ', extending along both columns represented the memory array, are cascaded with their associated write programming means 90. Two memory cells are disposed at the intersection of a line respectively word write 50 'and each of the segments of bit write lines cascaded 10 'and 20'.

According to the invention, we will build on the column selection means 130 of the read circuit 110, supplying a column address decode signal normally vested in the selection read a column from a plurality of columns, and the metal contact that are the read bit lines, to allow the write addressing programming means 90 associated a write line segment. thus reusing the decoding means column of the read circuit for writing purposes and the read bit line is in turn used for conveying column selection information to destination of the write circuitry.

Consider an example where the writing is desired address ways to programming 90 associated with the segmented bit write line 10, to program the cell 30. A suitable address signal generated by the means of column select 130, is sent to the read bit line 150 corresponding to the column that it is desired to select in writing, by via means 140 provided for this purpose in the read circuit 110 and that all read bit lines are connected. these means 140, symbolically represented by a multiplexer in Figure 2 enable, either select reading bit line in read mode or to convoy column selection information on the read bit line.

The column selection information, and conveyed by the bit line read 150, then selects all line segments bit write 10, 10 ', associated with the relevant column.

The memory device according to the invention further comprises a line Selection own segment for each segment of the device. The selection line segment conveying a signal segsel &lt;n&gt; for the segment considered through therefore the memory array along the horizontal axis and is provided for conveying a additional information segment selection. If one wishes to go also write the programming means 90 of the line segment Writing 10 ', it is then necessary to activate the further segment selection line segsel &lt;n-1&gt;.

An additional information segment selection and conveyed, in combination with the column selection information conveyed by line read bit 150, then allows to send in writing the means programming 90 of the write line segment 10.

To do this, a logic gate 190, typically a logic gate AND type, specific to each bit write line segment includes first input connected to the segsel segment select line &lt;n&gt;, a second input connected to the read bit line 150 and an output connected the programming means 90 associated with the segmented bit write line 10 addressed in writing. The combination of signals by logic gate 190 therefore enables the programming means 90 of the line segment wanted to write.

The interest of the writing addressing means of write bit lines segmented implemented in the memory device according to the present invention is especially that they require only a single logic gate 190 instead of the plurality of logic gates involved in the circuit column decode referenced 80 in Figure 1. In addition, a single horizontal signal by segment, segsel &lt;n&gt;, is necessitated to perform the write addressing.

Figure 3 finally describes a particular embodiment of the device memory according to the present invention, wherein the read circuitry is modified, particularly as regards the read access paths the memory cells. Thus, according to this embodiment, the bit line reading 150 is a global read bit line crossing the whole plane memory, and connected to intermediate read bit lines. According to a mode embodiment, a global read bit line is shared by two example columns of the memory array and is then adapted to be connected to two bit lines BL0 intermediate reading, BL1 to read access to each column respectively. The connection between the global read bit line and the lines intermediate read bit is performed by means of transistors of selection group 200, 210 controlled by the GSEL signals. The bit line intermediate BL0 and allows read access to the memory cell 30 by through the access transistor 170 and the intermediate bit line BL1 allows read access to the memory cell 40 through the access transistor 180.

The advantage of this architecture is that reading of the set of points memories of a column is no longer connected directly to the bit line global reading, which minimizes the capacitive loads on the line global read bit and thus improve the performance in terms of speed.

Thus, to read the contents of the cell 30 for example, is selected First the global read line 150 and then activates the selection transistor 200 allowing access to the intermediate bit line BL0 via the signal GSEL &lt;1&gt; and then, is selected to access the cell 30 by activating the access transistor 170 via wl &lt;i&gt; signal. During this operation reading, access to the intermediate read bit line BL1 is closed, a signal GSEL &lt;0&gt; is applied to the gate of corresponding select transistor 210.

Regarding write addressing means programming a bit write line segment, decoding information column is conveyed by the global read bit line 150 to the write circuitry. However, during such use of the resources of Read-write mode, it is necessary that the paths lines intermediate bit first, then to the other cells, are closed.

In the example, we have a common global bit line in two columns. The column selection information carried by the read bit line Global 150 then selects write all segments of bit write line, in particular 10 and 20, associated with each of the two columns respectively. In this configuration, for the segment, the door logic 190 associated with each bit of segmented write line 10, 20 therefore sees one of its inputs connected to the global read bit line 150. To writing the address in either segmented line, the other input of each logic gate 190 associated with each bit of segmented write line 10, 20 must then be connected to a different line of horizontal selection, respectively Col_sel &lt;1&gt; and Col_sel &lt;0&gt;, so as to select a column among the two addressed.

The concept of the present invention has been more particularly described in MRAM reference to a type of memory, but could actually be applied non-limiting manner to all types of memory integrated circuit having a write line architecture segmented formed of at least one write segment and including writing paths and differentiated reading.