Semiconductor structure on an extremely rough substrate

<u>Technical field and prior art</u>

p0001The invention relates to the field of substrates or structures for the electronic components, as well as methods of making such substrates or structures.

p0002It also relates to the assembly techniques of layers or substrates on rough layer or rough substrate.

p0003It applies to semiconductor structures, and in particular those of the SOI type.

p0004The document <patcit id="pcit0001" dnum="US20020069816A1"><text>US 2002/006 9816 A1</text></patcit> describes methods of manufacturing gallium nitride layers on textured silicon substrate.

p0005The document <patcit id="pcit0002" dnum="US5782975A"><text>US 5782975</text></patcit> describes a method for providing a silicon substrate and diamond having a transition layer carbon / silicon.

p0006The latter structures comprise, as illustrated in <figref idrefs="f0001">figure 1</figref>, A layer 4 of silicon, wherein the components themselves are located and in which is formed a buried layer 2 of silicon oxide. The latter constitutes a vis-a-vis insulation parasitic currents and charges originating from ionized particles. It also provides good insulation of adjacent components made in the same layer of silicon, including a significant reduction in parasitic capacitance between such adjacent components. She itself rests on a substrate 6 of silicon, which acts as a mechanical support.

p0007Typically, the surface layer 4 of silicon, for example a thickness of about 10 to 1000 nm, while the oxide layer 2 has a thickness of the order of several hundreds of nm, for example 400 nm.

p0008This type of structure can be obtained by a process type "SIMOX", or by molecular bonding.

p0009After making an assembly such as that of <figref idrefs="f0001">figure 1</figref>, Electronic components can be made in the surface layer 4 of silicon. It is therefore the active layer, the oxide layer 2 is an insulating layer, the substrate 6 serving as a mechanical support and allow handling of the assembly.

p0010The proper functioning of a component, made in layer 4, is related to various parameters which is a warm-up, which may greatly limit the component performance.

p0011This raises the problem of finding a semiconductor-on-insulator structure, and a method of making such a structure, wherein the components of performance, then made in the semiconductor layer are not limited by heating, or are less limited by the heating as in known structures.

p0012According to another aspect of the invention, the assembly of materials known techniques do not allow to adhere directly together substrates or layers having a roughness greater than a certain limit value, of the order of 0.5 nm RMS or difficult to polish, or with a chemistry that does not allow molecular bonding.

p0013Or sometimes the need is felt, to link them materials each having a roughness greater than this limit value, or which at least is difficult to polish, or has a chemistry that does not allow molecular bonding, or bind such a material with a layer or substrate material which may already be itself compatible with a direct bond or by molecular adhesion.

<u>Disclosure of Invention</u>

p0014The invention firstly relates to a semiconductor structure according to claim 1.

p0015The layer of semiconductor material and the adhesion layer, may be bonded by molecular adhesion even if the substrate or the base layer formed thereon, has a roughness greater than the roughness limit accepted for molecular adhesion or "wafer bonding" (which is about 0.5 nm RMS), or even if the substrate or base layer formed on it is difficult to polish or has a chemistry incompatible with molecular bonding.

p0016It is therefore possible to use a substrate, or base layer, a material such as for example diamond or aluminum nitride (AlN), which are chemically inert, very difficult to polish and possess even after chemical mechanical treatment, a roughness value well above the limit value accepted by the molecular bonding.

p0017These materials also offer high thermal conductivity greater than 1 W / cm / K or 10 W / cm / K.

p0018Components can be made in the layer of semiconductor material, in particular power components or high power or RF type since the heat can then be discharged via the substrate, which acts as a heat sink.

p0019Preferably, the surface of the adhesive layer faces the layer of semiconductor material is located at a distance of at most 10 nm asperities or maximum peaks of the surface of the substrate or base layer, which optimizes the use of heat transfer properties of the upper silicon layer to the substrate.

p0020An intermediate layer may further be provided between the substrate and the adhesion layer. Such an intermediate layer has a coefficient of thermal conductivity between that of the adhesion layer and that of the substrate or base layer or higher than that of the substrate or base layer.

p0021This intermediate layer is, for example silicon nitride.

p0022A structure according to the invention, as set forth above, is compatible with a molecular adhesion of the layer of semiconductor material on the adhesion layer.

p0023The invention also relates to a method for producing a semiconductor structure according to claim 13.

p0024The structure according to the invention is for example an SOI structure, the semiconductor material being silicon, and the adhesive layer a layer of silicon dioxide.

p0025A method is described for bonding or assembling them two substrates or layers each having a roughness greater than 0.5 nm RMS, or being difficult to be polished, or with a hardly compatible chemistry with molecular bonding, the method comprising:<ul><li>forming a layer, called an adhesion layer directly on each substrate, or on each layer to be assembled,</li><li>achieve molecular bonding between the adhesive layers.</li></ul>

p0026Also a method is described for binding or bonding between the two substrates or layers, one of which (e) has a greater roughness of 0.5 nm RMS, or is difficult to polish, or a chemistry hardly compatible with molecular bonding, and the other a roughness lower than 0.5 nm RMS, or is easily polishable, or offer a consistent chemistry with molecular bonding, the method comprising:<ul><li>forming a layer, called the adhesive layer directly on the substrate or on the layer whose roughness is greater than 0.5 nm RMS, or is difficult to be polished, or a chemistry hardly compatible with molecular bonding,</li><li>achieve molecular bonding between the adhesive layer and the substrate or the layer whose roughness is less than 0.5 nm RMS and is easy to polish, or offer compatible chemistry with molecular bonding.</li></ul>

<u>BRIEF DESCRIPTION OF FIGURES</u>

p0027<ul><li>the <figref idrefs="f0001">figure 1</figref> shows a known SOI structure,</li><li>the <figref idrefs="f0001 f0002">Figures 2 to 4</figref> represent various structures according to invention,</li><li>the <figref idrefs="f0003">5A to 5D</figref> represent various steps of a method of producing a structure according to the invention,</li><li>the <figref idrefs="f0002">Figures 6 and 7</figref> represent other structures according to the invention.</li></ul>

<u>Detailed description of embodiments of the invention</u>

p0028A first example of a structure according to the invention is given in <figref idrefs="f0001">2</figref>.

p0029In this figure, reference numeral 10 denotes a substrate (preferably of an electrically insulating material), the reference 14 a layer or a substrate of a material chosen from semiconductor materials, for example silicon or germanium (Ge) or gallium arsenide (GaAs) or silicon-germanium (SiGe), or semiconductor components III - V or II - VI, and reference numeral 12 an adhesive layer between the substrate 10 and the layer or substrate 14.

p0030The substrate 10 is a substrate having a surface 15 is rough or has a roughness greater than 0.4 nm RMS or 0.5 nm RMS (RMS = root mean square value). It may also be a surface having a chemistry that does not accept a molecular adhesion, or whose chemical properties are not compatible with molecular bonding. This substrate may have a thickness between, for example, 100 .mu.m and 2 mm.

p0031In principle, a molecular bonding can not be achieved, or is very difficult to achieve, on a substrate or a surface having such roughness (see in particular <nplcit id="ncit0001" npl-type="b"><text>QY Tong and U. Gösele, Semiconductor Wafer Bonding: Science and Technology, Wiley-Interscience, p.86, 1999</text></nplcit>).

p0032The substrate 10 may also be of a flame polishable material, that is to say, a roughness lower than 0.4 nm RMS or RMS 0.5 nm can not be reached after a long polishing time: practically, we can therefore use such a material that with roughness greater than 0.4 or 0.5 nm RMS.

p0033The mechanical strength of an assembly comprising, for example, such a substrate and a layer or a substrate of semiconductor material, assembled by molecular adhesion, can be measured using the bonding wave, for example by transmission infra Red in silicon, or transparent in the case of transparent materials, or by acoustic microscopy in the presence of metal layers. It can also be assessed by measuring the bonding energy by the technique of the blade (described for example in<nplcit id="ncit0002" npl-type="s"><text>WPMaszara et al, J. Appl. Phys., Vol. 64, p. 4943, 1988</text></nplcit>): At room temperature, and in the hydrophilic case, this energy is greater than 60 mJ / m 2, for example greater than 70 mJ / m2 or even at 100 mJ / m 2, if there is actually gluing.

p0034The achievement or non-achievement of a molecular bonding can be determined by these mechanical measures.

p0035The diamond or aluminum nitride (AlN) are examples of materials which can be used for the substrate 10; they have roughnesses well beyond the value of 0.5 nm RMS roughness of the diamond is between RMS 30 nm and 100 nm RMS, that of aluminum nitride is in the range of 1 nm RMS, or between 0.5 nm RMS to 10 nm RMS.

p0036These materials are chemically inert, in particular in the case of the use of products such as "Caro" (sulfuric acid-based mixture and hydrogen peroxide) and Sc1 (based on ammonium hydroxide mixture, hydrogen peroxide and water).

p0037Preferably, substrate 10 is made of a high thermal conductivity material, for example more than 1 W / cm / K: this is the case of diamond or aluminum nitride AIN (3.2 W / cm / K).

p0038A layer, or base layer, it - even on a substrate, can also be used instead of the substrate 10. It may then have a thickness of several tens of nm, for example between 50 nm and 300 nm. The material of this layer has the same properties as those described above in the case of a single substrate: this is hardly polishable material, or has a roughness greater than 0.4 nm RMS or 0.5 nm RMS (RMS = root mean square value) or has a surface with a chemistry that is not or does not accept a molecular adhesion, or whose chemical properties are not compatible with molecular bonding.

p0039For example, diamond or aluminum nitride can be provided either as the substrate or as a layer on a substrate, the latter being for example of silicon. Depositing diamond or aluminum nitride can then be obtained by CVD technique.

p0040In the following, the expression "substrate" refer to both alternatives.

p0041Layer 12 is called an adhesion layer, and has, after chemical-mechanical treatment or polishing, a surface roughness less than 5 nm RMS. It serves to adhere the substrate material 10 with the layer or substrate 14 of semiconductor material. It is preferably connected to the adhesive layer 12 by molecular adhesion.

p0042In one example, layer 12 is silicon dioxide. It can also be a material of "high coefficient K", such as those described in<nplcit id="ncit0003" npl-type="b"><text>MRS Bulletin, March 2002, Viol. 27, No. 3, "Alternative Gate Dielectrics for Microelectronics"</text></nplcit> : Such materials are, for example hafnium oxide (HfO2) or zirconium oxide (ZrO2) or alumina (Al2O3), or the Y2O3 (yttrium oxide).

p0043Another embodiment is illustrated in <figref idrefs="f0001">3</figref>Where references identical to those of the <figref idrefs="f0001">2</figref> designate identical or corresponding elements. In the structure illustrated in this figure, is further included a layer 16, intermediate between the adhesion layer and the substrate 10. The coefficient of thermal conductivity of said intermediate layer is between that of the adhesion layer and that of or substrate is higher than that of the substrate.

p0044For example, for an adhesion layer of silicon dioxide (SiO₂) Of thermal conductivity 0.01 W / cm / K, and a thermal conductivity of diamond substrate 20 W / cm / K, an intermediate layer of silicon nitride (Si₃ NOT₄) Clearly, this material having a coefficient of thermal conductivity of 0.3 W / cm / K.

p0045For a layer 12-type high coefficient K, we can also use silicon nitride Si₃ NOT₄ as material of the intermediate layer.

p0046Preferably, the material of layer 16 is much more resistant or selective than that of the layer 12 with respect to physico-chemical treatments or with respect to a polishing treatment such as a chemical-mechanical polishing. For against, it is preferable to select the material of the layer 16 a material with properties for bonding by molecular adhesion are similar to those of the material of the layer 12, whether a hydrophilic molecular adhesion or hydrophobic.

p0047The <figref idrefs="f0001">4A</figref> shows a similar structure to that of <figref idrefs="f0001">3</figref>, The roughness of the upper surface of substrate 30 being however enhanced or exaggerated.

p0048The adhesion layer 22 was polished to be flush with the upper peaks 32, 36 of the substrate surface 30. These spikes will create thermal conduction channels which will promote heat transfer between the silicon layer 24 and the substrate 30.

p0049According to a variant, illustrated in <figref idrefs="f0002">4B</figref>, The surface 25 of the adhesion layer 22 is located at a maximum of 10 nm or maximum peaks or asperities of the substrate, to best promote heat transfer by the peaks or asperities then by the substrate.

p0050Such thickness or distance can be measured at any time, for example by ellipsometry, even in preparation of the adhesion layer.

p0051The roughness of the substrate are operated to promote heat transfer between the upper layers of the structure, which contain electronic components, and the base substrate.

p0052In the case of diamond, the heat transfer between the upper silicon layer and the diamond substrate is improved by a factor of about 60.

p0053It follows that the operation of components formed in the layer 24 itself is improved. Such components can be power components, which give off significant heat output, such as IGBT, components and / or MOSFET, and / or RF components (for fast operation).

p0054Typically, the adhesion layer 12,22 has, after polishing, a thickness of for example 5 nm and 50 nm, and the intermediate layer 16, 26 has a thickness between 5 nm and 20 nm.

p0055A method for producing a component according to the invention will be described in connection with the <figref idrefs="f0003">5A to 5D</figref>.

p0056The <figref idrefs="f0003">5A</figref> 10 shows a substrate whose roughness is greatly exaggerated. Such a substrate has not undergone polishing treatment, or can not be polished and has a roughness or surface micro-roughness greater than the limit value accepted by the molecular bonding, eg roughness or micro surface -rugosité between 5 nm RMS (or 20 or 30 nm RMS) and 100 nm RMS.

p0057An intermediate layer 26 by Si₃NOT₄, Is formed on the substrate.

p0058This layer follows the roughness of the upper surface of the substrate. It is for example deposited by PECVD, or LPCVD technique.

p0059It is then proceeded to the formation of an adhesion layer, for example a silicon dioxide layer SiO₂. Preferably, the initial thickness of this layer is greater than 2.8 or 3 times the value of the roughness of the substrate surface 30, in order to have a flat layer after polishing.

p0060For example, this layer initially will have a value between 0.5 and 1 micron, or between 0.5 and 10 .mu.m.

p0061This adhesion layer is then subjected to a polishing treatment, for example, by chemical mechanical polishing. Some methods, such as the STI process (described for example in the article by<nplcit id="ncit0004" npl-type="s"><text>CP Chang et al. "A highly manufacturable Corner Rounding Solution for 0, 18 microns Shallow Trench Isolation", IEDM 97 - p.661</text></nplcit>) Have a high selectivity between the nitride 26 and the oxide layer 22. Such selectivity permits to flatten the layer 22 until the layer 26 is reached, the latter then acting as a stop layer in the process planarizing.

p0062A layer or a silicon substrate 24 may then be attached or bonded to the layer 22 by wafer bonding, according to known techniques, for example described in the Tong Gösele and work already cited above.

p0063It is possible to make the accession of a silicon substrate and to achieve a thin layer thinning and polishing the substrate, or using the technique called "SMART CUT" for example described in the article <nplcit id="ncit0005" npl-type="s"><text>AJ Auberton - Hervé et al. "Why can Smart-Cut change the future of microelectronics" published in Journal of High Speed ​​Electronics and Systems, Vol.10, No.1 (2002), p.131 - 146</text></nplcit>.

p0064According to yet another technique, is used the formation of a porous layer forming sillicium embrittlement plane, for example as described in the article by <nplcit id="ncit0006" npl-type="s"><text>K.Sataguchi et al. "If ELTRAN by Splitting Porous layers", Proceedings of the 9th International Symposium on Silicon-on-Insulator Tech. and Device, 99-3, The Electrochemical Society, Seattle, p.117 -121 1999</text></nplcit>.

p0065This results in a structure as that of the <figref idrefs="f0003">5D</figref>, Similar to the <figref idrefs="f0001">4A</figref>.

p0066Components can then be made in the layer 24, in particular power or RF components, for which the substrate 10 can eliminate the heat produced during their operation.

p0067Another example of embodiment of the invention is illustrated in <figref idrefs="f0002">6</figref>.

p0068It relates to the connection between a substrate 40 or 40 of high roughness layer (greater than 0.4 nm RMS or RMS 0.5 nm, for example between 1 nm and 100 nm RMS RMS), or hardly polishable or having a chemistry hardly compatible with molecular bonding, and a substrate layer 50 or 50 having the same properties. For example, the substrate 40 is in the diamond while the substrate 50 is made of diamond or AlN (aluminum nitride).

p0069On each substrate, an adhesion layer 42, 52 is formed, as already explained above, directly or with an intermediate layer, also as already explained above. Each of these adhesive layers is for example silicon dioxide. It is then possible to establish a connection by molecular adhesion between these two layers of adhesion.

p0070This method is particularly interesting in the case where at least one of the two materials is hardly polishable and is chemically inert, in the sense indicated above.

p0071All that has been explained above remains valid, replacing the layer of silicon or semiconductor material with a rough substrate assembly - layer adhesion.

p0072More generally, the invention also relates, as illustrated in <figref idrefs="f0002">7</figref>The connection between a substrate 40 or 40 hardly polishable layer or high roughness, in any case greater than 0.5 nm RMS, for example between 1 nm and 100 nm RMS RMS or having a chemistry incompatible with bonding molecular adhesion, and a substrate 60 or a layer 60 having a chemistry and a roughness compatible with bonding by molecular adhesion, roughness being less than 0.5 nm rms.

p0073On the substrate 40, an adhesion layer 42 is formed directly or with an intermediate layer as explained above. The adhesive layer is for example of silicon dioxide. It is then possible to establish a connection by molecular adhesion between the adhesion layer and the layer or substrate 60.

p0074All that has been explained above remains valid, replacing the layer of silicon or semiconductor material by the layer or the substrate 60.

p0075In these last two cases, the material of each substrate hardly polishable, or roughness greater than 0.5 nm RMS, or chemistry incompatible with bonding by molecular adhesion may for example be selected from the materials already mentioned above ( diamond, aluminum nitride AIN).