Recording and reproduction of video signals

0001The present invention relates generally to recording and reproduction of video signals, and can be applied to apparatus for recording and reproducing digital video signals, and more particularly, though not exclusively, to a recording and reproduction apparatus provided with high-efficient encoding apparatuses and decoding apparatuses, disk and other data storage apparatuses, high speed data transmission media, line switching apparatuses, etc.

0002In the past, in the preparation of a news video in a broadcasting station, for example, the original video data recorded by cameras etc. with built-in video tape recorders were kept separate from each other recorded on tape.

0003An editor would then play back the tapes on which the original video data were recorded as needed using a video tape player in the editing room and combine parts of several of the reproduced original video data on a separate tape so as to prepare the news video for the actual broadcast.

0004When managing original video data in the form of the tapes on which they are respectively recorded, however, in particular when using a large number of original video data to prepare a single news video, the work efficiency was poor when selecting the necessary parts from the large number of original video data. Further, it was necessary to bring the tapes on which the original video data were recorded from their place of storage to the editing room. Also, it was not easy for a number of editors to make use of the original video data at the same time.

0005Further, news videos prepared on tapes are generally carried to and loaded in a video tape player for transmission use or a cart machine in which it is built in. The management of the news videos at the transmission stage and the procedures when changing the order of transmission were not easy to perform efficiently and with a high reliability.

0006<patcit id="pcit0001" dnum="WO9222983A"><text>WO 92/22983</text></patcit> describes a multi-source recorded player.

0007<nplcit id="ncit0001" npl-type="b"><text>Alan Debreil and Phillipe Oddo, "Synchronous designs in VHDL", Design Automation Conference, 1993, IEEE Comput. Soc. 20 September 1993, pages 486-491</text></nplcit>, describes synchronous designs in VHDL.

0008Aspects of the present invention are set out in the appended claims.

0009Embodiments of the present invention provide a video signal recording and reproduction apparatus with few limitations as to the system size and expandability. Further embodiments of the present invention provide a video signal recording and reproduction apparatus which accurately synchronizes with an external synchronization signal.

0010Further embodiments of the present invention provide a video signal recording and reproduction apparatus which operates with a good response with respect to requests from an editing apparatus without being influenced by the transfer capability of the computer network.

0011Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings in which: <ul id="ul0001" list-style="none" compact="compact"><li><figref idref="f0001">Fig. 1</figref> is a block diagram of an example of the configuration of a video signal server system based on a concept similar to a server system used in a computing system;</li><li><figref idref="f0002">Fig. 2</figref> is a block diagram of a video signal recording and reproduction apparatus according to a first embodiment of the present invention;</li><li><figref idref="f0003">Fig. 3</figref> is a block diagram of an example of a data storage apparatus in a video signal recording and reproduction apparatus shown in <figref idref="f0002">Fig. 2</figref>;</li><li><figref idref="f0004">Fig. 4</figref> is a block diagram of an example of a synchronous system control execution apparatus in a video signal recording and reproduction apparatus shown in <figref idref="f0002">Fig. 2</figref>;</li><li><figref idref="f0005">Fig. 5</figref> is a flow chart of an example of the operation of the CPU 2 in the synchronous system control execution apparatus shown in <figref idref="f0004">Fig. 4</figref>;</li><li><figref idref="f0006">Fig. 6</figref> is a block diagram of a video signal recording and reproduction apparatus according to a second embodiment of the present invention; and</li><li><figref idref="f0007">Fig. 7</figref> is a block diagram of a video signal recording and reproduction apparatus according to a third embodiment of the present invention.</li></ul>

0012<figref idref="f0001">Figure 1</figref> is a view of an example of the configuration of a server system for a video signal by a concept similar to the server system used in a computing system.

0013As shown in <figref idref="f0001">Fig. 1</figref>, the server system 500 is basically comprised of basic computer components such as a CPU 501, ROM 502, and RAM 503, a high speed bus 504, data storage apparatuses 506-1 to 506-m connected through device interfaces 505-1 to 505-m, video signal high-efficient encoding apparatuses 508-1 to 508-n connected through input/output interfaces 507-1 to 507-n, and video signal decoding apparatuses 509-1 to 509-n corresponding to the same.

0014When the host application system is realized on a separate computer, a LAN interface 511 is provided for connecting a LAN 510 and system 500.

0015In the system 500, when recording a video signal, the input video signal S50 is encoded at a high efficiency in the video signal high-efficiency encoding apparatus 508 and becomes the high-efficient encoded video data S51 which is transferred through the input/output interface 507 to the high speed bus 504. The high-efficient encoded video data transferred on the bus 504 is temporarily stored in the RAM 503 for ordinary data flow control etc., then is once again transferred to the bus 504 and is sent through the device interface 505 for recording in the data storage apparatus 506.

0016On the other hand, when reproducing a video signal, the high-efficient encoded video data which had been stored in the data storage apparatus 506 is reproduced through the device interface 505, then is transferred to the high speed bus 504. The high-efficient encoded video data transferred to the bus 504, in the same way as at the time of recording, is temporarily stored in the RAM 503, then is transferred to the bus 504 and is sent through the input/output interface 507 to become the input data S52 of the video signal decoding apparatus 509. The video signal decoding apparatus 509 decodes the video signal S53 from the input data S52 and outputs it from the system 500.

0017In the above recording and reproducing operations, the input/output interfaces 507-1 to 507-n, bus 504, and device interfaces 505-1 to 505-m all operate under the control of a CPU 501 which receives instructions from the application system through the LAN 510, LAN interface 511, bus 504, and RAM 503.

0018Note that when the operating instructions are supplied from the input/output side of the video signal rather than the application system, the control line S54 connected to the input/output interface 507 shown by the broken line in <figref idref="f0001">Fig. 1</figref> is necessary. In this case, the instructions supplied from the control line S54 are transmitted to the CPU 501 through the input/output interface 507, bus 504, and RAM 503 and are reflected in the control by the CPU 501.

0019The above is not necessarily suitable for realization of a server system assuming recording and reproduction of a high quality video signal handled in a broadcasting station of the configuration explained above for the following reasons.

0020A first point posing a hurdle in handling a video signal of a high quality of a level usable in a broadcasting station is the restriction on the system size and its expandability caused by the insufficient data transfer capability of the buses.

0021The speed of the data obtained by digitization of a current television video signal is at least 100 Megabits/second. Even the speed of video signal high-efficient encoded data obtained by high-efficient encoding of this, assuming deterioration caused by the editing, would be about 30 Megabits/second, that is, 4 Megabytes/second, as described for example in CCIR

Recommendation 733.

0022Therefore, for example, if desiring to realize a system enabling eight editors to make joint use of original video data and enabling so-called "AB roll" editing where two sets of data are accessed simultaneously, then, considering also the interposition of the RAM 503, there would be a total of 48 series of video signal high-efficient encoded data on the bus 504 at the same time, that is, 3 (for reproducing two sets of data simultaneously and recording one edited video) x 2 (travel to and from the RAM) x 8 (number of editors). Accordingly, the bus would have to have an effective transfer speed of 192 Megabytes/second just for the video signal high-efficient encoded data.

0023Further, there is the restriction inherent to a server system for a video signal for a broadcasting station that the transfer of data to the input/output interface must be instantaneous. The processing capability of the CPU controlling the bus and RAM therefore also becomes a problem.

0024In addition, the physical transfer speed of a bus in a general high performance computer is about 100 Megabytes. Even a system of a size enabling at most eight editors to make joint use of original video data would not necessarily be easy to realize technically speaking. Further, even if realized, it would be necessary to construct special hardware, which would not be rational cost-wise.

0025A second point posing a hurdle in realization of a system usable in a broadcasting station is the synchronization dependency of the system to external synchronization.

0026Normally, in a system in a broadcasting station, a video signal is transmitted and sent out in strict synchronization with the reference synchronization signal for the video signal, so to facilitate connection with existing apparatuses, it is necessary that the video signal of the server system be input and output in synchronization with the reference synchronization signal. It is not necessarily easy to realize this by a system configured about a computer which basically operates asynchronously.

0027That is, in a configuration which transfers and switches data using an asynchronous bus and RAM, the video data which is inherently to be input and output in synchronization with the reference synchronization signal inevitably passes through an asynchronous system in that system and therefore synchronization/asynchronization conversion becomes necessary. This invites an increase in the size and cost of the equipment.

0028A third point posing a hurdle in realizing a system usable in a broadcasting station is the hurdle in operation caused by the system delays created during the processing for the transfer and switching of data using the asynchronous bus and RAM and the processing for synchronization/asynchronization conversion.

0029System delays become problems not only in the sense of the absolute amount of the delay in the editing work etc., but also as to if the amount of delay should be fixed or not in system automation designed based on time lines. Regarding the absolute amount of the delay, in the configuration of <figref idref="f0001">Fig. 1</figref>, for example, during reproduction, it is necessary to control the amount of flow of data using a memory at three locations, that is, the device interfaces 505-1 to 505-n, the RAM 503, and the input/output interfaces 507-1 to 507-n, so it is basically difficult to achieve the response performance demanded in editing work. Further, regarding fixing the amount of the delay, since the basic parts of the system operate asynchronously, this is not easy to guarantee.

0030A fourth point posing a hurdle in realizing a system usable in a broadcasting station is that when high speed transfer of data is required between data storage means so as to deal with possible breakdowns of data storage means, a sufficient speed of transfer cannot be secured due to the problem of bus capacity mentioned above.

0031Further, in the configuration of <figref idref="f0001">Fig. 1</figref>, data is transferred between data storages of different server systems through the LAN 510, but existing LANs have for example insert transfer capacities of 10 Megabits/second or so and therefore require a long time for transfer, so are not suited to practical use.

0032A fifth point posing a hurdle in realizing a system usable in a broadcasting station is that when the data is recorded and reproduced in and from the server system under the control of for example an external control apparatus, the above-mentioned problems of synchronization and delay occur.

0033When realizing such a system, it is necessary to connect a special control line S54 as shown by the broken line of <figref idref="f0001">Fig. 1</figref> for example to the input/output interfaces 507-1 to 507-n, but in this case the control instructions are sent through the bus 504 to the CPU 501 and then through the bus 504 to the device interfaces 505-1 to 505-m and the input/output interfaces 507-1 to 507-n, so delay ends up being caused in the transmission of the instructions themselves.

0034Further, even if delay-free control were possible, practical operation could not be achieved unless solving the problem of the system delays in the data.

0035A sixth point posing a hurdle in realizing a system usable in a broadcasting station is that in a server system configured about a direct extension of the computer technology of the prior art, the data is transferred and switched using a bus and RAM, so the above-mentioned problems in bus capacity etc. make the transfer and switching of deterioration-free baseband-frequency digital video signals difficult and force high-efficient encoding of all video signals.

0036High-efficient encoding is a superior technique when it comes to the effective utilization of hardware resources, but there is original video data for which application of high-efficient encoding will cause problems in the quality of the video signal. While rare, it is possible that the quality of the video signal will become a level not acceptable to the broadcasting system.

0037<figref idref="f0002">Figure 2</figref> is a block diagram of a video signal recording and reproduction apparatus according to a first embodiment of the present invention.

0038In <figref idref="f0002">Fig. 2</figref>, digitalized input video signals S10 are input to the variable encoding efficiency video signal high-efficient encoding apparatuses 10-1 to 10-n where they are encoded at a high efficiency and become the high-efficient encoded video data S11a.

0039The encoding efficiencies of the video signal high-efficient encoding apparatuses 10-1 to 10-n are set in advance by the control signals S12 supplied from the synchronous system control execution apparatus 16.

0040If the high-efficient encoding apparatuses 10-1 to 10-n extract the clocks and frame timing from the input video signals S10 and use them internally, then it would become possible to input the video signals in synchronization with the video signal synchronization signal.

0041The high-efficient encoded video data S11a are input to a line switching apparatus 11 such as a routing switcher for a broadcasting station. In the line switching apparatus 11, the destination of the line switching operation is set by a control signal S13 supplied from the synchronous system control execution apparatus 16. Accordingly, the high-efficient encoded video data S11a input to the line switching apparatus 11 are transmitted to the predetermined data storage apparatus 12 connected by the set route as input high-efficient encoded video data S11b.

0042The high-efficient encoded video data S11b are recorded in the independently controlled data storage apparatuses 12-1 to 12-n by a control signal S14 supplied from the synchronous system control execution apparatus 16.

0043The data storage apparatuses 12-1 to 12-n are each comprised, as shown for example in <figref idref="f0003">Fig. 3</figref>, by a data and control format conversion apparatus 121 and a general use disk apparatus 122.

0044In <figref idref="f0003">Fig. 3</figref>, the high-efficient encoded video data S11b transferred by a data transmission medium able to transfer a baseband-frequency digital video signal is input to the data and control format conversion apparatus 121 where it is converted to a format able to be input to the disk apparatus 122, for example, a format according to the SCSI format.

0045On the other hand, the data reproduced from the disk apparatus 122 is input to the data and control format conversion apparatus 121 where it is converted to the same data format as at the time of recording and becomes the reproduced high-efficient encoded video data S15a which is transmitted by a data transmission medium able to transmit a baseband-frequency digital video signal.

0046The data and control format conversion apparatus 121 converts the control format to a format able to control the disk apparatus 122 in accordance with a control signal S14 supplied from the synchronous system control execution apparatus 16.

0047By configuring the system in this way, the data and control format conversion apparatus 121 and the general use disk apparatus 122 can be connected through a general use connection line S120 carrying a mixture of data and control signals and recording and reproduction of encoded video data becomes possible using a general use disk apparatus.

0048Further, by configuring the system in this way, the data storage apparatus 12 can be changed in the speed of recording and reproduction up to the extent of the maximum data transfer speed of the disk apparatus 122.

0049Note that as the disk apparatus 122, use may be made of a magnetooptic (MO) disk apparatus, hard disc apparatus, etc.

0050The reproduced high-efficient encoded video data S15a is input to the line switching apparatus 11 in the same way as at the time of recording. In the line switching apparatus 11, the destination of the line switching operation is set by a control signal S13 supplied from the synchronous system control execution apparatus 16. Accordingly, the high-efficient encoded video data S11a input to the line switching apparatus 11 are conveyed to the predetermined video signal decoding apparatuses 13-1 to 13-n connected by the set route as the high-efficient encoded video data S15b.

0051The high-efficient encoded video data S15b are decoded in the video signal decoding apparatuses 13-1 to 13-n into the decoded video signals S16 which are then for example output to an editing apparatus.

0052In the example of <figref idref="f0002">Fig. 2</figref>, no control signal was input to the video signal decoding apparatuses 13, but this was because this type of decoding apparatus is configured to automatically be slaved to changes in the encoding efficiency.

0053Further, in the control system of this system, first, a plurality of independent control instructions S17a issued from a host application system 14 comprised of one or more computers are successively transferred through a LAN to a control instruction transfer apparatus 15 usually comprised of a single computer in the form based on the general purpose protocol.

0054The control instruction transfer apparatus 15 transfers to the synchronous system control execution apparatus 16 the control instructions S17b obtained by protocol conversion for enabling communication with the synchronous system control execution apparatus 16.

0055The synchronous system control execution apparatus 16 is comprised, for example as shown in <figref idref="f0004">Fig. 4</figref>, of a plurality of computers (hereinafter referred to as "CPU units") 160-1 to 160-n.

0056The CPU units 160-1 to 160-n are each basically comprised of a communication interface 161, the basic computer components of a CPU 162, ROM 163, and RAM 164, and a control interface 165 connected to a bus 166 operating under the control of the CPU 162.

0057The plurality of CPU units 160-1 to 160-n are joined by connecting the communication bus 167 and communication interface 161. The communication bus 167 is connected to a control instruction transfer apparatus 15 for transfer of control instructions S17b.

0058In the CPU units 160-1 to 160-n, a video signal reference synchronization signal S18 is supplied to the control interface 165.

0059The control interface 165 is configured so as to handle the control for a number of controlled apparatuses. For example, it is configured to have control lines 168 enabling input and output of a plurality of control signals such as the control signals S12, S13, and S14 shown in <figref idref="f0002">Fig. 2</figref>.

0060The video signal reference synchronization signal S18, as shown in <figref idref="f0004">Fig. 4</figref>, may be supplied to the communication interface 161 as well and be put to use for achieving high speed communication or fixing the delay time caused due to the communication.

0061Further, it is also possible to supply some sort of time information such as a station time code in addition to the video signal reference synchronization signal S18 so as to enable control based on a time line.

0062In the configuration of <figref idref="f0004">Fig. 4</figref>, first a control instruction S17b is supplied from the control instruction transfer apparatus 15 to the communication bus 167.

0063The communication interface 161 of each of the CPU units 160-1 to 160-n fetches the control instructions which the unit is to process from the communication bus 167 and transfers them to the internal bus 166. The control instructions fetched to the internal bus 166 are converted to instructions for real time control for actually controlling the devices and are transferred to the control interface 165.

0064At the control interface 165, the video signal reference synchronization signal S18 is referred to and the devices are communicated with by, for example, an accurate timing within a frame period so as to realize control by for example the control signals S12, S13, and S14 such as shown in <figref idref="f0002">Fig. 2</figref>. By this, the encoding efficiencies of the video signal high-efficient encoding apparatuses 10-1 to 10-n are set, the lines connecting the video signal high-efficient encoding apparatuses 10-1 to 10-n or the video signal decoding apparatuses 13-1 to 13-n and the data storage apparatuses 12-1 to 12-n are set or switched under the control of the line switching apparatus 11, and the operation of the data storage apparatuses 12 at the time of recording and reproduction is controlled.

0065Further, the CPU units 160-1 to 160-n supply the devices with real time control commands based on the flow chart shown in <figref idref="f0005">Fig. 5</figref>.

0066At step ST1, the operation is started.

0067At step ST2, the communication interface 161 fetches the control commands to be processed from the communication bus 167 and transmits them to the internal bus 166.

0068At step ST3, the CPU 162 converts the control commands fetched into the internal bus 166 into real time control commands for controlling the devices.

0069At step ST4, the real time control commands are supplied to the devices through the control interface and at step ST5, the operation is ended.

0070In such a configuration, by making the communication bus 167 and communication interface 161 and the control interface 165 operate in synchronization with the video signal reference synchronization signal S18 and, further, limiting the processing in the CPU 162, ROM 163, and RAM 164, fixing the amount of system delay relating to the control inside the synchronous system control execution apparatus 16 to units of frame periods becomes easy.

0071Further, the control interface 165 gives priority to issuing control signals at accurate timings in synchronization with the video signal reference synchronization signal S18, so it becomes possible to easily satisfy the conditions relating to the timing of control signals, which differ depending the devices and require accuracy.

0072Further, by giving an extra leeway to just the communication capacity of the communication bus 167, it becomes possible to easily expand the synchronous system control execution apparatus 16 by increasing the number of the CPU units 160, so the flexibility of the number of the devices and apparatuses under the control of the synchronous system control execution apparatus 16 is maintained and as a result the expandability of the scale of the system is maintained.

0073Further, the following operation is performed when the data transfer instructions are issued from a host application system 14.

0074That is, the data transfer control instructions S17a issued from the host application system 14 are transferred to the control instruction transfer apparatus 15 where they are converted in protocol to enable communication with the synchronous system control execution apparatus 16.

0075The synchronous system control execution apparatus 16 follows the control instructions S17b obtained by protocol conversion, refers to the video signal reference synchronization signal, controls the reproduction side data storage apparatus 12(a), line switching apparatus 11, and recording side data storage apparatus 12(b) at a suitable timing, and executes the transfer of data between the data storage apparatuses 12.

0076Here, a data storage apparatus on the reproduction side among the plurality of data storage apparatuses 12-1 to 12-n is designated as 12 (a) and a data storage apparatus on the recording side is designated as 12(b).

0077When transferring data between data storage apparatuses 12, the reproduction side data storage apparatus 12(a) is controlled by the control signal S14 to reproduce the stored data and output the reproduced data train S15a. The reproduced data train S15a is input to the line switching apparatus 11, such as a broadcasting station use routing switcher, where it is switched as set in advance by the control signal S13, is connected to the recording side data storage apparatus 12(b), and becomes the input data S11b. The input data S11b is recorded in the data storage apparatus 12(b) by the control signal S14.

0078Further, by performing the logical switching of control signals using a function of setting a control signal line connecting any devices of the synchronous system control execution apparatus 16 shown in <figref idref="f0004">Fig. 4</figref>, it becomes possible to realize the transfer of control instructions between any devices included in a lower system and high speed transfer of control instructions from outside the lower system through the control signal line without having to go through the host application system 14.

0079In this case, the following operation is performed.

0080For example, by having the logical circuit setting instructions S17a for transfer of control instructions, issued from the host application system 14, be transferred to the control instruction transfer apparatus 15 and having the synchronous system control execution apparatus 16 receiving the same allocate time slots of the communication bus 167 which the communication interface 161 of the CPU unit 160-1 and the communication interface 161 of the CPU unit 160-2 can make exclusive use of, it is possible to set a logical circuit for transfer of control instructions.

0081When transferring control instructions between the CPU unit 160-1 and the CPU unit 160-2, first, the control signal input from an apparatus connected to the control interface 165 of the CPU unit 161-1 is supplied to the internal bus 166 and then is immediately transferred to the communication interface 161 under the control of the CPU 162. The communication interface 161 sends the transferred control instructions to the communication bus 167. The control instructions sent to the communication bus 167 are transferred by the communication interface 161 of the CPU unit 160-2 to the internal bus 166 of the CPU unit 160-2, are immediately transferred to the communication interface 161 under the control of the CPU 162, and from there are supplied to the apparatus connected to the control interface 165 of the CPU unit 160-2.

0082By using the above system, it becomes easy to fix the amount of system delay relating to the control in the synchronous system control execution apparatus 16 to units of frame periods.

0083Further, the control interface 165 gives priority to issuing control signals at accurate timings in synchronization with the video signal reference synchronization signal S18 and therefore the conditions relating to the timing of control signals, which differ depending the devices and require accuracy, are easily satisfied. The controlled devices thereby operate smoothly even though there are system delays of units of frame periods.

0084In addition to the above mentioned system, it is possible to realize the transfer of control instructions between devices connected to the same control interface 165 by the configuration of <figref idref="f0004">Fig. 4</figref>.

0085In this case, for example, control instructions S161 from a control side (master) device are input to the control interface 165 and are returned once again to the control interface 165 through the bus 166 and RAM 164. The control interface 165 refers to the video signal reference synchronization signal S18 and issues control instructions S162 at an accurate timing in the same way as explained above.

0086<figref idref="f0006">Figure 6</figref> is a block diagram of a video signal server system according to a second embodiment of a video signal recording and reproduction apparatus of the present invention.

0087In the second embodiment, in addition to the configuration of the first embodiment shown in <figref idref="f0002">Fig. 2</figref>, a digital baseband-frequency video signal input S20 and digital baseband-frequency video signal output S21 are added to the line switching apparatus 11 of the system, an ordinary digital video tape recorder 20 for example is disposed in line with the data storage apparatuses 12, and therefore both digital baseband-frequency video signals and high-efficient encoded video data are recorded and reproduced in the same system.

0088Further, it is possible to once record a digital baseband-frequency video signal as it is at the digital video tape recorder 20 and, when needed, reproduce it and perform high-efficient encoding using the video signal high-efficient encoding apparatus 10, and record the result in the data storage apparatuses 12 for use. At this time, a digital baseband-frequency video signal output from the line switching apparatus 11 is supplied through the transmission line S21a to the input terminal of the video signal high-efficient encoding apparatus 10-n.

0089Further, for control, the data storage apparatus 12 and the digital video tape recorder 20 are switched. The control may be performed in the same way as with the case of the first embodiment explained above except for the control for the video signal high-efficient encoding apparatuses 10-1 to 10-n and the video signal decoding apparatuses 13-1 to 13-n.

0090As explained above, in embodiments of the video signal recording and reproduction apparatus of the present invention, by giving flexibility to the size of the control system, it becomes possible to easily and inexpensively configure a system with far fewer restrictions as to the system size and expandability than in the past.

0091As a result, for example, in the system of a broadcasting station, it becomes possible to construct a server system of the optimal size for the scale of the work in the broadcasting station or the type of the work using the system in the same station and, further, it becomes possible to easily change the size and functions of the system.

0092Further, with embodiments of the invention, since the video signal is input and output in strict synchronization with the video signal reference synchronization signal and the data is transferred and exchanged inside the system, it becomes possible to more easily construct a system with a high compatibility with existing apparatuses and systems in a system in a broadcasting station than in the past.

0093Further, in embodiments of the invention, since the locations where delay is caused in the system can be drastically cut and a system configuration can be obtained enabling the delay to be quantized to a fixed amount, it becomes possible to more easily configure a system for a broadcasting station requiring a high control response capability than in the past.

0094Further, in embodiments of the invention, since it is easy to transfer and switch data at a high speed and independently so that the data is transferred between data storage apparatuses in a manner not detectable by the system user, it becomes possible to more efficiently copy a video signal in a system in a broadcasting station than in the past.

0095Further, in embodiments of the invention, since provision is made of a function by which the external control instructions themselves are directly switched and high speed transfer of the control instructions becomes possible, it becomes possible to more easily configure a system where high speed response is required, such as due to editing in a broadcasting station, than in the past.

0096Further, in embodiments of the invention, since it is possible to configure the system so as to enable free transfer and switching of data even in the state of a deterioration-free baseband-frequency digital video signal, it becomes easy to rationally operate the system in a manner never before seen, where for example recording is performed in a digital video tape recorder once in the state of the digital baseband-frequency video signal as it is and then, when necessary, this is reproduced and used subjected to high-efficient encoding at an encoding efficiency giving the picture quality commensurate with the application.

0097Next, an explanation will be made of a third embodiment of the present invention using a plurality of editing apparatuses as the application system 14 shown in <figref idref="f0002">Fig. 2</figref> and <figref idref="f0006">Fig. 6</figref>.

0098<figref idref="f0007">Figure 7</figref> is a block diagram of an embodiment of a video editing system according to the present invention. Constituent portions the same as in <figref idref="f0002">Fig. 2</figref> are shown by the same reference.

0099That is, this video editing system is comprised of the video signal high-efficient encoding apparatuses 10-1 to 10-n, line switching apparatus 11, data storage apparatuses 12-1 to 12-n, video signal decoding apparatuses 13-1 to 13-n, editing apparatuses 14a-1 to 14a-n, control instruction transfer apparatus 15, synchronous signal control execution apparatus 16, computer network 17, and control signal switching apparatus 18.

0100The editing apparatuses 14a-1 to 14a-n are each configured by one or more computers. When reproducing material etc., they designate the addresses of the video data required at the computer network 17 and output requests for operation, such as reproduction or stopping, that is, the AV equipment control signals S18, to the control signal switching apparatus 18 by a route different from the computer network 17.

0101The AV equipment control signals S18 are based on a so-called "9 protocol". Control signals are sent and signals responding to the same are received in one frame.

0102The control signal switching apparatus 18 receives the control signals S18 output from the synchronous signal control execution apparatus 16 based on the address designation of the editing apparatuses 14a-1 to 14a-n, switches the destination of the output of the AV equipment control signals S18 output from the editing apparatuses 14a-1 to 14a-n, and cause the signals to be input to the desired one of the data storage apparatuses 12-1 to 12-n.

0103Note that the data storage apparatuses 12-1 to 12-n, for example, as shown in <figref idref="f0003">Fig. 3</figref>, are each configured of a data and control format conversion apparatus 121 and general use disk apparatus 122.

0104In <figref idref="f0003">Fig. 3</figref>, the high-efficient encoded video data S11b transmitted by a data transmission medium able to transmit a baseband-frequency digital video signal is input to the data and control format conversion apparatus 121 where it is converted to a format enabling input to a disk apparatus 122.

0105On the other hand, the data reproduced from the disk apparatus 12 is input to the data and control format conversion apparatus 121 where it is converted to the same data format as at the time of recording and becomes the reproduced high-efficient encoded video data S15a transmitted by a data transmission medium able to transmit a baseband-frequency digital video signal.

0106The data and control format conversion apparatus 121 is changed in control format to a format enabling control of the disk apparatus 122 in accordance with control signals S14 from the synchronous signal control execution apparatus 16.

0107By adopting this configuration, the data and control format conversion apparatus 121 and the general use disk apparatus 122 can be connected through a general use connection line S120 carrying a mixture of ordinary data and control signals and recording and reproduction of encoded video data becomes possible using a general use disk apparatus 122.

0108Further, by adopting this configuration, the data storage apparatus 12 can be changed in the speed of recording and reproduction to the extent of the maximum data transfer speed of the disk apparatus 122.

0109Note that as the disk apparatus 122, use may be made for example of a magnetooptic (MO) disk apparatus.

0110Further, it is possible to configure a system having an SCSI or other general use interface and including a disk changer. In this case, the disk charger is controlled by control signals S14a from the synchronous signal control execution apparatus 16.

0111Next, an explanation will be made of the operation by the above configuration.

0112First, the digitalized input video signals S10 are input to the variable encoding efficiency video signal high-efficient encoding apparatuses 10-1 to 10-n where they are encoded at a high efficiency and become the high-efficient encoded video data S11a.

0113The encoding efficiencies in the video signal high-efficient encoding apparatuses 10-1 to 10-n are set in advance by the control signals S12 from the synchronous signal control execution apparatus 16.

0114Further, if the high-efficient encoding apparatuses 10-1 to 10-n extract the clocks and frame timing from the input video signals S10 and use them internally, then it would become possible to input the video signals in synchronization with the video signal synchronization signal.

0115The high-efficient encoded video data S11a is input to a line switching apparatus 11 such as a routing switcher of a broadcasting station. In the line switching apparatus 11, the destination of the line switching operation is set by the control signals S13 from the synchronous signal control execution apparatus 16. Accordingly, the high-efficient encoded video data S11a input to the line switching apparatus 11 is conveyed as the input high-efficient encoded video data S11b to the predetermined data storage apparatus 12 connected by the set route.

0116The high-efficient encoded video data S11b is recorded in the data storage apparatuses 12-1 to 12-n, which are separately controlled by the control signals S14 from the synchronous signal control execution apparatus 16.

0117In this way, when decoding a video signal recorded in the data storage apparatuses 12-1 to 12-n and editing by any of the editing apparatuses 14a-1 to 14a-n, the address of the material, that is, the video data, which is required by the editing apparatus 14a-1 for example, configured by one or more computers, is sent as the control signal S17a through the computer network 17 to the control instruction transfer apparatus 15. The requests for operation such as reproduction or stopping, that is, the AV equipment control signals S18, are output to the control signal switching apparatus 18 by a different route from the computer network 17.

0118The control signals S17a are successively transferred through a LAN to the control instruction transfer apparatus 15, usually configured of a single computer, in a form based on the general use protocol.

0119The control instruction transfer apparatus 15 transfers to the synchronous signal control execution apparatus 16 the control instructions S17b obtained by protocol conversion for enabling communication with the synchronous signal control execution apparatus 16.

0120In the synchronous signal control execution apparatus 16, control signals S13 are output to the line switching apparatus 11 in accordance with the content of the control instructions S17b and the destination of the line switching operation is set. Control signals S14a setting the route of the control signals to the data storage apparatus 12-2 in which the data whose address is designated is recorded are output to the control signal switching apparatus 18 from the synchronous system control execution apparatus.

0121In the control signal switching apparatus 18, the control signals S14a output from the synchronous signal control execution apparatus 16 are received and the destination of the output of the AV equipment control signals S18 output from the editing apparatus 14a-1 is switched. Due to this, the operation requests to the desired data storage apparatus 12-1, such as for reproduction or stopping, that is, the AV equipment control signals S18, are sent to the data storage apparatus 12-2 in which the video data to be reproduced is recorded.

0122As a result, high-efficient encoded video data S15a is reproduced from the data storage apparatus 12-2 receiving the control signals S18.

0123The reproduced high-efficient encoded video data S15a is input to the line switching apparatus 11 in the same way as at the time of recording. In the line switching apparatus 11, since the destination of the line switching operation is set by the control signals S13 from the synchronous signal control execution apparatus 16, the reproduced high-efficient encoded video data S15a input to the line switching apparatus 11 is conveyed as the high-efficient encoded video data S15b to the predetermined video signal decoding apparatus 13-1 connected through the set route.

0124The high-efficient encoded video data S15b is decoded in the video signal decoding apparatus 13-1 to the restored video signal S16 which is then output to the editing apparatus 14a-1. Due to this, the predetermined editing may be performed in the editing apparatus 14a-1.

0125As explained above, according to the present embodiment, data is designated from the editing apparatuses 14a-1 to 14-a-n at the server control system, that is, the control instruction transfer apparatus 15, through the computer network 17, and control signals S18 showing operation requests, such as for reproduction or stopping, are output to the control signal switching apparatus 18 by a route different from the computer network 17. In the control signal switching apparatus 18, the route of transmission of the control signals S18 is switched based on control signals S14a from the synchronous signal control execution apparatus 16 to transfer the operation requests, that is, control signals S18, to the desired data storage apparatus 12-1 to 12-n. Therefore, it is possible to realize a video editing system which can immediately respond to requests from a plurality of editing apparatuses, not just a single editing apparatus, without being affected by the transfer capability of the computer network.

0126As explained above, according to video editing systems embodying the invention,it is possible to immediately respond even to requests from a plurality of editing apparatuses, not just a single editing apparatus, without being affected by the transfer capability of the computer network.