Time division multiplexed link connections between a switching matrix and a port in a network element

The present invention relates to telecommunication network elements, typically ADMs (Add/Drop Multiplexers) or DXC (Digital Cross-connects). In particular, the present invention relates to a port device for connecting input flows to a switching matrix (also known as switching fabric) and a method for providing a plurality of input flows to a switching matrix in a network element. Furthermore, the present invention relates to a backpanel frame for transmitting input flows to a switching matrix.

As it is known, an ADM is a network element that provides access to all, or some subsets, of the constituent signals contained within an STM-N. The constituent signals are added to or dropped from the STM-N signal as it passes through the ADM.

Digital cross-connect systems are commonly employed to controllably rearrange and redirect the contents of signals being communicated in digital transmission systems. However, with ever increasing demands for larger transmission capacity, there is a need for increasingly larger capacity non-blocking switch units used in the cross-connect switching fabric. In particular, there is the need to provide a fabric switch whose capacity can be easily varied.

In network elements, input flows are received at ports and sent to a switching matrix through backpanel connections. After a cross-connection is carried out at such a switching matrix, the properly cross-connected data are sent to output ports.

Several different arrangements are known for providing a switching matrix with data from a port. Unfortunately, prior art solutions are focused on specific applications, for instance for transporting only SONET or SDH or OTN payload. Furthermore, the known arrangements are typically derived from standard frame formats and thus they are not optimized for efficient, flexible, agnostic and scalable architectures.

The Applicant has felt the need to provide an agnostic arrangement having the capability to cross-connect both High Order SONET/SDH tributaries and ODUx tributaries.

The Applicant has also felt the need to provide an arrangement allowing a scalable "word slice" approach maximizing the matrix capacity and minimizing complexity and power dissipation of the switching matrix.

In addition, the Applicant has felt the need to provide a link protection between port and switching matrix.

These and further objects are obtained by the port, the method and the frame according to claim 1, 7 and 13, respectively. Further advantageous features are set forth in the dependent claims. All the claims are deemed to be an integral part of the present description.

According to a first aspect, the present invention provides an input port to a number of switching matrices of a network element or the like through a number of backpanel connections, the port receiving input flows in the form of bits arranged in frames, the port comprising: a memory for storing a number of bytes belonging to a tributary; a slicer for slicing the stored bytes in a number of word structures and a backpanel framer for forming backpanel frames with said word structures, the number of said word structures being equal to the number of said switching matrices and the capacity of the input flow being equal to the capacity of the overall backpanel connection capacity.

Profitably, each of said backpanel frame comprises an overhead section and a payload section, the overhead section including a plurality of words and redundant data, the payload section including a plurality of words with redundant data.

According to one embodiment, said redundant data provide a forward error correction protection feature.

According to one preferred embodiment, eight bytes of one tributary are stored in the port memory, said eight bytes being arranged into four 2-bytes structures (four words) that are provided to four switching matrices through said backpanel connections. Preferably, the port memory does not store all said eight bytes, but transmits two bytes to each of the four matrices in a round robin fashion as soon as said two bytes are available.

Preferably, said switching matrices are time division multiplex (TDM) matrices.

According to a second aspect, the present invention provides a method for feeding a number of switching matrices of a network element or the like through a number of backpanel connections, the method comprising the steps of receiving input flows in the form of bits arranged in frames, storing a number of bytes belonging to a tributary; slicing the stored bytes in a number of word structures and forming backpanel frames with said word structures, the number of said word structures being equal to the number of said switching matrices and the capacity of the input flow being equal to the capacity of the overall backpanel connection capacity.

Profitably, the step of forming backpanel frames comprises the steps of providing an overhead section and a payload section, the overhead section including a plurality of words and redundant data, the payload section including a plurality of words with redundant data.

According to one embodiment, said redundant data provide a forward error correction protection feature.

According to one preferred embodiment, eight bytes of one tributary are stored in the port memory, said eight bytes being arranged into four 2-bytes structures (four words) that are provided to four switching matrices through said backpanel connections. Preferably, the port memory does not store all said eight bytes, but transmits two bytes to each of the four matrices in a round robin fashion as soon as said two bytes are available.

Preferably, said switching matrices are time division multiplex (TDM) matrices.

According to a third aspect, the present invention provides a backpanel frame structure for connecting at least one port to at least one switching matrix in a network element, the frame structure comprising an overhead section and a payload section, the overhead section including a plurality of words and redundant. data, the payload section including a plurality of words with redundant data.

According to one embodiment, said redundant data provide a forward error correction protection feature.

The present invention will become clear after reading the following detailed description, to be read with reference to the attached drawings, wherein: <ul id="ul0001" list-style="dash" compact="compact"><li>Figure 1 shows a single square switching matrix cross-connecting M flows, with each flow comprising T time slots;</li><li>Figure 2 shows an arrangement of four square switching matrices cross-connecting 4xM flows, with each flow comprising T time slots;</li><li>Figure 3 shows a first embodiment of backpanel frame according to the present invention;</li><li>Figure 4 shows a second embodiment of backpanel frame according to the present invention;</li><li>Figure 5 shows a third embodiment of backpanel frame according to the present invention; and</li><li>Figure 6 diagrammatically shows an input port according to one embodiment of the present invention.</li></ul>

With reference first to Figure 1, an elementary square TDM matrix is shown and designed as SWITCH. The matrix of Figure 1 comprises M input links, each link carrying T time slots. The cross connection capability is N x N, where N = M x T. Let's call C the capacity of each time slot in Mbit/s: the overall capacity of the elementary matrix of Figure 1 is then N x C.

By mapping a tributary in one or more time slots, it is possible to use the matrix of Figure 1 for different tributary bit rates. The number Nt of time slots required for each tributary is N_t = ┌f_T /C┐, where f_T is the tributary bit rate.

The Applicant has followed this novel approach for providing a higher capacity matrix arrangement. The basic idea consists in using multiple elementary TDM matrices in parallel. With k matrices in parallel the cross connection capability still is N x N but the capacity of the single equivalent time slot (made of k elementary time slots in parallel) is C_k=C x k. Each time slot is distributed through the k elementary matrices, and the tributaries are switched by the k matrices working in parallel. As an example, Figure 2 shows four switching matrices (k=4), designed A, B, C and D, respectively.

To exploit the flexibility of this kind of novel approach, a particular backpanel frame structure has been defined for the link between ports and matrices. In particular the port according to the present invention is connected to all the elementary matrices used in a specific configuration, through a link simply composed by an ordered structure of time slots handled by the matrix, plus some overhead for link management and communication between port and matrix. A first embodiment of backpanel frame according to the present invention is shown in Figure 3.

The frame according to Figure 3 is an 8 KHz frame with an overall frequency of 2,48832 Gbit/sec (equivalent to an STM-16 or OC-48 bit rate) transporting a synchronous transmission payload, typically SDH or SONET (AU4 or AU3). The backpanel frame of Figure 3 comprises a first portion with a frame alignment word (FAW), an overhead and a number of payload packets. In the embodiment of Figure 3, each word comprises 16 bits, namely two bytes. The frame alignment word comprises 48 words, the overhead comprises 192 words and each payload packet comprises 768 words (equivalent to 768 time slots); there are 25 of such packets.

As the capacity of each time slot (each word in a packet) is C=8000x25x16 bit/s = 3.2 Mb/s, it is possible to accommodate one AU3 (f_AU3=50.304 Mb/s) in 16 time slots, as C₁₆=16x3.2 Mb/s = 51.2 Mb/s. In this case, it is possible to built an AU3 switch with up to 16 matrices working in parallel, each one handling one of the 16 time slots; the resulting system is able to switch up to Mx768 AU3. Similarly, it is possible to build a system with (1) 2, 4, 8 matrices working in parallel, each one respectively handling (16) 8, 4, 2 time slots of a single AU3. The resulting systems will be able to switch respectively up to (Mx48) Mx96, Mx192, Mx384 AU3.

An AU4 is simply transported using three times the slots necessary for an AU3. The same applies for higher bit-rates tributaries. It is convenient to synchronize the SDH/SONET tributaries to the backpanel frame: this can be achieved with pointer processing, putting an SDH/SONET Section adaptation function on the port; moreover, as C₁₆&gt;f_AU3, some bits in the time slots will contain fixed stuffing.

The frame according to Figure 4 is a 2,7648 Gbit/sec frame (8 KHz periodicity) transporting a synchronous transmission payload, typically SDH or SONET. The backpanel frame of Figure 4 comprises a first portion with a frame alignment word (FAW), a stuffing portion, an overhead and a number of payload packets. In the embodiment of Figure 4, each word comprises 16 bits, namely two bytes. The frame alignment word comprises 48 words, the overhead comprises 204 words and each payload packet comprises 816 words. Between FAW and overhead, some stuffing is provided. In the shown embodiment, the stuffing comprises 132 words.

As it is clear from Figure 4, both the overhead and payload sections comprise a plurality of words and each word has redundant data providing forward error correction features. In this way, the link between Port and Matrix becomes protected in order to enable the use of a big number of High Speed links with very dense boards layout. The FEC algorithm and frame structure could be designed in order to provide an adequate coding gain and minimize the complexity of FEC encoder and decoder. The 13^rd payload packet is empty (i.e. contains stuffing data) when the frame is carrying SDH/SONET payload: in this case the capacity of each time slot is still C=8000x25x16 bit/s = 3.2 Mb/s. As a consequence, the mapping of AU4 and AU3 in this case is identical to the one defined for the 2,48832 Gbit/sec frame.

The frame according to Figure 5 is a 2,7648 Gbit/sec frame (8 KHz periodicity) transporting ODU tributaries (OTN payload).

The backpanel frame of Figure 5 comprises a first portion with a frame alignment word (FAW), a stuffing portion, an overhead and a number of payload packets. In the embodiment of Figure 5, each word comprises 16 bits, namely two bytes. The frame alignment word comprises 48 words, the overhead comprises 204 words and each payload packet comprises 816 words. Between FAW and overhead, some stuffing is provided. In the shown embodiment, the stuffing comprises 132 words.

As it is clear from Figure 5, both the overhead and payload sections comprise a plurality of words and each word has redundant data providing forward error correction features. In this way, the link between Port and Matrix becomes protected in order to enable the use of a big number of High Speed links with very dense boards layout. The FEC algorithm and frame structure could be designed in order to provide an adequate coding gain and minimize the complexity of FEC encoder and decoder.

In this case all the payload packets can be filled with payload: the capacity of each time slot is increased up to C=8000x26x16 bit/s = 3.328 Mb/s. This allows for a mapping of one ODU1 in 16x48=768 time slots, a mapping of one ODU2 in 16x192=3072 time slots, and a mapping of an ODU3 in 16x768=12288 time slots. As the ODUx tributary cannot be synchronized to the 8KHz backpanel frame, a convenient plesiochronous mapping method must be defined for this case, e.g. using a proprietary positive stuffing mapping.

An alternative to Figure 5 backpanel frame could be to define a frame with a time slot capacity of C=8000x25x16 bit/s = 3.2 Mb/s (the same as for the frame in Figure 3), but inserting in the frame a higher number of timeslots, for instance 800. In this case the mapping of one ODU1 can be achieved using 16x50=800 time slots, the mapping of one ODU2 using 16x200=3200 time slots, and the mapping of an ODU3 using 16x800=12800 time slots. As the ODUx tributary cannot be synchronized to the 8KHz backpanel frame, a convenient plesiochronous mapping method must be defined for this case, e.g. using a proprietary positive stuffing mapping.The port according to the present invention, according to the tributary capacity and the number of parallel elementary matrices, manages the mapping of one tributary in the time slots inside each link. The elementary matrix itself has not to know the payload content of the frames received as input flows and it is thus agnostic.

In Figure 6 the operation of a port (PORT) according to one embodiment of the present invention is shown. In particular, the slicing step is shown for the case of a 16xSTM16/OC48 receiving port. The port receives sixteen input flows (L0, L1, L2, ..., L15) with STM16/OC48 frame format. For each AU-3 tributary, eight bytes are collected and stored in a memory. The number of AU-3 tributaries inside an STM 16 is 48 (0 ...47); t=0 stands for the first arrived byte of a tributary and, analogously, t+ 1 stands for the second arrived byte, and so on up to the last arrived byte (t+7). It is supposed that the port of Figure 6 is connected to four switching matrices (A, B, C, D, not shown), through four backpanel connections for each matrix, numbered 0 to 3.

As it is shown in Figure 6, the eight bytes of each tributary received at each input link are sliced so that four equal structures are fed to the four switching matrices. For instance, the tributaries of the first input link L0 are sliced and arranged in four different frames. The first frame (A0, sent to matrix A) comprises L0[0°,0¹)(1⁰,1¹)...(47⁰,47¹)], wherein: <ul id="ul0002" list-style="none" compact="compact"><li>0⁰ : first received byte of AU3 number 0;</li><li>0¹ : second received byte of AU3number 0;</li><li>1⁰ : first received byte of AU3 number 1;</li><li>1¹ : second received byte of AU3 number 1;</li><li>47⁰ first received byte of AU3 number 47;</li><li>47¹: second received byte of AU3 number 47; and, more in general,</li><li>jⁱ : (i+1)-th received byte of j-th AU3</li></ul>

The second frame (B0, sent to matrix B) comprises L0[0²,0³)(1²,1³) ... (47²,47³)], wherein: <ul id="ul0003" list-style="none" compact="compact"><li>0² : third received byte of AU3 number 0;</li><li>0³ : fourth received byte of AU3 number 0; and so on.</li></ul>

The third frame (C0, sent to matrix C) comprises L0[04,0⁵)(14,15) ... (47⁴,47⁵)], wherein: <ul id="ul0004" list-style="none" compact="compact"><li>0⁴ : fifth received byte of AU3 number 0;</li><li>0⁵ : sixth received byte of AU3 number 0; and so on.</li></ul>

And, finally, the fourth frame (D0, sent to matrix D) comprises L0[0⁶,0⁷)(1⁶,1⁷) ... (47⁶,47⁷)], wherein: <ul id="ul0005" list-style="none" compact="compact"><li>0⁶ : seventh received byte of AU3 number 0;</li><li>0⁷ : eighth received byte of AU3 number 0; and so on.</li></ul>

The same criteria is adopted for the other fifteen input links L1 to L15).

It is possible to avoid storing eight bytes for each tributary before starting the transmission of payload towards the four matrices: as soon as two bytes are stored, they are transmitted towards one of the four matrices, in round robin fashion; this results in having the four links towards the four matrices which are slightly delayed from matrix number 1 (the first served) to matrix number four (the last served). The matrices operate with this relative delay, and the delay is absorbed in the de-slice process (the one which reconstructs the original AU3 after the cross-connection).

It will be realized that the present invention fundamentally consists in organizing received data in a proper frame format (comprising payload and overhead) coming from the line framer to the Matrix switches. At least the following objectives are reached by the present invention:

It is obtained an agnostic architecture having the capability to cross-connect both High Order SONET/ SDH tributaries and ODUx tributaries (and possibly any payload that can be accommodated in a number of time slots).

It is allowed a scalable "word slice" approach maximizing Matrix capacity and minimizing complexity and power dissipation for Matrix switch.

Finally, the link between Port and Matrix becomes protected by a FEC in order to enable the use of a large number of High Speed links with very dense boards layout. The FEC algorithm and frame structure are studied in order to provide an adequate coding gain and minimize the complexity of FEC encoder and decoder.

The solution according to the present invention is extremely flexible. In fact, the matrix is payload agnostic, and it simply switches time slots. Furthermore, it is very easy adding specific ports to the system in order to obtain an equipment able to cross-connect at the same time every type of TDM traffic (e.g. SDH, SONET, OTH...).

Moreover the system is easily scalable thanks to the word-slice approach.

The backpanel links provide built-in communication channels between ports and matrix (useful for system maintenance and traffic overhead handling).

Profitably, the port and the matrix are ASIC implemented.

Whilst only input ports have been described, it is clear that output ports will operate fundamentally in a mirrored manner.