Method of fabricating self-aligned source and drain contacts in a Double gate FET with controlled manufacturing of a thin Si or non-Si channel

The invention relates to a method of forming a transistor structure on a substrate (SOI), the substrate comprising a supporting Si layer (1), a buried insulating layer (2), and a top Si layer (3) comprising a high dopant level, the transistor structure comprising a gate region (G1), and a source and drain region (5). The method further comprises the formation of the gate region (G1) on the top Si layer (3), the gate region (G1) being separated from the top Si layer (3) by a dielectric layer (GD), the formation of an open area (O1) on the top Si layer (3) demarcated by a demarcating oxide and/or resist layer region (4), the formation of high level impurity or heavily-damaged regions (5) by ion implantation, exposing the open area (O1) to an ion beam (IB), with the demarcating layer region (4) and the gate region (G1) acting as implantation mask. The ion beam (IB) comprises a combination of beam energy and dose, which allows the formation, in the top Si layer (3), of high impurity level regions (L1) below the source and drain regions (5) in the buried insulating layer (2) and of a high impurity level or heavily-damaged regions (L0) below the gate region (G1) in the top Si layer (3).