Pwm led regulator with sample and hold

0001The invention relates to regulated LED current sources. More particularly the invention relates to techniques for configuring an LED regulator for improved stability.

0002LED lighting systems generally employ regulated power sources for supplying power to the LEDs. In the art of LED drivers, it is known to use a pulse-width modulated (PWM) drive current as a power source to the LED. Generally, a regulator circuit includes several sub-circuits with active and passive elements that operate in concert to provide power regulation.

0003A simple circuit diagram for a typical regulator for driving LED strings is shown in <figref idref="f0001">FIG. 1</figref>. A Buck-Boost converter is formed of <b>Q1</b>, <b>L, D1</b> and <b>C1.</b> A serial LED string is denoted as <b>D5.</b> The <b>OP-AMP1</b> along with the surrounding resistors, <b>R5, R6, R7, R8</b> forms a differential amplifier for the sensed current signal form <b>R1.</b> An analog PID controller is formed by <b>OP-AMP2</b> along with the surrounding components <b>R9, R10, R11, R12, C5, C6,</b> and <b>C7.</b> A PWM signal is introduced to the regulator circuit through the modulator <b>COMP1.</b> In steady-state DC operation, the LED string <b>D5</b> current is regulated by the regulator circuit.

0004<figref idref="f0002">FIG. 2</figref> illustrates the regulator circuit configured to provide the LED string <b>D5</b> with light output adjustment or dimming functionality. It is known to be beneficial to use a low-frequency PWM current for the LED string <b>D5</b> by invoking a series switch <b>Q2</b> as is depicted in <figref idref="f0002">FIG. 2</figref>. In order to reduce the current peak pulse in the LED string <b>D5</b> at each turn on event, a simple sample-and-hold <b>210</b> sub-circuit consisting <b>of R2, R4, C2</b> and <b>D2</b> is provided. As shown in <figref idref="f0002">FIG. 2</figref>, the sample-and-hold sub-circuit has an output voltage <b>V3</b> and an input voltage <b>V6.</b> It can be shown that when the diode <b>D2</b> conducts, the transfer function of the sample-and-hold <b>210</b> sub-circuit is: <maths id="math0001" num="(1)"><math display="block"><mfrac><mrow><mi mathvariant="normal">V</mi><mo>⁢</mo><mn mathvariant="normal">3</mn></mrow><mrow><mi mathvariant="normal">V</mi><mo>⁢</mo><mn mathvariant="normal">6</mn></mrow></mfrac><mo>=</mo><mi>K</mi><mfenced><mi>s</mi></mfenced><mo>=</mo><msub><mi>K</mi><mn>0</mn></msub><mo>⁢</mo><mfrac><mn mathvariant="italic">1</mn><mrow><mn mathvariant="italic">1</mn><mo>+</mo><mfrac><mi>s</mi><mi mathvariant="normal">ω</mi></mfrac></mrow></mfrac><mo>,</mo></math><img file="EP1579736B1_D0001.tif" /></maths> where <maths id="math0002" num="(2)"><math display="block"><msub><mi>K</mi><mn>0</mn></msub><mo>=</mo><mfrac><mrow><mi mathvariant="bold">R</mi><mo>⁢</mo><mn mathvariant="bold">2</mn></mrow><mrow><mi mathvariant="bold">R</mi><mo>⁢</mo><mn mathvariant="bold">2</mn><mo mathvariant="bold">+</mo><mi mathvariant="bold">R</mi><mo>⁢</mo><mn mathvariant="bold">4</mn></mrow></mfrac><mo>,</mo><mi>and</mi></math><img file="EP1579736B1_D0002.tif" /></maths><maths id="math0003" num="(3)"><math display="block"><mi mathvariant="normal">ω</mi><mo>=</mo><mfrac><mrow><mi mathvariant="bold">R</mi><mo>⁢</mo><mn mathvariant="bold">2</mn><mo>+</mo><mi mathvariant="bold">R</mi><mo>⁢</mo><mn mathvariant="bold">4</mn></mrow><mrow><mi mathvariant="bold">R</mi><mo>⁢</mo><mn mathvariant="bold">2</mn><mo>*</mo><mi mathvariant="bold">R</mi><mo>⁢</mo><mn mathvariant="bold">4</mn><mo>*</mo><mi mathvariant="bold">C</mi><mo>⁢</mo><mn>2</mn></mrow></mfrac><mn>.</mn></math><img file="EP1579736B1_D0003.tif" /></maths> Inspection of equation (1) reveals that the sample-and-hold introduces a pole, with an associated 90 degree phase delay, into the current regulation loop. The LED regulator phase margin is therefore reduced and the regulator circuit tends to oscillate.

0005<patcit id="pcit0001" dnum="US6472957B1"><text>US-6472957-B1</text></patcit> provides a filter circuit comprising n bandpass filters, each bandpass filter coupled between an input terminal of the filter circuit and an output terminal. Each bandpass filter comprises a resonant circuit comprised of an inductor and capacitors. If used in a regulator, the transfer function of the filter circuit would introduce a pole, with an associated 90 degree phase delay, into the current regulation loop.

0006It would therefore be desirable to provide an improved LED regulator configuration that addressed these and other limitations.

0007The present invention is directed to a system and method for improving stability in an LED regulator as put down in the enclosed claims.

0008In accordance with another aspect of the invention, a regulator circuit having a sample-and-hold circuit with improved stability is provided.

0009The foregoing and other features and advantages of the invention are apparent from the following detailed description of exemplary embodiments, read in conjunction with the accompanying drawings. The detailed description and drawings are merely illustrative of the invention rather than limiting, the scope of the invention being defined by the appended claims and equivalents thereof. <ul id="ul0001" list-style="none" compact="compact"><li><figref idref="f0001">FIG. 1</figref> illustrates a prior art LED regulating system.</li><li><figref idref="f0002">FIG. 2</figref> illustrates a prior art low-frequency PWM based LED regulating system.</li><li><figref idref="f0003">FIG. 3</figref> is a block diagram of an pseudo-all-pass sample-and-hold circuit in accordance with the present invention.</li><li><figref idref="f0003">FIG. 4</figref> is a block diagram illustrating an embodiment of the pseudo-all-pass sample-and hold circuit of <figref idref="f0003">FIG. 3</figref> in accordance with the present invention.</li><li><figref idref="f0004">FIG. 5</figref> is a flow diagram of a method for configuring a regulator circuit having a sample-and-hold circuit in accordance with the present invention.</li></ul>

0010In the following description the term "coupled" means either a direct connection between the things that are connected, or a connection through one or more active or passive devices that may or may not be shown, as clarity dictates.

0011<figref idref="f0003">FIG. 3</figref> is a block diagram of a pseudo-all-pass sample-and-hold circuit in accordance with the present invention. <figref idref="f0003">FIG. 3</figref> shows a pseudo-all-pass sample-and-hold circuit <b>300.</b> The pseudo-all-pass sample-and-hold circuit <b>300</b> is shown having an input node <b>Vin</b> and an output node <b>Vout</b> both referenced to ground.

0012The pseudo-all-pass sample-and-hold circuit <b>300</b> is any circuit that provides a sample-and-hold function and has the transfer function: <ul id="ul0002" list-style="none" compact="compact"><li><b>Vout(s) /Vin(s)=</b> K(s), K(s) is an all pass function when <b>Vin</b> > <b>Vout,</b> and (4)</li><li><b>Vout(t)</b> is a nearly constant signal when <b>Vin</b> < <b>Vout.</b> (5)</li></ul>

0013Therefore, the pseudo-all-pass sample-and-hold configuration provides a sample-and-hold function in a regulator circuit without introducing a pole into the transfer function of the regulator. A regulator is then able to operate in a more stable manner.

0014In one embodiment, the pseudo-all-pass sample-and-hold circuit <b>300</b> is an active sample-and-hold device configured for all pass operation such as an integrated circuit, for example. In another embodiment, the pseudo-all-pass sample-and-hold circuit <b>300</b> is a passive circuit containing passive devices such as resistors, capacitors, diodes and the like. A passive embodiment of a pseudo-all-pass sample-and-hold circuit <b>300</b> is discussed in detail with reference to <figref idref="f0003">FIG 4</figref>.

0015<figref idref="f0003">FIG. 4</figref> is a block diagram illustrating an embodiment of the pseudo-all-pass sample-and hold circuit of <figref idref="f0003">FIG. 3. FIG. 3</figref>, shows an all sample-and-hold circuit <b>300</b> comprising a sample and hold circuit <b>210</b> as in <figref idref="f0002">FIG. 2</figref>, a first pass diode <b>D6</b> and a second pass diode <b>D7.</b> The first pass diode <b>D6</b> is shown coupling the sample-and-hold circuit <b>210</b> to an output node <b>V3</b> with a forward bias. The second pass diode <b>D7</b> is shown coupling an input node <b>V6</b> with the output node with a forward bias.

0016In operation, the pass diode <b>D7</b> passes a current whenever the voltage potential at <b>V6</b> is greater than the potential voltage at <b>V3.</b> The potential voltage applied to <b>V6</b> is either time-varying, such as a periodic pulse or a DC value. The bias of diodes <b>D6</b> and <b>D7</b> prevents current reversal if the potential voltage of <b>V3</b> is greater than <b>V6,</b> and therefore configures the sample-and-hold circuit.

0017In the following process description certain steps may be combined, performed simultaneously, or in a different order without departing from the invention.

0018<figref idref="f0004">FIG. 5</figref> is a flow diagram of a method for configuring a regulator circuit having a sample-and-hold circuit in accordance with the present invention. Process <b>500</b> begins in step <b>510.</b> Generally, the sample-and-hold circuit operates to reduce the current peak pulse in an LED string under PWM drive at each turn-on moment.

0019In step <b>510</b> an input voltage is coupled to an input node <b>V6</b> of a pseudo-all-pass sample-and hold <b>300.</b> The input voltage is generally the output of a regulator sub-circuit, such as, for example, a differential amplifier that monitors the current through an LED string <b>D5.</b> The input voltage may be a time-varying signal such as a periodic pulse, or a static DC value. The voltage may be coupled to the input node at any time, and may be selectably operated for specific functionality such as a PWM operational mode.

0020In step <b>520,</b> the pseudo-all-pass sample-and-hold circuit <b>300</b> is activated in response to the voltage coupled in step <b>510.</b> The pseudo-all-pass sample-and-hold circuit <b>300</b> contains components that are activated when a voltage is coupled to the circuit such as a capacitor. In one embodiment, the capacitor charges in response to the voltage signal. Activation of the sample-and-hold <b>300</b> occurs immediately with the coupling of the input voltage in step <b>510.</b>

0021In step <b>530,</b> output voltage at an output node is sensed. Generally, a first pass diode <b>D6</b> and second pass diode <b>D7</b> are configured around a sample-and-hold to allow sensing of the output voltage. The diodes will reverse bias if the output voltage is greater than the reference input voltage.

0022In step <b>540</b> a determination is made whether the input voltage at the input node is greater than the output voltage at the output node. Generally, the first pass diode <b>D6</b> and the second pass diode <b>D7</b> provide a determination of whether the input voltage is greater than the output voltage, since the forward biased diodes will conduct under those conditions. If the input voltage is less than the output voltage, then the diode <b>D7</b> will not conduct and the output voltage of the sample-and-hold circuit will be an almost constant signal.

0023In step <b>550,</b> a sample-and-hold function is provided based on the determination of step <b>540.</b> The sample-and-hold circuit <b>300</b> has a transfer characteristic based on the relative voltages determined in step <b>540.</b> The sample-and-hold function is provided at all times the sample-and-hold circuit is operational.

0024While the preferred embodiments of the invention have been shown and described, numerous variations and alternative embodiments will occur to those skilled in the art, wherein the invention is limited only in terms of the appended claims.