EP1577946A3

Method to make markers for doublegate SOI processing

Abstract

Method to make at least one marker (MX) for double gate SOI processing on a SOI wafer, the at least one marker having a diffracting structure in a first direction and the diffracting structure being arranged for generating an asymmetrical diffraction pattern during use in an alignment and overlay detection system for detection in the first direction; the SOI wafer comprising a substrate, an oxidized layer on the substrate, and a semiconductor layer on top of the oxidized layer; the double gate SOI processing being performed on at least one die (D); the at least one die (D) being located on the semiconductor layer and comprising at least an inner area arranged as a circuit area (C) and an outer area arranged as scribe line area (SL); the at least one marker (MX) being defined in the scribe line area (SL); and the double gate SOI processing comprising a processing step for: separating the semiconductor layer from the oxidized layer,attaching the separated semiconductor layer as a turned-over semiconductor layer on a surface of a new substrate, with the original top surface of the semiconductor layer directed towards on the surface of the new substrate, wherein the method provides a mirrored marker (MX'), the mirrored marker (MX') being the mirror image of the marker (MX), by using a mirror operation around a second direction perpendicular to the first direction.

EP1577946A3, drawing sheet 1
Sheet 1 of 1

Term

Term ended

Projected expiry passed 23 February 2025, 1.6 years ago.

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