EP1575092A2

Reduced area images devices incorporated within surgical instruments

Abstract

A reduced area imaging devices for use in an investigating imaging device to view difficult to access locations comprising an image sensor provided on a planar structure, an array of CMOS pixels lying in a first plane, said array of CMOS pixels receives images thereon; said planar structure defines a profile area which determines the critical dimensions of the imaging device for the integration into the investigating imaging device, first circuitry means electrically coupled to said array of CMOS pixels, said circuitry means include means for timing and control of said array of CMOS pixels, said timing and control means producing an analog pre-video signal, second circuitry means including means for receiving said analog pre-video signal from said timing and control means and converting said pre-video signal to a post-video output signal for reception by a video device, and a power supply electrically coupled to said array of CMOS pixels, and said circuitry means, wherein said CMOS pixel array and said first circuitry means are positioned in a first plane, and said second circuitry means is positioned in a remote control box.

EP1575092A2, drawing sheet 1
Sheet 1 of 13

Term

Term ended

Projected expiry passed 17 September 2018, 8 years ago.

  1. Priority
  2. Filed
  3. Published
  4. Projected expiry
  5. Today

15 claims: 9 independent, 6 dependent

  1. 1
    A reduced area imaging devices for use in an investigating imaging device to view difficult to access locations comprising:an image sensor provided on a planar structure;an array of CMOS pixels lying in a first plane, said array of CMOS pixels receives images thereon;said planar structure defines a profile area which determines the critical dimensions of the imaging device for the integration into the investigating imaging device;first circuitry means electrically coupled to said array of CMOS pixels, said circuitry means include means for timing and control of said array of CMOS pixels, said timing and control means producing an analog pre-video signal;second circuitry means including means for receiving said analog pre-video signal from said timing and control means and converting said pre-video signal to a post-video output signal for reception by a video device;and a power supply electrically coupled to said array of CMOS pixels, and said circuitry means, wherein said CMOS pixel array and said first circuitry means are positioned in a first plane;and said second circuitry means is positioned in a remote control box.
  2. 2
    A reduced area imaging devices for use in an investigating imaging device to view difficult to access locations comprising:an image sensor provided on a planar structure;an array of CMOS pixels lying in a first plane, said array of CMOS pixels receives images thereon;said planar structure defines a profile area which determines the critical dimensions of the imaging device for the integration into the investigating imaging device;first circuitry means electrically coupled to said array of CMOS pixels, said circuitry means include means for timing and control of said array of CMOS pixels, said timing and control means producing an analog pre-video signal;second circuitry means including means for receiving said analog pre-video signal from said timing and control means and converting said pre-video signal to a post-video output signal for reception by a video device;and a power supply electrically coupled to said array of CMOS pixels, and said circuitry means, wherein said CMOS pixel array is positioned in a first plane;and said first circuitry means and said second circuitry means are positioned in a second plane in a stacked arrangement to the first plane.
  3. 3
    A reduced area imaging devices for use in an investigating imaging device to view difficult to access locations comprising:an image sensor provided on a planar structure;an array of CMOS pixels lying in a first plane, said array of CMOS pixels receives images thereon;said planar structure defines a profile area which determines the critical dimensions of the imaging device for the integration into the investigating imaging device;first circuitry means electrically coupled to said array of CMOS pixels, said circuitry means include means for timing and control of said array of CMOS pixels, said timing and control means producing an analog pre-video signal;second circuitry means including means for receiving said analog pre-video signal from said timing and control means and converting said pre-video signal to a post-video output signal for reception by a video device;and a power supply electrically coupled to said array of CMOS pixels, and said circuitry means, wherein said CMOS pixel array is positioned in a first plane;said first circuitry means is positioned in a second plane in a stacked arrangement to the first plane;and said second circuitry means is positioned in a remote control box.
  4. 4
    A reduced area imaging devices for use in an investigating imaging device to view difficult to access locations comprising:an image sensor provided on a planar structure;an array of CMOS pixels lying in a first plane, said array of CMOS pixels receives images thereon;said planar structure defines a profile area which determines the critical dimensions of the imaging device for the integration into the investigating imaging device;first circuitry means electrically coupled to said array of CMOS pixels, said circuitry means include means for timing and control of said array of CMOS pixels, said timing and control means producing an analog pre-video signal;second circuitry means including means for receiving said analog pre-video signal from said timing and control means and converting said pre-video signal to a post-video output signal for reception by a video device;and a power supply electrically coupled to said array of CMOS pixels, and said circuitry means, wherein said CMOS pixel array is positioned in a first plane;said first circuitry means is positioned in a second plane in a stacked arrangement to the first plane;and said second circuitry means is positioned in a third plane in a stacked arrangement to the second plane.
  5. 5
    A reduced area imaging device as claimed in any one of the claims 1 - 4, wherein said array of CMOS pixels includes a plurality of passive CMOS pixels, and wherein individual passive CMOS pixels of said plurality of passive CMOS pixels each include a photo diode for producing photo electrically generated signals, and an access transistor communicating with said photo diode to control the release of said photo electrically generated signals.
  6. 6
    A reduced area imaging device as claimed in any one of the claims 1 - 5, wherein individual pixels within said array of CMOS pixels each include an amplifier.
  7. 7
    A reduced area imaging device as claimed in any of the claims 1 - 6, wherein said imaging device further comprises an electrical conductor interconnecting the first circuitry means and the CMOS pixel array thereby not extending said profile area defined by said CMOS pixel array.
  8. 8
    A reduced area imaging device as claimed in any of the claims 1 - 7, further including a supplementary circuitry means communicating with said array of CMOS pixels and said first circuitry means for enhancing said analog pre-video signal.
  9. 9
    A reduced area imaging device as claimed in any of the claims 1 - 8, wherein said circuitry means is positioned in a stacked arrangement to said CMOS pixel array so as not to extend substantially beyond said profile area of said CMOS pixel array in direction perpendicular to a stack axis.
  10. 10
    A reduced area imaging device as claimed in any of the claims 8 and 9, wherein said supplementary circuitry means is positioned in a stacked arrangement to the first plane.
  11. 11
    A reduced area imaging device as claimed in any of the claims 8 and 9, wherein said supplementary circuitry means is positioned in a remote control box.
  12. 12
    An endoscope with integral imaging capability comprising:a tubular portion including a distal end, a proximal end and a central passageway extending therethrough;and a reduced area imaging devices according to any one of the previous claims wherein a CMOS pixel array and a first circuitry means as defined in claims 1 - 4 are mounted in said tubular portion.