Integrating n-type and p-type metal gate transistors

FIELD

0001The invention relates to the manufacture of complementary metal-oxide-semiconductor (CMOS) devices. More particularly, the invention relales to integrating n-type and p-type metal gate transistors within a single CMOS device.

BACKGROUND

0002Prior art CMOS devices manufactured with prior art semiconductor processes typically have polysilicon gate structures. Polysilicon, however, can be susceptible to depletion effects, which can add to the overall gate dielectric thickness in the CMOS device. Furthermore, as the effective physical gate dielectric thickness decreases, the polysilicon depletion contributes proportionally to the total dielectric thickness. It is, therefore, desirable to eliminate polysilicon depletion in order to scale gate oxide thickness.

0003Metal gates, on the other hand, are not as susceptible to depletion as polysilicon and are in many ways preferable to polysilicon for forming gate structures. Typical prior art semiconductor processes, however, do not incorporate n-type and p-type metal gates within the same device or integrated circuit. This is due, in part, to the complexity and cost of developing a semiconductor process that can reliably deposit metal gate structures of differing types into the same semiconductor device or integrated circuit.

0004In document <patcit id="pcit0001" dnum="GB2358737A"><text>GB 2 358 737</text></patcit> two methods for manufacturing complimentary MOSFET devices are disclosed. The first (depicted in <figref idref="f0001 f0002">figs 1-3</figref>) comprises depositing dummy gate electrodes on a substrate, using these as ion implantation masks and then forming an insulation film over the substrate and dummy gate electrodes. The dummy electrodes are removed separately and the recesses left in the insulation film are individually filled with different gate electrode materials. The second method (depicted in <figref idref="f0003">figs 5 and 6</figref>) comprises separately forms gate electrodes of different material in recesses formde in an insulation layer and then uses these actual electrodes as implantation masks. Electrode materials, insulation layer materials and composite electrodes are all disclosed. The gate electrode materials preferably have a work function close to the work function of either n or p type polysilicon.

0005Document <patcit id="pcit0002" dnum="US2002058374A1"><text>US 2002/058374 A1</text></patcit> relates to a method of forming dual-metal gates in a semiconductor device, including the steps of providing a semiconductor substrate having a PMOS area and an NMOS area wherein dummy gates are formed in the PMOS and NMOS areas respectively, forming an insulating interlayer on the semiconductor substrate so as to cover the dummy gates, polishing the insulating interlayer until the dummy gates are exposed, forming a first groove defining a first metal gate area by selectively removing one of the dummy gates formed in the PMOS and NMOS areas, forming a first gate insulating layer and a first metal layer on an entire area of the semiconductor substrate including the first groove successively, forming a first metal gate in the first groove by etching the first metal layer and first gate insulating layer until the insulating interlayer is exposed, forming a second groove defining a second metal gate area by removing the remaining dummy gate, forming a second gate insulating layer and a second metal layer on the entire area of the semiconductor substrate including the second groove, and forming a second metal gate in the second groove by etching the second metal layer and second gate insulating layer until the insulating interlayer is exposed.

0006Documents <patcit id="pcit0003" dnum="US6255698B1"><text>US-B1-6 255 698</text></patcit>, <patcit id="pcit0004" dnum="EP0899789A"><text>EP-A-0 899 789</text></patcit> and <patcit id="pcit0005" dnum="US6365450B"><text>US-B-6 365 450</text></patcit> also disclose the formation of n-type and n-type transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

0007Embodiments of the invention are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

0008<figref idref="f0001">Figure 1</figref> illustrates the state of transistors after depositing ILDO according to one embodiment.

0009<figref idref="f0001">Figure 2</figref> illustrates the state of transistors after ILDO polish-back to expose polysilicon gate structures according to one embodiment.

0010<figref idref="f0002">Figure 3</figref> illustrates the state of transistors after selective n-type poly etch according to one embodiment.

0011<figref idref="f0002">Figure 4</figref> illustrates the state of transistors after depositing n-type metal according to one embodiment.

0012<figref idref="f0003">Figure 5</figref> illustrates the state of transistors after polishing the n-type metal according to one embodiment.

0013<figref idref="f0003">Figure 6</figref> illustrates the state of transistors after selectively etching p-type polysilicon according to one embodiment.

0014<figref idref="f0004">Figure 7</figref> illustrates the state of transistors after depositing p-type metal according to one embodiment.

0015<figref idref="f0004">Figure 8</figref> illustrates the state of transistors after polishing the p-type metal according to one embodiment.

0016<figref idref="f0005">Figure 9</figref> illustrates the completed transistors according to one embodiment.

0017<figref idref="f0005">Figure 10</figref> illustrates the state of transistors after an optional implant patterning according to one non-claimed example.

0018<figref idref="f0006">Figure 11</figref> illustrates the state of transistors of <figref idref="f0005">Fig. 10</figref> after n-type implant and ash.

0019<figref idref="f0006">Figure 12</figref> illustrates the state of transistors of <figref idref="f0006">Fig. 11</figref> after a second selective n-type polysilicon etch.

DETAILED DESCRIPTION

0020Embodiments of the invention described herein relate to semiconductor manufacturing. More particularly, embodiments of the invention described relate to integrating n-type and p-type metal gate transistors within the same complementary metal-oxide-semiconductor (CMOS) device or integrated circuit.

0021In order to manufacture CMOS devices and integrated circuits that can avoid the effects of gate depletion, embodiments of the invention incorporate n-type and p-type metal gates into the same CMOS device or integrated circuits.

0022<figref idref="f0001">Figure 1</figref> illustrates a cross-section of a CMOS device containing a p-type transistor and an n-type transistor after depositing ILDO ("Inter-layer dielectric") according to one embodiment. In <figref idref="f0001">Figure 1</figref>, poly-silicon gate transistors 105, 110 are fabricated using standard CMOS processing techniques in order to prevent silicide formation on the poly-silicon gate electrode. The nitride hard masks 115 are to protect the gate structures during silicidation and ILDO 120 is deposited on the structure.

0023The ILDO is polished back to expose the doped polysilicon gates in <figref idref="f0001">Figure 2</figref>. The ILDO polishing also removes residual silicide around the nitride masking layer. After the polysilicon gates 205, 210 are exposed, an ammonium hydroxide etch is used to selectively etch away 305 the n-type polysilicon. The ammonium hydroxide etch is low temperature (e.g., &lt;40 deg. Celsius), uses sonication, and has a concentration of approximately 2 - 29%. The result of the polysilicon etch is illustrated in <figref idref="f0002">Figure 3</figref>.

0024Removal of the n-type polysilicon above the gate dielectric creates a damascene-like "trench" which is filled with an n-type metal 405, such as Hf, Zr, Ti, Ta, or Al, as illustrated in <figref idref="f0002">Figure 4</figref>. Alternatively, the trench can be filled with an alloy containing an n-type component using PVD ("Physical vapor deposition"), CVD ("Chemical vapor deposition"), or ALD ("Atomic Layer deposition"). CVD and ALD may use an organometallic or halide precursor, and a reducing atmosphere. Furthermore, the thickness of the n-type metal or alloy can be such that the trench is only partially filled. For example, the thickness of the n-type metal or alloy can vary from approximately 50 angstroms to approximately 1000 angstroms in various embodiments. If the trenches are not completely filled, they may be filled with an easily polished metal, such as W (tungsten") or Al ("Aluminum").

0025The n-type metal gate can be doped by implanting n-type material after the metal gate has been deposited in the trench.

0026The n-type metal is polished back to create the n-type metal gates 505 and to expose the p-type polysilicon gate 510 as illustrated in <figref idref="f0003">Figure 5</figref>.

0027<figref idref="f0003">Figure 6</figref> illustrates the transistors after a selective dry etch is performed to remove the p-type polysilicon without removing the n-type metal gate. The selective dry etch can be performed using a parallel plate or ECR ("Electron cyclotron resonance") etcher and SF6 ("Sulfur hexafluoride"), HBr ("Hydrogen Bromide"), Hl ("Hydrogen Iodide"), Cl2 ("Chlorine"), Ar ("Argon"), and/or He ("Helium"). Alternatively, a wet etch, such as approximately 20 - 30 % TMAH ("Tetramethylammonium Hydroxide") at approximately 60 - 90 degrees Celsius with or without sonication may also be used to remove the p-type polysilicon gate.

0028A p-type metal, such as Ru ("Ruthenium"), Pd (palladium"), Pt ("platinum"), Co ("Cobalt'), Ni ("Nickel"), TiAlN ("Titanium Aluminum Nitride"), or WCN ("Tungsten Carbon Nitride") can be used to fill the gate trench created by etching the p-type polysilicon gate 510. Alternatively, an alloy using p-type metal can be deposited in the trench using chemical vapor deposition or atomic layer deposition with an organometallic precursor and a reducing atmosphere. The p-type metal gate can be doped by implanting the metal gate with p-type material after the metal gate has been deposited in the gate trench. Furthermore, the thickness of the p-type metal or alloy can be such that the trench is only partially filled. <figref idref="f0004">Figure 7</figref> illustrates the transistors after the p-type metal or alloy has been deposited in the gate trench 710.

0029The p-type metal or alloy is polished back, as illustrated in <figref idref="f0004">Figure 8</figref>, to create the n-type and p-type gate structures 805, 810, and ILDO is again deposited to provide room for the contact layer.

0030Contacts 903 are etched and deposited, as illustrated in <figref idref="f0005">Figure 9</figref>, resulting in the final transistor structure.

0031In a non-claimed alternative, rather than using a dry etch to remove the p-type polysilicon as described above, the p-type polysilicon gate can be converted to n-type in order to allow a gentler wet etch to remove the polysilicon rather than a dry etch. For example, after the p-type polysilicon 1010 has been exposed, rather than using a selective dry etch to remove the polysilicon, an n-type implant 1015 is performed to change the doping of the polysilicon in order to allow an ammonium hydroxide etch to be performed, as illustrated in <figref idref="f0005">Figure 10</figref>.

0032The result of the implant and ash (if required) is illustrated in <figref idref="f0006">Figure 11</figref>. An ammonium hydroxide etch removes the remaining polysilicon gate structure 1210 resulting in the structure illustrated in <figref idref="f0006">Figure 12</figref>. A p-type metal or alloy may then be deposited in the trench left by removing the p-type polysilicon gate as described above.

0033While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the scope of the invention as defined in the appended claims.