Measuring an error rate in a communication link

Description of equivalent WO 2004051910 A2

MEASURING AN ERROR RATE IN A COMMUNICATION LINK

Cross Reference to Related Applications [0001] This application is related to, and claims the benefit of the filing date of, US Provisional Application No. 60/430,433 filed on December 3, 2002.

Technical Field

[0002] The present invention relates generally to the field of telecommunications, and, in particular to measuring an error rate of a communication link.

Background

[0003] Telecommunications networks provide a mechanism for communicating between subscriber equipment at diverse locations. A typical telecommunications network includes a variety of electronic modules, circuits and components. Further, these modules are typically coupled together over various communications links or lines through switches, routers, and other conventional equipment.

[0004] Some networks transmit digital data. With systems transmitting digital data, one aspect that affects the quality of the services provided is the bit error rate. This is a measurement of the number of errors per second and is typically represented as a percentage of bad bits to good. For example, a bit error rate of 1 bit in 1 billion would be represented as a bit error rate of 10^"9. A common specification for equipment manufacturers to meet is a maximum allowable bit error rate.

[0005] Before deploying equipment, manufacturers typically test their equipment in the lab to determine whether the equipment meets its design specifications. If not, modifications can be made until the criteria is met. These tests are accomplished with conventional test equipment which generates test signals, transmits the signals over the system in the lab, and then compares the output of the system with an expected signal. One aspect of this testing is that no errors are introduced by the connection between the test equipment and the system under test. This can be readily accomplished in a laboratory environment. However, once the equipment is deployed, the communication link between the system under test and the equipment under test may introduce errors into the process of measuring the error rate. For example, in the testing of a system with a host module and a remote module coupled over a fiber optic link, the test equipment cannot be connected over a perfect connection. Therefore, once deployed, the bit error rate for a system under test cannot readily be monitored to determine whether the performance level has changed since any connection back to the test equipment could also introduce errors.

[0006] Therefore, there is a need in the art for improvements in measuring and monitoring the bit error rate of a communication link.

Summary

[0007] Embodiments of the present invention measure bit error rate in deployed equipment by applying a self-synchronization technique to a deterministic stream of data to maintain a substantially continuous synchronization to the stream of data even in view of errors, dropped and inserted data. In one embodiment, the data stream is a sequence of numbers and in another embodiment the data stream is a pseudorandom bit stream. For example, in one embodiment a pseudorandom bit stream with approximately 1 million bits is used.

[0008] In one embodiment, an error rate detector is provided. The error rate detector includes a sequence generator that is adapted to generate a test sequence for comparison with a received sequence. The error rate detector also includes a self synchronization circuit that is responsive to the test sequence received from the sequence generator and the received sequence. The self synchronization circuit is adapted to move the sequence generator to a different point in the sequence based on a measure of the mismatches between the test sequence and the received sequence.

Brief Description of the Drawings

[0009] Figure 1 is a block diagram of a system with an error rate monitoring circuit according to the teachings of the present invention.

[0010] Figures 2A and 2B are graphs that illustrate one example of the operation of the monitoring circuit of Figure 1.

[0011] Figure 3 is a block diagram of another embodiment of a system with a bit error rate monitoring circuit according to the teachings of the present invention.

[0012] Figure 4 is a block diagram of another embodiment of a system with an error rate monitoring circuit according to the teachings of the present invention. [0013] Figure 5 is a flow chart that illustrates one method for monitoring an error rate with self-synchronization to a received sequence of data according to the teachings of the present invention.

Detailed Description

[0014] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific illustrative embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense.

[0015] Embodiments of the present invention measure an error rate in a communication link of a telecommunications network. Advantageously, the embodiments measure the error rate even in deployed systems by providing a sequence generator at a first end, e.g., a host end, and a sequence detector with self- synchronization at a second end, e.g., a remote end, of the communication link. The system generates a sequence at the first end and transmits the sequence to the remote end. At the remote end, the system monitors the received sequence and compares it with a locally created test sequence. The sequence detector uses a synchronization measure to determine when synchronization is lost between the received sequence and the test sequence. When synchronization is lost, the sequence detector is seeded with a value based on recently received information to resynchronize the test sequence at the sequence detector with the sequence received from the first end.

I. System with Error Rate Monitor

[0016] Figure 1 is a block diagram of a system, indicated generally at 100, with an error rate monitoring circuit according to the teachings of the present invention. System 100 includes sequence generator 102 and sequence detector 1 4. In one embodiment, sequence generator 102 is located at a first end of a communication link, e.g., a host terminal, and sequence detector 104 is located at a second end of the communication link, e.g., a remote terminal. Sequence generator 102 is coupled to sequence detector 104 over communication link 106. [0017] System 100 monitors the quality of communication link 106 using sequence generator 102 and sequence detector 104 by measuring, for example, an error rate for link 106. Sequence generator 102 generates a sequence and transmits the sequence over link 106. The sequence is a deterministic sequence in that the elements or members of the sequence are determinable based on prior elements or members. In one embodiment, the sequence comprises a pseudorandom sequence of numbers. In another embodiment, the sequence comprises a pseudorandom sequence of 2^N-1 bits. In other embodiments, any other deterministic sequence is used, e.g., consecutive numbers, etc.

[0018] In one embodiment, system 100 is a digital communication system that communicates data in digital frames over link 106. In one embodiment, the sequence is transmitted using a single bit of each frame. In other embodiments, a field or selected byte of the frame is reserved to transmit the sequence. In other embodiments, the sequence is transmitted using other portions of the frame.

[0019] Sequence detector 104 monitors a sequence received over communication link 106 and determines a measure of the error rate for the link based on comparison with a locally generated test sequence. Advantageously, sequence detector 104 self- synchronizes the test sequence with the received sequence even when members of the received sequence are lost or additional members are inserted into the received sequence. This means that system 100 is able to determine when synchronization is lost between the received and the locally generated sequences. When synchronization is lost, sequence detector 104 moves the test sequence to a different point in the sequence. In one embodiment, self-synchronization is accomplished by providing and monitoring a synchronization measure at synchronization detector 104. When this measure reaches a selected level, such as described below, synchronization detector 104 changes the expected sequence until the synchronization measure indicates synchronization has been achieved.

[0020] In one embodiment, sequence detector 104 generates a measure of the error rate for link 106. Further, sequence detector 104 also self-synchronizes to the sequence generated by sequence generator 102 such that when the sequence is corrupted in some way, sequence detector 104 detects the corruption and re- synchronizes to the received sequence. Sequence detector 104 includes sequence generator 108. Sequence generator 108 is coupled to comparator 110. Comparator 110 is also coupled to receive the sequence from sequence generator 102. Comparator 110 provides an output that indicates whether the elements of the received sequence from sequence generator 102 match the elements of the expected sequence produced by sequence generator 108. This information is provided to error rate calculator 112. In one embodiment, error rate calculator 112 determines a bit error rate for link 106. In other embodiments, error rate calculator 112 provides any other appropriate measure of the error rate.

[0021] Sequence generator 108 is self-synchronized to sequence generator 102 using a self-synchronization circuit. This self-synchronization circuit, in one embodiment, uses comparator 110, sequence memory 114 and synchronization monitor 116. Sequence memory 114 buffers a selected portion of the sequence received from sequence generator 102. For example, sequence memory 114 stores a last element of a received sequence such as a sequence of consecutive numbers. Alternatively, for a pseudorandom number sequence with 2^N-1 bits, sequence memory 114 stores the most recent N bits. The size of sequence memory 114 is determined by how much information is necessary to be kept in order to deterministically identify the next expected element in the received sequence based on one or more previously received elements. The stored value in sequence memory 114 is used to re-seed sequence generator 108 to generate a next expected value when synchronization monitor 116 determines that synchronization has been lost.

[0022] Synchronization monitor 116 uses a synchronization measure to determine when synchronization is lost. In one embodiment, synchronization monitor 116 uses a counter to provide the synchronization measure. This counter is incremented when an element of the received sequence matches an element of the sequence generated by sequence generator 108 as indicated by comparator 110. In one embodiment, the counter is incremented on each match until a selected level is reached. When a received element of the sequence from sequence generator 102 does not match the expected element generated by sequence generator 108, the counter is decremented. In one embodiment, the counter is decremented by two on a mismatch and is incremented by 1 on a match. This is advantageous when the sequence is a bit stream since in an unsynchronized bit stream of ones and zeros a mismatch is as likely as a match. Thus, by decrementing the counter twice as fast as incrementing the counter, it is likely to march toward zero in the face of an unsynchronized bit stream. [0023] When the counter reaches a selected level, e.g., zero, synchronization monitor 116 determines that the test sequence is not synchronized with the received sequence. Synchronization monitor 116 thus provides a reload signal to sequence generator 108. This causes data from sequence memory 114 to be loaded into sequence generator 108 to produce a next expected element for comparator 110 based on one or more recently received elements from sequence generator 102.

[0024] Figures 2 A and 2B are graphs that illustrate one example of the operation of the monitoring circuit of Figure 1. In this example, the sequence is a sequence of consecutive numbers. In one embodiment, this sequence is implemented by counting from zero modulo 256. In this example, the members of the sequence are received in "sequence slots." In one embodiment, these slots are time slots. In other embodiments, the sequence slots are not tied to a specific time frame.

[0025] In this example, sequence detector 104 starts out with a counter value of zero indicating an out of synchronization state as shown in Figure 2A. At sequence slot 0, the value 77 was received. Thus, synchronization monitor 116 causes this value to be provided by sequence memory 114 to sequence generator 108. Sequence generator 108 determines that the next expected value is 78 for sequence slot 1. At sequence slot 1, the element 78 is received and the counter is incremented by 1 as shown in Figure 2 A. At sequence slots 2 and 3, additional correct values are received. Thus, the counter is again incremented. In sequence slot 4, an error is detected. The value 52 is received when 81 was expected. Thus, the counter is reduced as shown in Figure 2A. Since the counter is still greater than zero, synchronization monitor 116 does not yet initiate a re-synchronization. In sequence slots 5 through 7, additional correct values are received. Thus, the counter continues to increment toward a maximum value, for this example, of five. It is noted that in other embodiments other maximum values are used. If the maximum value for the counter is set to a high value, the error monitor has a higher immunity to noise. However, it will also take longer for the error monitor to resynchronize when the transport system slips (drops or inserts a value into the sequence).

[0026] At sequence slot 12, a slip has occurred in the sequence received from sequence generator 102. This means that one number in the sequence has been dropped in the data received over communication link 106. Since sequence generator 108 generates its sequence independent of sequence generator 102, sequence generator 108 continues to produce elements of its sequence without the slip. Thus, the expected elements and the received elements do not match in sequence slots 12 through 16. This causes the counter to be decremented with each sequence slot, as shown in Figure 2A. When the counter reaches zero at sequence slot 16, synchronization monitor 116 causes sequence memory 114 to load sequence generator 108 with the current element, namely 94 in this example. Based on this value, sequence generator 108 moves to the point in the sequence such that the next expected value is 95 instead of 94. Thus, resynchronization is achieved and the counter increments over sequence slots 17 through 21.

II. Pseudorandom Bit Stream Embodiment

[0027] Figure 3 is a block diagram of another embodiment of a system, indicated at 300, with a bit error rate monitoring circuit according to the teachings of the present invention. System 300 includes sequence generator 302 and sequence detector 304. Sequence generator 302 is located at a first end of a communication link, e.g., a host terminal, and sequence detector 304 is located at a second end of the communication link, e.g., a remote terminal. Sequence generator 302 is coupled to sequence detector 304 over communication link 306.

[0028] System 300 monitors a bit error rate of communication link 306 using sequence generator 302 and sequence detector 304. Sequence generator 302 generates a sequence and transmits the sequence over link 306. The sequence is a deterministic, pseudorandom number sequence. In one embodiment, the sequence comprises a pseudorandom sequence of 2^N-1 bits. In the example illustrated in Figure 3, sequence generator 302 generates a 15 bit sequence taken at the output of register REG 4 (Q₃). In this embodiment, sequence generator 302 comprises four registers; namely REG 1 , REG 2, REG 3, and REG 4. The registers are coupled together in series with the outputs of REG 3 and REG 4 being provided as feedback to REG 1 through exclusive-OR gate 303. In this configuration, sequence generator 302 produces the values set out in Table 1, below. <img file="WO2004051910A2_D0001.tif" />

Table 1

[0029] It is noted that any of the outputs, Qo to Q₃ could be used as the pseudorandom number sequence. In Figure 3, Q₃ is used to generate the transmitted sequence. It is also noted that any appropriate function that produces a pseudorandom number sequence of the same or different size can be used in place of the function shown in Figure 3. This function is shown and described by way of example and not by way of limitation. In other embodiments, longer, deterministic, pseudorandom number sequences, e.g., sequences of 1 million bits or more, are used. Such deterministic sequences are generated using, for example, known or later developed algorithms.

[0030] In one embodiment, system 300 is a digital communication system that communicates data in digital frames over link 306. In one embodiment, the sequence is transmitted using a single bit of each frame. In other embodiments, a field or selected byte of the frame is reserved to transmit the sequence. In other embodiments, the sequence is transmitted using other portions of the frame. [0031] Sequence detector 304 monitors a sequence received over communication link 306 and determines a measure of the error rate for the link based on comparison with a locally generated test sequence. Advantageously, sequence detector 304 self- synchronizes the test sequence with the received sequence even when bits of the received sequence are lost or additional bits are inserted into the received sequence. This means that system 300 is able to determine when synchronization is lost between the received and the locally generated sequences. When synchronization is lost, sequence detector 304 moves the test sequence to a different point in the sequence. In one embodiment, self-synchronization is accomplished by providing and monitoring a synchronization measure at synchronization detector 304. When this measure reaches a selected level, such as described below, synchronization detector 304 changes the expected sequence until the synchronization measure indicates synchronization has been achieved.

[0032] In one embodiment, sequence detector 304 generates a measure of the error rate for link 306. Further, sequence detector 304 also self-synchronizes to the sequence generated by sequence generator 302 such that if the sequence is corrupted in some way, sequence detector 304 detects the corruption and re-synchronizes to the received sequence. Sequence detector 304 includes sequence generator 308. Sequence generator 308 includes the same functions as sequence generator 302 and thus produces the same deterministic output when provided with the same input.

[0033] Sequence generator 308 is coupled to comparator 310. Comparator 310 is also coupled to receive the sequence from sequence generator 302. Comparator 310 provides an output that indicates whether the bits of the received sequence from sequence generator 302 match the bits of the expected sequence produced by sequence generator 308. This information is provided to error rate calculator 312. In one embodiment, error rate calculator 312 determines a bit error rate for link 306. In other embodiments, error rate calculator 312 provides any other appropriate measure of the error rate.

[0034] Sequence generator 308 is self-synchronized to sequence generator 302 by self-synchronization circuitry. This self-synchronization circuitry includes, in one embodiment, comparator 310, bit memory 314 and synchronization monitor 316. Bit memory 314 buffers a selected portion of the sequence received from sequence generator 302. For example, bit memory 314 stores the most recent N bits for a pseudorandom number sequence with 2 &gt;N -1 bits. The size of bit memory 314 is determined by how much information is necessary to be kept in order to deterministically identify the next expected element in the received sequence based on one or more previously received elements. The stored value in bit memory 314 is used to re-seed sequence generator 308 to generate a next expected value when synchronization monitor 316 determines that synchronization has been lost.

[0035] Synchronization monitor 316 uses a synchronization measure to determine when synchronization is lost. In one embodiment, synchronization monitor 316 uses a counter to provide the synchronization measure. This counter is incremented when an element of the received sequence matches an element of the sequence generated by sequence generator 308 as indicated by comparator 310. In one embodiment, the counter is incremented on each match until a selected level is reached. When a received element of the sequence from sequence generator 302 does not match the expected element generated by sequence generator 308, the counter is decremented. In one embodiment, the counter is decremented by two on a mismatch and is incremented by 1 on a match. This is advantageous when the sequence is a bit stream since in an unsynchronized bit stream of ones and zeros a mismatch is as likely as a match. Thus, by decrementing the counter twice as fast as incrementing the counter, it is likely to march toward zero in the face of an unsynchronized bit stream.

[0036] When the counter reaches a selected level, e.g., zero, synchronization monitor 316 determines that the test sequence is not synchronized with the received sequence. Synchronization monitor thus provides a reload signal to sequence generator 308. This causes data from bit memory 314 to be loaded into sequence generator 308 to produce a next expected element for comparator 310 based on one or more recently received elements from sequence generator 302. It is noted that at sequence detector 304, the output of sequence generator 308 is taken from register REG1 (Qo). This is possible since each of the outputs Qi to Q₄ are equivalent sequences, although delayed in time. By selecting Qo as the output value, the values from bit memory 314 can be validly loaded into the registers REG1 to REG4 of sequence generator 308 to produce the expected next value for the sequence.

III. Communication System Embodiment [0037] Figure 4 is a block diagram of another embodiment of a system, indicated generally at 400, with an error rate monitoring circuit according to the teachings of the present invention. System 400 includes a host communication circuit 402 and a remote communication circuit 404. It is understood that in various embodiments, communication circuits 402 and 404 are implemented as any appropriate communication circuit, e.g., communication circuits for wired, wireless, fiber optic or other communication circuits. Further, in various embodiments, communication circuits 402 and 404 are coupled together over any appropriate communication medium 410, e.g., coaxial cable, fiber optic cable, twisted pair, CAT 5, wireless, infrared, or any other appropriate communication medium.

[0038] Error rate monitoring is accomplished with sequence generator 412 and sequence detector 414. Advantageously, sequence detector 414 is self-synchronized with the sequence generated by sequence generator 412 as described above, for example, with respect any one or more of Figures 1-3. In this embodiment, the sequence used for determining the bit error rate is transmitted across the same communication medium 410 used to communicate traffic between the host communication circuit 402 and the remote communication circuit 404. MUX 406 inserts the sequence into the communication stream between host communication circuit 402 and remote communication circuit 404 such as by inserting bits into a selected bit position, inserting bits into a selected byte or field of a frame, or any other appropriate location in the stream of data sent between host communication circuit 402 and remote communication circuit 404. DEMUX 408 separates out the data for the received sequence and passes this to sequence detector 414.

IN. Method

[0039] Figure 5 is a flow chart that illustrates one method for monitoring an error rate with self-synchronization to a received sequence of data according to the teachings of the present invention. The method begins at block 502 with receiving an element in a sequence of data used to determine the error rate. At block 504, the method determines the expected value for the received element. At block 506, the method determines whether the received element equals the expected element. If so, the method proceeds to block 508.

[0040] At block 508, the method determines whether a SYNC COUNT is less than a maximum value (MAX). If so, then the SYNC COUNT is incremented at 510 and the method returns to 502. If, however, SYNC COUNT is not less than MAX, the method returns to block 502 without incrementing SYNC COUNT. The SYNC COUNT is a measure of the synchronization of the received and generated sequences of data. If the SYNC COUNT is greater than zero, the method presumes that the two sequences are synchronized. If zero, then the method declares a loss of synchronization and action is taken to re-synchronize.

[0041] At block 506, if the two elements are not equal, the method proceeds to block 512. At block 512, the method increments an error count since the two values did not match. The method proceeds to block 514 and determines whether the SYNC COUNT is greater than a minimum value (MIN). If so, the method decrements the SYNC COUNT at block 516 and returns to block 502. If not, then the method determines that synchronization has been lost and reloads the sequence generator based on received elements at block 518 and returns to block 502.