Nova Patents
EP1569348A1

Iterative multidimensional decoding

Abstract

Disclosed is a method for performing an iterative n-dimensional decoding of a data structure comprising a data bit frame. The method comprises the steps of: receiving possibly errored data; computing syndromes in all the n dimensions in a single step; storing the first calculated syndromes; processing syndromes in a first dimension; correcting errors; and updating the syndromes which have been affected by the correction in said first dimension; and processing syndromes in all the possible dimensions up to the n-th one and, for each of the processed syndromes, correcting errors and updating the syndromes in all the dimensions which have been affected by the correction. The time required by each sub-iteration (from second sub-iteration on) will be progressively reduced. The number of iterations is increased without increasing the delay and processing complexity. Processing complexity is reduced because only one circuit is used for processing the syndromes in all the dimensions and for all the iterations.

EP1569348A1, drawing sheet 1
Sheet 1 of 4

Term

Term ended

Projected expiry passed 13 February 2024, 2.6 years ago.

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22 claims: 14 independent, 8 dependent

  1. 1
    A decoder for performing an iterative n -dimensional decoding of a data structure comprising a data bit frame, the decoder comprising:a syndrome calculator (SYND_COMP) for computing syndromes in all the n dimensions in a single step;a syndrome processor (SYND_PROC) for processing the syndromes in 1, 2, ... n dimensions, the syndrome processor comprising storage means (SYND_RAM) for storing the syndromes;and a data processor (DATA_PROC) for storing received data (DATA_RAM_A, DATA_RAM_B), correcting data according to information (11) from the syndrome processor (SYND_CALC, SYND_PROC) and outputting corrected data (DATA_OUT).
  2. 5
    The decoder according to any of previous claims 2-4, wherein the syndrome processor (SYND_PROC) further comprises a sequencer (SEQ_CER) for managing a number of syndrome correction iterations in a preset time interval, said sequencer cooperating (9, 10) with the error calculator (ERR_CALC) and the syndrome storage means (SYND_RAM).
  3. 6
    The decoder according to any of previous claims, wherein the syndrome processor (SYND_PROC) comprises a syndrome multiplexer (SYND_MUX) for switching between an output (4) of the syndrome calculator (SYND_COMP) and an output of the calculator of new syndromes (N_SYND_COMP).
  4. 7
    The decoder according to any of previous claims, wherein the data processor (DATA_PROC) comprises a first memory (DATA_RAM_A) and a second memory (DATA_RAM_B) and an output multiplexer (MUX_OUT) switching between said first or second memories.
  5. 9
    The decoder according to any of previous claims, wherein the syndrome processor (SYND_PROC) processes the syndromes for 1, 2, ..., m iterations.
  6. 10
    The decoder according to any of previous claims, wherein only one circuit is used to process the syndromes in all the dimensions and for all the iterations.
  7. 11
    The decoder according to any of previous claims, wherein it operates in two dimensions.
  8. 12
    The decoder according to any of previous claims, wherein it is embodied in an application-specific integrated circuit.
  9. 13
    A method for performing an iterative n -dimensional decoding of a data structure comprising a data bit frame, the method comprising the steps of:- receiving possibly errored data (100);- computing syndromes (101) in all the n dimensions in a single step;- storing (102) the first calculated syndromes;- processing syndromes (103) in a first dimension;correcting errors;and updating the syndromes which have been affected by the correction in said first dimension;and - processing syndromes (104) in all the possible dimensions up to the n-th one and, for each of the processed syndromes, correcting errors and updating the syndromes in all the dimensions which have been affected by the correction.
  10. 15
    The method according claim 13 or 14, wherein the syndromes are processed for 1, 2, ..., m iterations.
  11. 16
    The method according to any of claims 13-15, wherein only one circuit is used to process the syndromes in all the dimensions and for all the iterations.
  12. 18
    The method according to any of claims 13-15, wherein n is equal to 2.
  13. 19
    The method according to any of claims 13-16, wherein it is performed by an application-specific integrated circuit.
  14. 20
    A network element comprising a decoder according to any of claims 1-12.